coreboot September 2008

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r3596 build service
by coreboot information 24 Sep '08

24 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3596 to the coreboot source repository and caused the following changes: Change Log: Add abuild support for the dbm690t. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3596&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3596&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3596&device=epia-cn&vendor… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3596 - trunk/coreboot-v2/targets/amd/dbm690t
by svn＠coreboot.org 24 Sep '08

24 Sep '08

Author: mjones Date: 2008-09-24 05:21:55 +0200 (Wed, 24 Sep 2008) New Revision: 3596 Added: trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb Log: Add abuild support for the dbm690t. (trivial) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Added: trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb (rev 0) +++ trunk/coreboot-v2/targets/amd/dbm690t/Config-abuild.lb 2008-09-24 03:21:55 UTC (rev 3596) @@ -0,0 +1,28 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=1024*1024 +romimage "normal" + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-normal" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x20000 + option COREBOOT_EXTRA_VERSION=".0-failover" +end + +buildrom ./coreboot.rom ROM_SIZE "normal" "failover"

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r3595 build service
by coreboot information 24 Sep '08

24 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3595 to the coreboot source repository and caused the following changes: Change Log: This patch adds support for watchdog kill and adds it to Asus M2V-MX SE. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Marc Jones <marc.jones(a)amd.com> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3595&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3595&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3595&device=epia-cn&vendor… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3594 build service
by coreboot information 23 Sep '08

23 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3594 to the coreboot source repository and caused the following changes: Change Log: The AMD dbm690t mainboard uses the it8712f SIO with the default 48MHz clock input. The Asus a8n_e uses the it8712f with a 24MHz clock input. The it8712f early init code was setting a 24MHz input clock(to support the a8n_e). Since 48Mhz is the default I added a function to set 24MHz input clock to the a8n_e. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3594&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3594&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3594&device=epia-cn&vendor… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3593 build service
by coreboot information 23 Sep '08

23 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3593 to the coreboot source repository and caused the following changes: Change Log: Attached patch removes HPET info from ACPI tables. HPET does not work fine on VT8237R (random keyboard/mouse lockups). Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3593&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3593&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3593&device=epia-cn&vendor… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3591 build service
by coreboot information 23 Sep '08

23 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ruik" checked in revision 3591 to the coreboot source repository and caused the following changes: Change Log: Following patch adds support for Asus M2V-E SE. Works pretty well, the only problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers recently released, maybe with OpenChrome too. It wont work with the little patch which will hop in soon Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3591&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3591&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3591&device=epia-cn&vendor… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

4 4

r3595 - in trunk/coreboot-v2/src: mainboard/asus/m2v-mx_se superio/ite/it8712f
by svn＠coreboot.org 23 Sep '08

23 Sep '08

Author: ruik Date: 2008-09-24 00:26:27 +0200 (Wed, 24 Sep 2008) New Revision: 3595 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c Log: This patch adds support for watchdog kill and adds it to Asus M2V-MX SE. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-09-23 22:19:27 UTC (rev 3594) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2008-09-23 22:26:27 UTC (rev 3595) @@ -157,6 +157,7 @@ sio_init(); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_kill_watchdog(); uart_init(); console_init(); enable_rom_decode(); @@ -226,6 +227,7 @@ sio_init(); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); + it8712f_kill_watchdog(); uart_init(); console_init(); enable_rom_decode(); Modified: trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c 2008-09-23 22:19:27 UTC (rev 3594) +++ trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c 2008-09-23 22:26:27 UTC (rev 3595) @@ -32,6 +32,7 @@ #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ #define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ +#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ #define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ @@ -77,6 +78,16 @@ } +static void it8712f_kill_watchdog(void) +{ + it8712f_enter_conf(); + + /* Kill the Watchdog */ + it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00); + + it8712f_exit_conf(); +} + /* Enable the peripheral devices on the IT8712F Super I/O chip. */ static void it8712f_enable_serial(device_t dev, unsigned iobase) {

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r3594 - in trunk/coreboot-v2/src: mainboard/asus/a8n_e superio/ite/it8712f
by svn＠coreboot.org 23 Sep '08

23 Sep '08

Author: mjones Date: 2008-09-24 00:19:27 +0200 (Wed, 24 Sep 2008) New Revision: 3594 Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c Log: The AMD dbm690t mainboard uses the it8712f SIO with the default 48MHz clock input. The Asus a8n_e uses the it8712f with a 24MHz clock input. The it8712f early init code was setting a 24MHz input clock(to support the a8n_e). Since 48Mhz is the default I added a function to set 24MHz input clock to the a8n_e. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2008-09-23 21:57:33 UTC (rev 3593) +++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2008-09-23 22:19:27 UTC (rev 3594) @@ -221,6 +221,7 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } + it8712f_24mhz_clkin(); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); Modified: trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c 2008-09-23 21:57:33 UTC (rev 3593) +++ trunk/coreboot-v2/src/superio/ite/it8712f/it8712f_early_serial.c 2008-09-23 22:19:27 UTC (rev 3594) @@ -45,10 +45,10 @@ outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8712F Super I/O chip. */ -static void it8712f_enable_serial(device_t dev, unsigned iobase) + +static void it8712f_enter_conf(void) { - /* (1) Enter the configuration state (MB PnP mode). */ + /* Enter the configuration state (MB PnP mode). */ /* Perform MB PnP setup to put the SIO chip at 0x2e. */ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ @@ -57,7 +57,33 @@ outb(0x01, IT8712F_CONFIGURATION_PORT); outb(0x55, IT8712F_CONFIGURATION_PORT); outb(0x55, IT8712F_CONFIGURATION_PORT); +} +static void it8712f_exit_conf(void) +{ + /* Exit the configuration state (MB PnP mode). */ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); +} + + +static void it8712f_24mhz_clkin(void) +{ + it8712f_enter_conf(); + + /* Select 24MHz CLKIN (48MHZ default)*/ + it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); + + it8712f_exit_conf(); + +} + +/* Enable the peripheral devices on the IT8712F Super I/O chip. */ +static void it8712f_enable_serial(device_t dev, unsigned iobase) +{ + + /* (1) Enter the configuration state (MB PnP mode). */ + it8712f_enter_conf(); + /* (2) Modify the data of configuration registers. */ /* Select the chip to configure (if there's more than one). @@ -69,13 +95,9 @@ it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ - /* Select 24MHz CLKIN (set bit 0). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x01); - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ /* (3) Exit the configuration state (MB PnP mode). */ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); + it8712f_exit_conf(); } -

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r234 - in buildrom-devel: bin config/platforms packages/coreboot-v2
by svn＠coreboot.org 23 Sep '08

23 Sep '08

Author: jcrouse Date: 2008-09-24 00:15:47 +0200 (Wed, 24 Sep 2008) New Revision: 234 Added: buildrom-devel/bin/construct-rom.sh Modified: buildrom-devel/config/platforms/dbm690t.conf buildrom-devel/config/platforms/platforms.conf buildrom-devel/packages/coreboot-v2/coreboot.inc Log: buildrom: Add script to automatically pad ROMs Many ROMs may need to be padded before use. This script tries to do this somewhat automatically. If the platform needs the payload to be padded to a power of 2, then it should set PAYLOAD_DOPAD to '-p'. Otherwise, the script behaves as it normally does. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Ward Vandewege <ward(a)gnu.org> Added: buildrom-devel/bin/construct-rom.sh =================================================================== --- buildrom-devel/bin/construct-rom.sh (rev 0) +++ buildrom-devel/bin/construct-rom.sh 2008-09-23 22:15:47 UTC (rev 234) @@ -0,0 +1,51 @@ +#!/bin/sh -e +# Usage: ./construct-rom.sh [-p] components ... + +DOPAD=0 + +if [ "$1" == "-p" ]; then + DOPAD=1 + shift +fi + +COMPONENTS=$* + +if [ $DOPAD -eq 1 ]; then + + ROMSIZE=0 + + # Get the size of all the components together + + for c in $COMPONENTS; do + size=`du -b $c | cut -f1` + ROMSIZE=`expr $ROMSIZE + $size` || true + done + + # Pad to a power of 2, starting with 128k + RSIZE=131072 + + while true; do + PAD=0 + + if [ $ROMSIZE -gt $RSIZE ]; then + RSIZE=`expr $RSIZE "*" 2` + continue + fi + + if [ $ROMSIZE -lt $RSIZE ]; then + PAD=`expr $RSIZE - $ROMSIZE` + fi + + break + done + + PADFILE=`mktemp` + dd if=/dev/zero of=$PADFILE bs=1 count=$PAD > /dev/null 2>&1 + COMPONENTS="$PADFILE $COMPONENTS" +fi + +cat $COMPONENTS + +if [ $DOPAD -eq 1 ]; then + rm -rf $PADFILE +fi Modified: buildrom-devel/config/platforms/dbm690t.conf =================================================================== --- buildrom-devel/config/platforms/dbm690t.conf 2008-09-23 22:02:55 UTC (rev 233) +++ buildrom-devel/config/platforms/dbm690t.conf 2008-09-23 22:15:47 UTC (rev 234) @@ -51,6 +51,9 @@ CBV2_TDIR=dbm690t CBV2_TAG=3590 +# Tell construct-rom.sh to pad the ROM to a power of 2 +PLATFORM_DOPAD := -p + # FILO configuration FILO_CONFIG=dbm690t-Config Modified: buildrom-devel/config/platforms/platforms.conf =================================================================== --- buildrom-devel/config/platforms/platforms.conf 2008-09-23 22:02:55 UTC (rev 233) +++ buildrom-devel/config/platforms/platforms.conf 2008-09-23 22:15:47 UTC (rev 234) @@ -6,6 +6,11 @@ STRIP=strip AS=as +# Each individual platform needs to decide if they want to pad the +# ROM or not + +PLATFORM_DOPAD := + ##Include the correct platform configuration PLATFORM-y= Modified: buildrom-devel/packages/coreboot-v2/coreboot.inc =================================================================== --- buildrom-devel/packages/coreboot-v2/coreboot.inc 2008-09-23 22:02:55 UTC (rev 233) +++ buildrom-devel/packages/coreboot-v2/coreboot.inc 2008-09-23 22:15:47 UTC (rev 234) @@ -150,7 +150,7 @@ $(OUTPUT_DIR)/$(TARGET_ROM): $(CBV2_COMPONENTS) @ mkdir -p $(OUTPUT_DIR) - @ cat $(CBV2_COMPONENTS) > $@ + @ $(BIN_DIR)/construct-rom.sh $(PLATFORM_DOPAD) $(CBV2_COMPONENTS) > $@ generic-coreboot: $(OUTPUT_DIR)/$(TARGET_ROM)

1 0

r3592 build service
by coreboot information 23 Sep '08

23 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "oxygene" checked in revision 3592 to the coreboot source repository and caused the following changes: Change Log: 1. Preset CC to gcc in Makefile. There are some $(shell $(CC) ...) invocations with GCC specific options, so that shouldn't hurt. 2. Replace stdbool.h include in util/kconfig/expr.h by a custom implementation of booleans. This is okay as these booleans are purely internal. It's necessary because there's some disagreement between the Solaris headers and GCC on Solaris, about when stdbool.h is appropriate. 3. Remove stdbool.h include from util/kconfig/zconf.tab.c_shipped. This file includes expr.h already, so it picks up the right set of primitives, without duplicating the special case for Solaris. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of amd:dbm690t is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3592&device=dbm690t&vendor… Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3592&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3592&device=epia-cn&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot September 2008