coreboot September 2008

coreboot@coreboot.org

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415 discussions

r868 - in coreboot-v3: arch/x86/amd/k8 arch/x86/amd/model_fxx include/arch/x86 include/arch/x86/amd/k8 mainboard/amd/serengeti southbridge/amd/amd8111
by svn＠coreboot.org 19 Sep '08

19 Sep '08

Author: rminnich Date: 2008-09-19 20:35:22 +0200 (Fri, 19 Sep 2008) New Revision: 868 Modified: coreboot-v3/arch/x86/amd/k8/stage1.c coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c coreboot-v3/include/arch/x86/amd/k8/k8.h coreboot-v3/include/arch/x86/cpu.h coreboot-v3/mainboard/amd/serengeti/Makefile coreboot-v3/mainboard/amd/serengeti/initram.c coreboot-v3/mainboard/amd/serengeti/mainboard.h coreboot-v3/southbridge/amd/amd8111/stage1_reset.c coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c Log: substantial cleanups for k8. AMP TinyGX still builds, this won't affect other platforms. clean up 8111 stage1 code; add function to smbus, memreset_setup_amd8111, for the 8111 specific parts of memreset. include k8 .h to reduce warnings. Turn some things into functions (romcc legacy cleanup) and put them in .c files. simnow actually successfully gets through a reset cycle now. Next is to fix the fidvid code. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/k8/stage1.c =================================================================== --- coreboot-v3/arch/x86/amd/k8/stage1.c 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/arch/x86/amd/k8/stage1.c 2008-09-19 18:35:22 UTC (rev 868) @@ -28,6 +28,16 @@ #include <amd/k8/k8.h> /** + * Set the MTRR for initial ram access. + * be warned, this will be used by core other than core 0/node 0 or core0/node0 when cpu_reset. + * This warning has some significance I don't yet understand. + */ +void set_init_ram_access(void) +{ + set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); +} + +/** * Disable Cache As RAM (CAR) after memory is setup. * * Unknown how to do this just yet. @@ -60,5 +70,7 @@ [carsizequads] "i" (CONFIG_CARSIZE/4) : "memory", "%edi", "%esi", "%ecx"); banner(BIOS_DEBUG, "Disable_car: done wbinvd"); + /* we're now running in ram. Although this will be called again, it does no harm to call it here. */ + set_init_ram_access(); banner(BIOS_DEBUG, "disable_car: done"); } Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c =================================================================== --- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-09-19 18:35:22 UTC (rev 868) @@ -246,11 +246,33 @@ } } +/** + * disable cache as ram on a BSP. + * For reasons not totally known we are saving ecx and edx. + * That will work on k8 as we copy the stack and return in the same stack frame. + */ +void disable_cache_as_ram_bsp(void) +{ + __asm__ volatile ( +// "pushl %eax\n\t" + "pushl %edx\n\t" + "pushl %ecx\n\t" + ); + + disable_cache_as_ram(); + __asm__ volatile ( + "popl %ecx\n\t" + "popl %edx\n\t" +// "popl %eax\n\t" + ); +} + + /** * wait for all apics to start. Make sure we don't wait on ourself. * @param bsp_apicid The BSP APIC ID */ -static void wait_all_aps_started(unsigned bsp_apicid) +void wait_all_aps_started(unsigned bsp_apicid) { for_each_ap(bsp_apicid, 0, wait_ap_started, (void *) 0); } Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h =================================================================== --- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-09-19 18:35:22 UTC (rev 868) @@ -743,23 +743,8 @@ ); } -static void disable_cache_as_ram_bsp(void) -{ - __asm__ volatile ( -// "pushl %eax\n\t" - "pushl %edx\n\t" - "pushl %ecx\n\t" - ); +void disable_cache_as_ram_bsp(void); - disable_cache_as_ram(); - __asm__ volatile ( - "popl %ecx\n\t" - "popl %edx\n\t" -// "popl %eax\n\t" - ); -} - - #endif /* ! ASSEMBLY */ #endif /* AMD_K8_H */ Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/include/arch/x86/cpu.h 2008-09-19 18:35:22 UTC (rev 868) @@ -243,14 +243,8 @@ } -/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/ -static void set_init_ram_access(void) -{ - set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); -} +void set_init_ram_access(void); - - void * bottom_of_stack(void); EXPORT_SYMBOL(bottom_of_stack); struct global_vars * global_vars(void); Modified: coreboot-v3/mainboard/amd/serengeti/Makefile =================================================================== --- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-09-19 18:35:22 UTC (rev 868) @@ -23,6 +23,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(src)/arch/x86/stage1_mtrr.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ $(src)/southbridge/amd/amd8111/stage1_ctrl.c \ $(src)/southbridge/amd/amd8111/stage1_enable_rom.c \ Modified: coreboot-v3/mainboard/amd/serengeti/initram.c =================================================================== --- coreboot-v3/mainboard/amd/serengeti/initram.c 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/mainboard/amd/serengeti/initram.c 2008-09-19 18:35:22 UTC (rev 868) @@ -51,14 +51,21 @@ #define DIMM6 0x56 #define DIMM7 0x57 -# warning fix hard_reset -void hard_reset(void) +/* this code is very mainboard dependent, sadly. */ +/** + * call the amd 8111 memreset_setup_amd8111 function to jam the GPIOs to reset memory. + */ +static void memreset_setup(void) { + void memreset_setup_amd8111(u8 data, u16 offset); + //GPIO on amd8111 to enable MEMRST ???? + memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0xc0 + 16); //REVC_MEMRST_EN=1 + memreset_setup_amd8111((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0xc0 + 17); } -void memreset_setup(void) -{ -} +/** + * this is a no op on this platform. + */ void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -66,25 +73,30 @@ void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int smbus_write_byte(u16 device, u16 address, u8 val); - int ret,i; - u16 device=(ctrl->channel0[0])>>8; - /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ - i=2; - do { - ret = smbus_write_byte(SMBUS_HUB, 0x01, device); - } while ((ret!=0) && (i-->0)); + int smbus_write_byte(u16 device, u16 address, u8 val); + int ret, i; + u16 device = (ctrl->channel0[0]) >> 8; + /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time */ + i = 2; + do { + ret = smbus_write_byte(SMBUS_HUB, 0x01, device); + } while ((ret != 0) && (i-- > 0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); + smbus_write_byte(SMBUS_HUB, 0x03, 0); } +/** + * read a byte from spd. + * @param device device to read from + * @param address address in the spd ROM + * @return the value of the byte at that address. + */ u8 spd_read_byte(u16 device, u8 address) { int smbus_read_byte(u16 device, u16 address); - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); } - /** * main for initram for the AMD Serengeti * @param init_detected Used to indicate that we have been started via init @@ -113,30 +125,33 @@ */ void enable_smbus(void); void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); + void soft_reset_x(unsigned sbbusn, unsigned sbdn); u32 init_detected; static const u16 spd_addr[] = { - //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + //first node + RC0 | DIMM0, RC0 | DIMM2, 0, 0, + RC0 | DIMM1, RC0 | DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, - RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, + //second node + RC1 | DIMM0, RC1 | DIMM2, RC1 | DIMM4, RC1 | DIMM6, + RC1 | DIMM1, RC1 | DIMM3, RC1 | DIMM5, RC1 | DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 - // third node - RC2|DIMM0, RC2|DIMM2, 0, 0, - RC2|DIMM1, RC2|DIMM3, 0, 0, - // four node - RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, - RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, + // third node + RC2 | DIMM0, RC2 | DIMM2, 0, 0, + RC2 | DIMM1, RC2 | DIMM3, 0, 0, + // four node + RC3 | DIMM0, RC3 | DIMM2, RC3 | DIMM4, RC3 | DIMM6, + RC3 | DIMM1, RC3 | DIMM3, RC3 | DIMM5, RC3 | DIMM7, #endif }; struct sys_info *sysinfo; - int needs_reset; int i; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; + struct msr msr; + printk(BIOS_DEBUG, "Hi there from stage1\n"); post_code(POST_START_OF_MAIN); sysinfo = &(global_vars()->sys_info); @@ -146,116 +161,91 @@ */ bsp_apicid = init_cpus(init_detected, sysinfo); -// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); #if MEM_TRAIN_SEQ == 1 - set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif - setup_coherent_ht_domain(); // routing table and start other core0 + setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 - // It is said that we should start core1 after all core0 launched + // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ - start_all_cores(); + start_all_cores(); wait_all_other_cores_started(bsp_apicid); #endif - + /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if K8_SET_FIDVID == 1 + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", + msr.hi, msr.lo); - { - struct msr msr; - msr=rdmsr(FIDVID_STATUS); - printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", msr.hi ,msr.lo); - - } - enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); + init_fidvid_bsp(bsp_apicid); - // show final fid and vid - { - struct msr msr; - msr=rdmsr(FIDVID_STATUS); - printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", msr.hi ,msr.lo); + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", + msr.hi, msr.lo); - } -#endif - #if 1 needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); - // fidvid change will issue one LDTSTOP and the HT change will be effective too - if (needs_reset) { - printk(BIOS_INFO, "ht reset -\r\n"); -#warning define soft_reset_x -//FIXME soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); - } + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\r\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } #endif allow_all_aps_stop(bsp_apicid); - //It's the time to set ctrl in sysinfo now; + //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); -#if 0 - for(i=0;i<4;i++) { - activate_spd_rom(&cpu[i]); - dump_smbus_registers(); - } -#endif - -#if 0 - for(i=1;i<256;i<<=1) { - change_i2c_mux(i); - dump_smbus_registers(); - } -#endif - memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output - /* all ap stopped? */ + /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 - print_pci_devices(); + print_pci_devices(); #endif #if 0 // dump_pci_devices(); - dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif #warning re-implement post_cache_as_ram - // post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + // post_cache_as_ram(); // bsp switch stack to ram and copy sysinfo ram now printk(BIOS_DEBUG, "stage1 returns\n"); return 0; Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h =================================================================== --- coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-09-19 18:35:22 UTC (rev 868) @@ -33,12 +33,6 @@ #define SB_HT_CHAIN_UNITID_OFFSET_ONLY 1 #define ENABLE_APIC_EXT_ID 0 #define LIFT_BSP_APIC_ID 1 -#warning clean up confusion on FIDVID. v2 was inconsistent. -/* In v2 there is confusion on the settings of these. - * The serengeti config sets it to zero. - * In the model_fxx support it is hardwired to 1. - * We'll assume that setting it to 1 is ok. - */ #define K8_SET_FIDVID 1 /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, * so may don't need to do twice */ Modified: coreboot-v3/southbridge/amd/amd8111/stage1_reset.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_reset.c 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/southbridge/amd/amd8111/stage1_reset.c 2008-09-19 18:35:22 UTC (rev 868) @@ -30,7 +30,10 @@ void hard_reset(void) { - u32 dev; + void set_bios_reset(void); + unsigned get_sblk(void); + u8 node_link_to_bus(unsigned int node, unsigned int link); + u32 busdevfn; unsigned int bus; unsigned int node = 0; unsigned int link = get_sblk(); @@ -39,9 +42,9 @@ * There can only be one 8111 on a hypertransport chain/bus. */ bus = node_link_to_bus(node, link); - pci_locate_device_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA, &dev); + pci_conf1_find_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA, &busdevfn); /* Reset */ set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + pci_conf1_write_config8(busdevfn, 0x47, 1); } Modified: coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c 2008-09-18 16:45:46 UTC (rev 867) +++ coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c 2008-09-19 18:35:22 UTC (rev 868) @@ -305,3 +305,17 @@ return smbus_read_byte(device, address); } +/** + * memreset_setup_amd8111 + * This function is part of a complex dance played between the mainboard and + * the southbridge. We don't want to export SMBUS_IO_BASE, but neither can the + * amd8111 know about what GPIOs connect to what reset lines. So + * we split the difference. The mainboard must call this function with bytes + * to be output to accomplish reset, as well as the offset from IOBASE; + * amd8111 will output those bytes to SMBIOS_IOBASE. + * The caller of this function must have called spd_init for it to work correctly. + */ +void memreset_setup_amd8111(u8 data, u16 offset) +{ + outb(data, SMBUS_IO_BASE + offset); +}

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v2: Two coding issues: asm invd, pci resources
by Mats Erik Andersson 19 Sep '08

19 Sep '08

Hello folks, I have two questions for the code base in coreboot-v2. 1) In an effort to understand how the L2 cache in a PII processor can be activated, I wished to use the machine instruction 'invd'. It is implemented in src/include/cpu/x86/cache.h, but does not even compile as it stands. I had to remove that inexplicable addition '::: "memory"' in order to compile a rom image: static inline void invd(void) { /* asm volatile("invd" ::: "memory"); */ asm volatile("invd"); } I have never seen the attribute before, so I wonder if it is some kind of safe guard. Anyway, my idea was to use static inline void enable_cache(void) { unsigned long cr0; cr0 = read_cr0(); cr0 &= 0x9fffffff; invd(); /* NEW */ write_cr0(cr0); wbinvd(); /* NEW */ } since 'the Programmer's Guide vol. 3A/3B' gives no clues on methods for activating the L2 cache. However, nothing improved. 2) Has it been judged superfluous to support configuration entries such as device pci 7.2 on # USB io 0x20 = 0x0000e001ul irq 0x3c = 0x0a end on grounds that pci-devices _can_ do auto detection? I inserted two instances of 'print_debug' to make sure that pci_set_resources() is executed for the USB Host Controler, but the above specification never came into action. Were they even parsed? Kind regards Mats Erik Andersson

2 1

k8 status: it speaks for itself
by ron minnich 18 Sep '08

18 Sep '08

CPU 804 Mhz Etherboot 5.4.3 (GPL) http://etherboot.org Drivers: VIA-VELOCITY/PCI Images: ELF Protocols: DHCP TFTP Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000) Boot from (N)etwork or (Q)uit? Probing pci nic... Probing isa nic... <sleep> I've committed the last set of changes which mainly consist of fixing a null pointer bug that I believe is in v2. Next steps are to better fill out the dts, and start working on the warnings etc. I get. ron

2 2

r3584 build service
by coreboot information 18 Sep '08

18 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3584 to the coreboot source repository and caused the following changes: Change Log: ck804 whitespace fixes Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3584&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3584&device=epia-cn&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r867 - in coreboot-v3: mainboard/amd/serengeti northbridge/amd/k8
by svn＠coreboot.org 18 Sep '08

18 Sep '08

Author: rminnich Date: 2008-09-18 18:45:46 +0200 (Thu, 18 Sep 2008) New Revision: 867 Modified: coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/pci.c Log: This set of changes adds new nodes to dts that are required, adds some prints, and fixes a null pointer deref bug that has been in the k8 code since the dawn of time. We get here: CPU 804 Mhz Etherboot 5.4.3 (GPL) http://etherboot.org Drivers: VIA-VELOCITY/PCI Images: ELF Protocols: DHCP TFTP Relocating _text from: [000100e0,000349c0) to [0007b720,000a0000) Boot from (N)etwork or (Q)uit? Probing pci nic... Probing isa nic... <sleep> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2008-09-17 16:38:16 UTC (rev 866) +++ coreboot-v3/mainboard/amd/serengeti/dts 2008-09-18 16:45:46 UTC (rev 867) @@ -50,6 +50,9 @@ pci@2,0{ }; }; + pci@18,1 {}; + pci@18,2 {}; + pci@18,3 {}; ioport@2e { /config/("superio/winbond/w83627hf/dts"); com1enable = "1"; Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2008-09-17 16:38:16 UTC (rev 866) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-09-18 16:45:46 UTC (rev 867) @@ -52,8 +52,6 @@ #define FX_DEVS 8 extern struct device * __f0_dev[FX_DEVS]; -extern struct device * __f1_dev[FX_DEVS]; -void debug_fx_devs(void); void get_fx_devs(void); u32 f1_read_config32(unsigned int reg); void f1_write_config32(unsigned int reg, u32 value); @@ -163,6 +161,7 @@ IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); #endif + printk(BIOS_DEBUG, "k8_pci_domain_read_resources done\n"); } static void k8_pci_domain_set_resources(struct device * dev) Modified: coreboot-v3/northbridge/amd/k8/pci.c =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c 2008-09-17 16:38:16 UTC (rev 866) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-09-18 16:45:46 UTC (rev 867) @@ -48,9 +48,6 @@ #define FX_DEVS 8 extern struct device * __f0_dev[FX_DEVS]; -extern struct device * __f1_dev[FX_DEVS]; -void debug_fx_devs(void); -void get_fx_devs(void); u32 f1_read_config32(unsigned int reg); void f1_write_config32(unsigned int reg, u32 value); unsigned int amdk8_nodeid(struct device * dev); @@ -66,7 +63,7 @@ unsigned max_bus; unsigned min_bus; unsigned max_devfn; - + printk(BIOS_SPEW, "amdk8_scan_chain\n"); dev->link[link].cap = 0x80 + (link *0x20); do { link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); @@ -201,6 +198,7 @@ } + printk(BIOS_SPEW, "amdk8_scan_chain done\n"); return max; } @@ -244,7 +242,7 @@ return max; } - +#warning document this unreadable function reg_useable static int reg_useable(unsigned reg, struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) { @@ -252,9 +250,12 @@ unsigned nodeid, link; int result; res = 0; +#warning fix hard-coded 8 in for loop. for(nodeid = 0; !res && (nodeid < 8); nodeid++) { struct device * dev; dev = __f0_dev[nodeid]; + if (! dev) + continue; for(link = 0; !res && (link < 3); link++) { res = probe_resource(dev, 0x100 + (reg | link)); } @@ -379,9 +380,11 @@ nodeid = amdk8_nodeid(dev); for(link = 0; link < dev->links; link++) { if (dev->link[link].children) { + printk(BIOS_DEBUG, "amdk8_read_resources link %d\n", link); amdk8_link_read_bases(dev, nodeid, link); } } + printk(BIOS_DEBUG, "amdk8_read_resources done\n"); } static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid)

1 0

r228 - in buildrom-devel: . packages/memtest
by svn＠coreboot.org 18 Sep '08

18 Sep '08

Author: jcrouse Date: 2008-09-18 18:30:48 +0200 (Thu, 18 Sep 2008) New Revision: 228 Modified: buildrom-devel/Makefile buildrom-devel/packages/memtest/memtest.mk Log: buildrom: Fix makefile flags and other issues affecting memtest memtest depends on implicit makefile rules, so remove -rR from the MAKEFLAGS and stick the $(STACKPROTECT) variable into the CC variable. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/Makefile =================================================================== --- buildrom-devel/Makefile 2008-09-18 16:29:48 UTC (rev 227) +++ buildrom-devel/Makefile 2008-09-18 16:30:48 UTC (rev 228) @@ -11,7 +11,7 @@ CONFIG_SHELL := sh KBUILD_DEFCONFIG := scripts/defconfig UNAME_RELEASE := $(shell uname -r) -MAKEFLAGS += -rR --no-print-directory +MAKEFLAGS += --no-print-directory # Make is silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) Modified: buildrom-devel/packages/memtest/memtest.mk =================================================================== --- buildrom-devel/packages/memtest/memtest.mk 2008-09-18 16:29:48 UTC (rev 227) +++ buildrom-devel/packages/memtest/memtest.mk 2008-09-18 16:30:48 UTC (rev 228) @@ -36,7 +36,7 @@ $(MEMTEST_SRC_DIR)/memtest: $(MEMTEST_CONFIG_TARGET) @ echo "Building memtest..." - @ $(MAKE) -C $(MEMTEST_SRC_DIR) AS="$(AS) $(CROSS_ASFLAGS)" CC="$(CC) $(CROSS_CFLAGS)" LD="$(LD) $(CROSS_LDFLAGS)" CFLAGS="$(CFLAGS)" memtest > $(MEMTEST_BUILD_LOG) 2>&1 + @ $(MAKE) -C $(MEMTEST_SRC_DIR) AS="$(AS) $(CROSS_ASFLAGS)" CC="$(CC) $(CROSS_CFLAGS) $(STACKPROTECT)" LD="$(LD) $(CROSS_LDFLAGS)" CFLAGS="$(CFLAGS)" memtest > $(MEMTEST_BUILD_LOG) 2>&1 $(MEMTEST_STAMP_DIR) $(MEMTEST_LOG_DIR): @ mkdir -p $@

1 0

r227 - in buildrom-devel/packages: filo libpayload
by svn＠coreboot.org 18 Sep '08

18 Sep '08

Author: jcrouse Date: 2008-09-18 18:29:48 +0200 (Thu, 18 Sep 2008) New Revision: 227 Modified: buildrom-devel/packages/filo/filo.mk buildrom-devel/packages/libpayload/libpayload.mk Log: buildrom: Update FILO to latest Update FILO and libpayload to latest revisions per Stefan. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/filo/filo.mk =================================================================== --- buildrom-devel/packages/filo/filo.mk 2008-09-12 17:18:00 UTC (rev 226) +++ buildrom-devel/packages/filo/filo.mk 2008-09-18 16:29:48 UTC (rev 227) @@ -1,5 +1,5 @@ FILO_URL=svn://coreboot.org/filo/trunk/filo -FILO_TAG=62 +FILO_TAG=63 FILO_DIR=$(BUILD_DIR)/filo FILO_SRC_DIR=$(FILO_DIR)/svn Modified: buildrom-devel/packages/libpayload/libpayload.mk =================================================================== --- buildrom-devel/packages/libpayload/libpayload.mk 2008-09-12 17:18:00 UTC (rev 226) +++ buildrom-devel/packages/libpayload/libpayload.mk 2008-09-18 16:29:48 UTC (rev 227) @@ -1,5 +1,5 @@ LIBPAYLOAD_URL=svn://coreboot.org/repos/trunk/payloads/libpayload -LIBPAYLOAD_TAG=3575 +LIBPAYLOAD_TAG=3583 LIBPAYLOAD_DIR=$(BUILD_DIR)/libpayload LIBPAYLOAD_SRC_DIR=$(LIBPAYLOAD_DIR)/svn

1 0

r3584 - trunk/coreboot-v2/src/southbridge/nvidia/ck804
by svn＠coreboot.org 18 Sep '08

18 Sep '08

Author: myles Date: 2008-09-18 18:27:00 +0200 (Thu, 18 Sep 2008) New Revision: 3584 Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc Log: ck804 whitespace fixes Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -21,9 +21,9 @@ device_t lpc_dev; lpc_dev = dev_find_slot(dev->bus->secondary, devfn); - + if ( !lpc_dev ) return lpc_dev; - + if ((lpc_dev->vendor != PCI_VENDOR_ID_NVIDIA) || ( (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_LPC) && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) && @@ -37,7 +37,7 @@ lpc_dev = 0; } } - + return lpc_dev; } @@ -114,7 +114,7 @@ index = 15; break; case PCI_DEVICE_ID_NVIDIA_CK804_PCI_E: - devfn -= (0xa<<3); + devfn -= (0xa<<3); index2 = 19; break; default: @@ -147,23 +147,21 @@ } - lpc_dev = find_lpc_dev(dev, devfn); + lpc_dev = find_lpc_dev(dev, devfn); if ( !lpc_dev ) return; - if ( index == 0) { + if ( index == 0) { final_reg = pci_read_config32(lpc_dev, 0xe8); final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<10)|(1<<12)|(1<<13)|(1<<14)|(1<<22)|(1<<18)|(1<<15)); pci_write_config32(lpc_dev, 0xe8, final_reg); -#if 1 reg_old = reg = pci_read_config32(lpc_dev, 0xe4); - reg |= (1<<20); + reg |= (1<<20); if (reg != reg_old) { pci_write_config32(lpc_dev, 0xe4, reg); } -#endif byte = pci_read_config8(lpc_dev, 0x74); byte |= ((1<<1)); @@ -185,7 +183,7 @@ reg_old = pci_read_config32(lpc_dev, 0xe8); if (final_reg != reg_old) { pci_write_config32(lpc_dev, 0xe8, final_reg); - } + } } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -4,31 +4,31 @@ */ static int set_ht_link_ck804(uint8_t ht_c_num) { - unsigned vendorid = 0x10de; - unsigned val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); + unsigned vendorid = 0x10de; + unsigned val = 0x01610169; + return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) { - int i; + int i; unsigned val; val = inl(control); val &= 0xfffffffe; - outl(val, control); + outl(val, control); - outl(0, index); + outl(0, index); - for(i = 0; i < max; i++) { - unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); + for(i = 0; i < max; i++) { + unsigned long reg; + reg = register_values[i]; + outl(reg, where); + } + val = inl(control); + val |= 1; + outl(val, control); } @@ -40,11 +40,11 @@ #define SYSCTRL_REG_POS 0x64 /* - 16 1 1 2 :0 - 8 8 2 2 :1 - 8 8 4 :2 - 8 4 4 4 :3 - 16 4 :4 + 16 1 1 2 :0 + 8 8 2 2 :1 + 8 8 4 :2 + 8 4 4 4 :3 + 16 4 :4 */ #ifndef CK804_PCI_E_X @@ -54,11 +54,11 @@ #if CK804_NUM > 1 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE+0x8000) #define CK804B_SYSCTRL_IO_BASE (SYSCTRL_IO_BASE+0x8000) - + #ifndef CK804B_BUSN #define CK804B_BUSN 0x80 #endif - + #ifndef CK804B_PCI_E_X #define CK804B_PCI_E_X 4 #endif @@ -75,33 +75,33 @@ #define CK804_CHIP_REV 3 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE + #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE + #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - #define CK804B_DEVN_BASE 1 + #define CK804B_DEVN_BASE 1 #else - #define CK804B_DEVN_BASE CK804_DEVN_BASE + #define CK804B_DEVN_BASE CK804_DEVN_BASE #endif static void ck804_early_set_port(void) { - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + static const unsigned int ctrl_devport_conf[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, #if CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, #endif - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, #if CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), CK804B_SYSCTRL_IO_BASE, #endif - }; - + }; + setup_resource_map(ctrl_devport_conf, sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0])); } @@ -109,18 +109,18 @@ static void ck804_early_clear_port(void) { - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + static const unsigned int ctrl_devport_conf_clear[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, #if CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, #endif - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, #if CK804_NUM > 1 - PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, -#endif - }; - + PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, +#endif + }; + setup_resource_map(ctrl_devport_conf_clear, sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0])); } @@ -128,75 +128,75 @@ static void ck804_early_setup(void) { - static const unsigned int ctrl_conf[] = { + static const unsigned int ctrl_conf[] = { - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, #endif - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, #endif - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, #endif - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, #endif - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, #endif @@ -204,12 +204,12 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), #if CK804_NUM > 1 @@ -223,96 +223,96 @@ #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, #endif - // Activate master port on primary SATA controller - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000, - - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + // Activate master port on primary SATA controller + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000, + + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), #if CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), #endif - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), + RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), #endif #if CK804_USE_ACI == 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), #endif #if CK804_NUM > 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), #endif #if CK804_NUM > 1 #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), #endif -#endif +#endif @@ -320,25 +320,25 @@ CK804_MB_SETUP #endif - }; + }; - + setup_resource_map_x(ctrl_conf, sizeof(ctrl_conf)/sizeof(ctrl_conf[0])); - setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); - setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE+0x40, ANACTRL_IO_BASE+0x44, ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE+0xb0, ANACTRL_IO_BASE+0xb4, ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); + setup_ss_table(ANACTRL_IO_BASE+0xc0, ANACTRL_IO_BASE+0xc4, ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); #if CK804_NUM > 1 - setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64); - setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64); - setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64); + setup_ss_table(CK804B_ANACTRL_IO_BASE+0x40, CK804B_ANACTRL_IO_BASE+0x44, CK804B_ANACTRL_IO_BASE+0x48, pcie_ss_tbl,64); + setup_ss_table(CK804B_ANACTRL_IO_BASE+0xb0, CK804B_ANACTRL_IO_BASE+0xb4, CK804B_ANACTRL_IO_BASE+0xb8, sata_ss_tbl,64); + setup_ss_table(CK804B_ANACTRL_IO_BASE+0xc0, CK804B_ANACTRL_IO_BASE+0xc4, CK804B_ANACTRL_IO_BASE+0xc8, cpu_ss_tbl,64); #endif #if 0 - dump_io_resources(ANACTRL_IO_BASE); - dump_io_resources(SYSCTRL_IO_BASE); + dump_io_resources(ANACTRL_IO_BASE); + dump_io_resources(SYSCTRL_IO_BASE); #endif } @@ -353,20 +353,20 @@ static void hard_reset(void) { - set_bios_reset(); + set_bios_reset(); - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); } static void soft_reset(void) { - set_bios_reset(); + set_bios_reset(); #if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); #endif } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_car.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -6,31 +6,31 @@ static int set_ht_link_ck804(uint8_t ht_c_num) { - unsigned vendorid = 0x10de; - unsigned val = 0x01610169; - return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); + unsigned vendorid = 0x10de; + unsigned val = 0x01610169; + return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) { - int i; + int i; unsigned val; val = inl(control); val &= 0xfffffffe; - outl(val, control); + outl(val, control); - outl(0, index); + outl(0, index); - for(i = 0; i < max; i++) { - unsigned long reg; + for(i = 0; i < max; i++) { + unsigned long reg; - reg = register_values[i]; - outl(reg, where); - } - val = inl(control); - val |= 1; - outl(val, control); + reg = register_values[i]; + outl(reg, where); + } + val = inl(control); + val |= 1; + outl(val, control); } @@ -42,11 +42,11 @@ #define SYSCTRL_REG_POS 0x64 /* - 16 1 1 2 :0 - 8 8 2 2 :1 - 8 8 4 :2 - 8 4 4 4 :3 - 16 4 :4 + 16 1 1 2 :0 + 8 8 2 2 :1 + 8 8 4 :2 + 8 4 4 4 :3 + 16 4 :4 */ #ifndef CK804_PCI_E_X @@ -61,7 +61,7 @@ #undef CK804B_BUSN #endif #define CK804B_BUSN 0x0 - + #ifndef CK804B_PCI_E_X #define CK804B_PCI_E_X 4 #endif @@ -77,69 +77,69 @@ #define CK804_CHIP_REV 3 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE + #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE + #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - #define CK804B_DEVN_BASE 1 + #define CK804B_DEVN_BASE 1 #else - #define CK804B_DEVN_BASE CK804_DEVN_BASE + #define CK804B_DEVN_BASE CK804_DEVN_BASE #endif static void ck804_early_set_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) { - static const unsigned int ctrl_devport_conf[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - }; + static const unsigned int ctrl_devport_conf[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + }; - static const unsigned int ctrl_devport_conf_b[] = { - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, - }; + static const unsigned int ctrl_devport_conf_b[] = { + PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, + PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, + }; - int j; - for(j = 0; j < ck804_num; j++ ) { - if(busn[j]==0) { //sb chain - setup_resource_map_offset(ctrl_devport_conf, - sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), - PCI_DEV(busn[j], 0, 0) , io_base[j]); - continue; - } - setup_resource_map_offset(ctrl_devport_conf_b, - sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]), - PCI_DEV(busn[j], 0, 0) , io_base[j]); - } + int j; + for(j = 0; j < ck804_num; j++ ) { + if(busn[j]==0) { //sb chain + setup_resource_map_offset(ctrl_devport_conf, + sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), + PCI_DEV(busn[j], 0, 0) , io_base[j]); + continue; + } + setup_resource_map_offset(ctrl_devport_conf_b, + sizeof(ctrl_devport_conf_b)/sizeof(ctrl_devport_conf_b[0]), + PCI_DEV(busn[j], 0, 0) , io_base[j]); + } } static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn, unsigned *io_base) { - static const unsigned int ctrl_devport_conf_clear[] = { - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, - }; + static const unsigned int ctrl_devport_conf_clear[] = { + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + }; - static const unsigned int ctrl_devport_conf_clear_b[] = { - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, - PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, - }; + static const unsigned int ctrl_devport_conf_clear_b[] = { + PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), 0, + PCI_ADDR(0, (CK804B_DEVN_BASE+0x1), 0, SYSCTRL_REG_POS), ~(0x0000ff00), 0, + }; - int j; - for(j = 0; j < ck804_num; j++ ) { - if(busn[j]==0) { //sb chain - setup_resource_map_offset(ctrl_devport_conf_clear, - sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), - PCI_DEV(busn[j], 0, 0) , io_base[j]); - continue; - } - setup_resource_map_offset(ctrl_devport_conf_clear_b, - sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]), - PCI_DEV(busn[j], 0, 0) , io_base[j]); - } + int j; + for(j = 0; j < ck804_num; j++ ) { + if(busn[j]==0) { //sb chain + setup_resource_map_offset(ctrl_devport_conf_clear, + sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), + PCI_DEV(busn[j], 0, 0) , io_base[j]); + continue; + } + setup_resource_map_offset(ctrl_devport_conf_clear_b, + sizeof(ctrl_devport_conf_clear_b)/sizeof(ctrl_devport_conf_clear_b[0]), + PCI_DEV(busn[j], 0, 0) , io_base[j]); + } } @@ -148,213 +148,213 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn, unsigned *io_base) { - static const unsigned int ctrl_conf_master[] = { + static const unsigned int ctrl_conf_master[] = { - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, #ifdef CK804_MB_SETUP - CK804_MB_SETUP + CK804_MB_SETUP #endif #if CK804_NUM > 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, #endif #if CK804_NUM == 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x19000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe0), 0xfffffeff, 0x00000100, #endif - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, ~(0xffff), 0x0f008, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, ~((0xff)|(0xff<<16)), (0x41<<16)|(0x32), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7c, ~(0xff<<16), (0xa0<<16), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), //PANTA RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, - - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804_PCI_E_X<<4)|(1<<8), + //SYSCTRL - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 8, ~(0xff), ((0<<4)|(0<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 9, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), #endif #if CK804_USE_ACI == 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x0d, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+0x1a, ~(0xff), ((0<<4)|(2<<2)|(0<<0)), #endif #if CK804_NUM > 1 - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), #endif - }; + }; - static const unsigned int ctrl_conf_slave[] = { + static const unsigned int ctrl_conf_slave[] = { - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x48), 0xfffffffd, 0x00000002, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x74), 0xfffff00f, 0x000009d0, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0x8c), 0xffff0000, 0x0000007f, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xcc), 0xfffffff8, 0x00000003, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd0), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd4), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xd8), 0xff000000, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE , 0, 0xdc), 0x7f000000, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, - RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xf0), 0xfffffffd, 0x00000002, + RES_PCI_IO,PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xf8), 0xffffffcf, 0x00000010, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x40), 0xfff8ffff, 0x00030000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x4c), 0xfe00ffff, 0x00440000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+9 , 0, 0x74), 0xffffffc0, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0x78), 0xc0ffffff, 0x20000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN,CK804B_DEVN_BASE+1,0,0xe0), 0xfffffeff, 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe8), 0xffffff00, 0x000000ff, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x20, 0xe00fffff, 0x11000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xc3f0ffff, 0x24040000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, 0x8c3f04df, 0x51407120, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x84, 0xffffff8f, 0x00000010, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x94, 0xff00ffff, 0x00c00000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, 0xf7ffffff, 0x00000000, RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x70), ~(0x000f0000), 0x00040000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xa0), ~(0x000001ff), 0x00000150, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0x7c), ~(0x00000010), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xd0), ~(0xf0000000), 0x00000000, + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+8 , 0, 0xe0), ~(0xf0000000), 0x00000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x04, ~((0x3ff<<0)|(0x3ff<<10)), (0x21<<0)|(0x22<<10), //PANTA RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c<<10)|0x1b, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x80, ~(1<<3), 0x00000000, - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7<<4)|(1<<8)), (CK804B_PCI_E_X<<4)|(1<<8), #if CK804_USE_NIC == 1 - RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), - RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), + RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE+0xa , 0, 0xf8), 0xffffffbf, 0x00000040, + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), + RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23), #endif - }; + }; - int j; + int j; - for(j=0; j<ck804_num; j++) { - if(busn[j] == 0) { - setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]), - PCI_DEV(busn[0],0,0), io_base[0]); - continue; - } + for(j=0; j<ck804_num; j++) { + if(busn[j] == 0) { + setup_resource_map_x_offset(ctrl_conf_master, sizeof(ctrl_conf_master)/sizeof(ctrl_conf_master[0]), + PCI_DEV(busn[0],0,0), io_base[0]); + continue; + } - setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]), - PCI_DEV(busn[j],0,0), io_base[j]); - } + setup_resource_map_x_offset(ctrl_conf_slave, sizeof(ctrl_conf_slave)/sizeof(ctrl_conf_slave[0]), + PCI_DEV(busn[j],0,0), io_base[j]); + } - for(j=0; j< ck804_num; j++) { - // PCI-E (XSPLL) SS table 0x40, x044, 0x48 - // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 - // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, - io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); - setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, - io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); -//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, -// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); - } + for(j=0; j< ck804_num; j++) { + // PCI-E (XSPLL) SS table 0x40, x044, 0x48 + // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 + // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 + setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, + io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); + setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, + io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); +//PANTA setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, +// io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); + } } static int ck804_early_setup_x(void) { - unsigned busn[4]; + unsigned busn[4]; unsigned io_base[4]; int ck804_num = 0; int i; @@ -362,20 +362,20 @@ for(i=0;i<4;i++) { uint32_t id; device_t dev; - if(i == 0) { // SB chain - dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0); - } - else { - dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0); - } + if(i == 0) { // SB chain + dev = PCI_DEV(i*0x40, CK804_DEVN_BASE, 0); + } + else { + dev = PCI_DEV(i*0x40, CK804B_DEVN_BASE, 0); + } id = pci_read_config32(dev, PCI_VENDOR_ID); if(id == 0x005e10de) { busn[ck804_num] = i * 0x40; io_base[ck804_num] = i * 0x4000; - ck804_num++; + ck804_num++; } } - + ck804_early_set_port(ck804_num, busn, io_base); ck804_early_setup(ck804_num, busn, io_base); ck804_early_clear_port(ck804_num, busn, io_base); @@ -384,20 +384,19 @@ static void hard_reset(void) { - set_bios_reset(); + set_bios_reset(); - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); } static void soft_reset(void) { - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif + set_bios_reset(); + + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup_ss.h 2008-09-18 16:27:00 UTC (rev 3584) @@ -203,4 +203,4 @@ 0x0C5039037, }; - + Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_smbus.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -14,11 +14,11 @@ if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); } - + print_debug("SMBus controller enabled\r\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - /* Set smbus iospace enable */ + /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); @@ -26,9 +26,9 @@ static int smbus_read_byte(unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_enable_rom.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -3,9 +3,9 @@ * by yhlu(a)tyan.com */ #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE - #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE + #define CK804_DEVN_BASE HT_CHAIN_END_UNITID_BASE #else - #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE + #define CK804_DEVN_BASE HT_CHAIN_UNITID_BASE #endif static void ck804_enable_rom(void) Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ht.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -10,12 +10,12 @@ #include "ck804.h" static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations ht_ops = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_ide.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -39,12 +39,12 @@ pci_write_config16(dev, 0x50, word); - byte = 0x20 ; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); - dword = pci_read_config32(dev, 0xf8); - dword |= 12; - pci_write_config32(dev, 0xf8, dword); + dword = pci_read_config32(dev, 0xf8); + dword |= 12; + pci_write_config32(dev, 0xf8, dword); #if CONFIG_PCI_ROM_RUN == 1 pci_dev_init(dev); #endif @@ -53,21 +53,21 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .scan_bus = 0, -// .enable = ck804_enable, - .ops_pci = &lops_pci, + .init = ide_init, + .scan_bus = 0, +// .enable = ck804_enable, + .ops_pci = &lops_pci, }; static const struct pci_driver ide_driver __pci_driver = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -94,7 +94,7 @@ printk_warning("IO APIC not responding.\n"); return; } - printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", + printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", a->reg, a->value_low, a->value_high); } } @@ -113,45 +113,45 @@ static void lpc_common_init(device_t dev) { - uint8_t byte; - uint32_t dword; - - /* IO APIC initialization */ - byte = pci_read_config8(dev, 0x74); - byte |= (1<<0); // enable APIC - pci_write_config8(dev, 0x74, byte); - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 - - setup_ioapic(dword); - + uint8_t byte; + uint32_t dword; + + /* IO APIC initialization */ + byte = pci_read_config8(dev, 0x74); + byte |= (1<<0); // enable APIC + pci_write_config8(dev, 0x74, byte); + dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + + setup_ioapic(dword); + #if 1 - dword = pci_read_config32(dev, 0xe4); - dword |= (1<<23); - pci_write_config32(dev, 0xe4, dword); -#endif + dword = pci_read_config32(dev, 0xe4); + dword |= (1<<23); + pci_write_config32(dev, 0xe4, dword); +#endif } -static void lpc_slave_init(device_t dev) +static void lpc_slave_init(device_t dev) { lpc_common_init(dev); } static void rom_dummy_write(device_t dev){ - uint8_t old, new; + uint8_t old, new; uint8_t *p; - - old = pci_read_config8(dev, 0x88); - new = old | 0xc0; - if (new != old) { - pci_write_config8(dev, 0x88, new); - } + + old = pci_read_config8(dev, 0x88); + new = old | 0xc0; + if (new != old) { + pci_write_config8(dev, 0x88, new); + } // enable write - old = pci_read_config8(dev, 0x6d); - new = old | 0x01; - if (new != old) { - pci_write_config8(dev, 0x6d, new); - } + old = pci_read_config8(dev, 0x6d); + new = old | 0x01; + if (new != old) { + pci_write_config8(dev, 0x6d, new); + } /* dummy write */ p = (uint8_t *)0xffffffe0; @@ -160,22 +160,22 @@ old = *p; // disable write - old = pci_read_config8(dev, 0x6d); - new = old & 0xfe; - if (new != old) { - pci_write_config8(dev, 0x6d, new); + old = pci_read_config8(dev, 0x6d); + new = old & 0xfe; + if (new != old) { + pci_write_config8(dev, 0x6d, new); - } + } } #if 0 static void enable_hpet(struct device *dev) { - unsigned long hpet_address; + unsigned long hpet_address; - pci_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk_debug("enabling HPET @0x%x\n", hpet_address); + pci_write_config32(dev,0x44, 0xfed00001); + hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; + printk_debug("enabling HPET @0x%x\n", hpet_address); } #endif @@ -195,34 +195,34 @@ #if 0 /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); + pci_write_config8(dev, 0x46, byte | (1<<0)); #endif /* power after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); - byte &= ~0x40; - if (!on) { - byte |= 0x40; - } - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&on, "power_on_after_fail"); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte &= ~0x40; + if (!on) { + byte |= 0x40; + } + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + printk_info("set power %s after power fail\n", on?"on":"off"); - /* Throttle the CPU speed down for testing */ - on = SLOW_CPU_OFF; - get_option(&on, "slow_cpu"); - if(on) { + /* Throttle the CPU speed down for testing */ + on = SLOW_CPU_OFF; + get_option(&on, "slow_cpu"); + if(on) { uint16_t pm10_bar; uint32_t dword; - pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); - outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); - dword = inl(pm10_bar + 0x10); - on = 8-on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", - (on*12)+(on>>1),(on&1)*5); - } + pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); + outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); + dword = inl(pm10_bar + 0x10); + on = 8-on; + printk_debug("Throttling CPU %2d.%1.1d percent.\n", + (on*12)+(on>>1),(on&1)*5); + } #if 0 // default is enabled @@ -243,7 +243,7 @@ byte_old = byte; nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); - if (nmi_option) { + if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW @@ -251,18 +251,18 @@ if( byte != byte_old) { outb(0x70, byte); } - + /* Initialize the real time clock */ rtc_init(0); /* Initialize isa dma */ isa_dma_init(); - /* Initialize the High Precision Event Timers */ -// enable_hpet(dev); + /* Initialize the High Precision Event Timers */ +// enable_hpet(dev); rom_dummy_write(dev); - + } static void ck804_lpc_read_resources(device_t dev) @@ -271,66 +271,66 @@ unsigned long index; /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP - - /* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */ - for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. - pci_get_resource(dev, index); - } - compact_resources(dev); + pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP - /* Add an extra subtractive resource for both memory and I/O */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Get Resource for ACPI, SYSTEM_CONTROL, ANALOG_CONTROL */ + for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. + pci_get_resource(dev, index); + } + compact_resources(dev); + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + } -/** +/** * @brief Enable resources for children devices - * + * * @param dev the device whos children's resources are to be enabled - * + * * This function is call by the global enable_resources() indirectly via the * device_operation::enable_resources() method of devices. - * + * * Indirect mutual recursion: * enable_childrens_resources() -> enable_resources() * enable_resources() -> device_operation::enable_resources() * device_operation::enable_resources() -> enable_children_resources() - */ + */ static void ck804_lpc_enable_childrens_resources(device_t dev) -{ - unsigned link; +{ + unsigned link; uint32_t reg, reg_var[4]; int i; int var_num = 0; - + reg = pci_read_config32(dev, 0xa0); - for (link = 0; link < dev->links; link++) { - device_t child; - for (child = dev->link[link].children; child; child = child->sibling) { - enable_resources(child); + for (link = 0; link < dev->links; link++) { + device_t child; + for (child = dev->link[link].children; child; child = child->sibling) { + enable_resources(child); if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { for(i=0;i<child->resources;i++) { struct resource *res; - unsigned long base, end; // don't need long long + unsigned long base, end; // don't need long long res = &child->resource[i]; if(!(res->flags & IORESOURCE_IO)) continue; - base = res->base; - end = resource_end(res); + base = res->base; + end = resource_end(res); printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; case 0x2f8: // COM2 - reg |= (1<<1); break; + reg |= (1<<1); break; case 0x378: // Parallal 1 reg |= (1<<24); break; - case 0x3f0: // FD0 + case 0x3f0: // FD0 reg |= (1<<20); break; case 0x220: // Aduio 0 reg |= (1<<8); break; @@ -341,33 +341,33 @@ if(var_num>=4) continue; // only 4 var ; compact them ? reg |= (1<<(28+var_num)); reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16); - } + } } } - } - } + } + } pci_write_config32(dev, 0xa0, reg); for(i=0;i<var_num;i++) { pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); - } - + } + } static void ck804_lpc_enable_resources(device_t dev) { - pci_dev_enable_resources(dev); - ck804_lpc_enable_childrens_resources(dev); + pci_dev_enable_resources(dev); + ck804_lpc_enable_childrens_resources(dev); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations lpc_ops = { @@ -386,30 +386,30 @@ }; static const struct pci_driver lpc_driver_pro __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_PRO, }; #if CK804_CHIP_REV == 1 static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, }; -#else +#else static struct device_operations lpc_slave_ops = { - .read_resources = ck804_lpc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = lpc_slave_init, -// .enable = ck804_enable, + .read_resources = ck804_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_slave_init, +// .enable = ck804_enable, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver_slave __pci_driver = { - .ops = &lpc_slave_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, -}; -#endif + .ops = &lpc_slave_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SLAVE, +}; +#endif Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_nic.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -21,30 +21,30 @@ static uint32_t nic_index = 0; - uint8_t *base; - struct resource *res; + uint8_t *base; + struct resource *res; - res = find_resource(dev, 0x10); + res = find_resource(dev, 0x10); - base = res->base; + base = res->base; #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 - writel(PHY_RGMII, base + NvRegPhyInterface); + writel(PHY_RGMII, base + NvRegPhyInterface); - old = dword = pci_read_config32(dev, 0x30); - dword &= ~(0xf); - dword |= 0xf; - if(old != dword) { - pci_write_config32(dev, 0x30 , dword); - } + old = dword = pci_read_config32(dev, 0x30); + dword &= ~(0xf); + dword |= 0xf; + if(old != dword) { + pci_write_config32(dev, 0x30 , dword); + } - conf = dev->chip_info; - - if(conf->mac_eeprom_smbus != 0) { + conf = dev->chip_info; + + if(conf->mac_eeprom_smbus != 0) { // read MAC address from EEPROM at first - struct device *dev_eeprom; + struct device *dev_eeprom; dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); if(dev_eeprom) { @@ -65,12 +65,12 @@ } if(mac_l != 0xffffffff) { mac_l += nic_index; - mac_h = 0; - for(i=5;i>=4;i--) { + mac_h = 0; + for(i=5;i>=4;i--) { mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; + mac_h += dat[i]; + } + eeprom_valid = 1; } } } @@ -82,12 +82,12 @@ mac_l = readl(mac_pos) + nic_index; mac_h = readl(mac_pos + 4); } -#if 1 +#if 1 // set that into NIC MMIO #define NvRegMacAddrA 0xA8 #define NvRegMacAddrB 0xAC - writel(mac_l, base + NvRegMacAddrA); - writel(mac_h, base + NvRegMacAddrB); + writel(mac_l, base + NvRegMacAddrA); + writel(mac_h, base + NvRegMacAddrB); #else // set that into NIC pci_write_config32(dev, 0xa8, mac_l); @@ -104,12 +104,12 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations nic_ops = { @@ -127,7 +127,7 @@ .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC, }; static const struct pci_driver nic_bridge_driver __pci_driver = { - .ops = &nic_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, + .ops = &nic_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_NIC_BRIDGE, }; Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pci.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -18,7 +18,7 @@ device_t pci_domain_dev; struct resource *mem1, *mem2; #endif - + /* System error enable */ dword = pci_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ @@ -26,16 +26,16 @@ pci_write_config32(dev, 0x04, dword); #if 0 - word = pci_read_config16(dev, 0x48); - word |= (1<<0); /* MRL2MRM */ - word |= (1<<2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); + word = pci_read_config16(dev, 0x48); + word |= (1<<0); /* MRL2MRM */ + word |= (1<<2); /* MR2MRM */ + pci_write_config16(dev, 0x48, word); #endif #if 1 - dword = pci_read_config32(dev, 0x4c); - dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ - pci_write_config32(dev, 0x4c, dword); + dword = pci_read_config32(dev, 0x4c); + dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ + pci_write_config32(dev, 0x4c, dword); #endif #if CONFIG_PCI_64BIT_PREF_MEM == 1 @@ -61,12 +61,12 @@ #endif printk_debug("[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); //TOM + pci_write_config32(dev, 0x50, dword); //TOM } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, }; static struct device_operations pci_ops = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_pcie.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -25,7 +25,7 @@ } static struct pci_operations lops_pci = { - .set_subsystem = 0, + .set_subsystem = 0, }; static struct device_operations pcie_ops = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_reset.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -6,26 +6,26 @@ #include <arch/io.h> #define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) + (((BUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x7) << 12)) typedef unsigned device_t; static void pci_write_config32(device_t dev, unsigned where, unsigned value) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); } static unsigned pci_read_config32(device_t dev, unsigned where) { - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); + unsigned addr; + addr = (dev>>4) | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); } #include "../../../northbridge/amd/amdk8/reset_test.c" @@ -33,7 +33,7 @@ void hard_reset(void) { set_bios_reset(); - /* Try rebooting through port 0xcf9 */ + /* Try rebooting through port 0xcf9 */ outb((0 <<3)|(0<<2)|(1<<1), 0xcf9); outb((0 <<3)|(1<<2)|(1<<1), 0xcf9); } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -15,90 +15,85 @@ // reset = 1 : reset // reset = 0 : clear { - uint32_t *base; + uint32_t *base; uint32_t dword; int loop; - base = (uint32_t *) pci_read_config32(dev, 0x24); + base = (uint32_t *) pci_read_config32(dev, 0x24); printk_debug("base = %08x\r\n", base); - if(reset) { - *(base + 4) = 0xffffffff; - *(base + 0x44) = 0xffffffff; - } + if(reset) { + *(base + 4) = 0xffffffff; + *(base + 0x44) = 0xffffffff; + } - dword = *(base +8); - dword &= ~(0xf); - dword |= reset; + dword = *(base +8); + dword &= ~(0xf); + dword |= reset; - *(base + 8) = dword; - *(base + 0x48) = dword; + *(base + 8) = dword; + *(base + 0x48) = dword; #if 0 udelay(1000); dword &= ~(0xf); - *(base + 8) = dword; - *(base + 0x48) = dword; + *(base + 8) = dword; + *(base + 0x48) = dword; #endif - - - if(reset) return; + if(reset) return; - dword = *(base+ 0); + dword = *(base+ 0); printk_debug("*(base+0)=%08x\r\n",dword); - if(dword == 0x113) { + if(dword == 0x113) { loop = 200000;// 2 do { dword = *(base + 4); - if((dword & 0x10000)!=0) break; + if((dword & 0x10000)!=0) break; udelay(10); } while (--loop>0); printk_debug("loop=%d, *(base+4)=%08x\r\n",loop, dword); } - - dword = *(base+ 0x40); + dword = *(base+ 0x40); printk_debug("*(base+0x40)=%08x\r\n",dword); - if(dword == 0x113) { + if(dword == 0x113) { loop = 200000;//2 do { - dword = *(base + 0x44); - if((dword & 0x10000)!=0) break; + dword = *(base + 0x44); + if((dword & 0x10000)!=0) break; udelay(10); - } while (--loop>0); + } while (--loop>0); printk_debug("loop=%d, *(base+0x44)=%08x\r\n",loop, dword); } - - } static void sata_init(struct device *dev) { - uint32_t dword; + uint32_t dword; struct southbridge_nvidia_ck804_config *conf; conf = dev->chip_info; - dword = pci_read_config32(dev, 0x50); - /* Ensure prefetch is disabled */ - dword &= ~((1 << 15) | (1 << 13)); - if (conf->sata1_enable) { - /* Enable secondary SATA interface */ - dword |= (1<<0); - printk_debug("SATA S \t"); - } - if (conf->sata0_enable) { - /* Enable primary SATA interface */ - dword |= (1<<1); - printk_debug("SATA P \n"); - } + dword = pci_read_config32(dev, 0x50); + /* Ensure prefetch is disabled */ + dword &= ~((1 << 15) | (1 << 13)); + if (conf->sata1_enable) { + /* Enable secondary SATA interface */ + dword |= (1<<0); + printk_debug("SATA S \t"); + } + if (conf->sata0_enable) { + /* Enable primary SATA interface */ + dword |= (1<<1); + printk_debug("SATA P \n"); + } #if 0 // write back - dword |= (1<<12); - dword |= (1<<14); + dword |= (1<<12); + dword |= (1<<14); #endif #if 0 @@ -107,33 +102,33 @@ dword |= (1<<17); #endif -#if 1 +#if 1 //DO NOT relay OK and PAGE_FRNDLY_DTXFR_CNT. dword &= ~(0x1f<<24); - dword |= (0x15<<24); + dword |= (0x15<<24); #endif - pci_write_config32(dev, 0x50, dword); + pci_write_config32(dev, 0x50, dword); #if 0 //SLUMBER_DURING_D3. - dword = pci_read_config32(dev, 0x7c); - dword &= ~(1<<4); - pci_write_config32(dev, 0x7c, dword); + dword = pci_read_config32(dev, 0x7c); + dword &= ~(1<<4); + pci_write_config32(dev, 0x7c, dword); dword = pci_read_config32(dev, 0xd0); dword &= ~(0xff<<24); dword |= (0x68<<24); pci_write_config32(dev, 0xd0, dword); - dword = pci_read_config32(dev, 0xe0); - dword &= ~(0xff<<24); - dword |= (0x68<<24); + dword = pci_read_config32(dev, 0xe0); + dword &= ~(0xff<<24); + dword |= (0x68<<24); pci_write_config32(dev, 0xe0, dword); #endif - dword = pci_read_config32(dev, 0xf8); - dword |= 2; - pci_write_config32(dev, 0xf8, dword); + dword = pci_read_config32(dev, 0xf8); + dword |= 2; + pci_write_config32(dev, 0xf8, dword); #if 0 dword = pci_read_config32(dev, 0xac); @@ -148,11 +143,11 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations sata_ops = { @@ -172,7 +167,7 @@ }; static const struct pci_driver sata1_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SATA1, }; Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -15,88 +15,88 @@ static int lsmbus_recv_byte(device_t dev) { - unsigned device; - struct resource *res; + unsigned device; + struct resource *res; struct bus *pbus; - device = dev->path.u.i2c.device; + device = dev->path.u.i2c.device; pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); - return do_smbus_recv_byte(res->base, device); + return do_smbus_recv_byte(res->base, device); } - + static int lsmbus_send_byte(device_t dev, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.u.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); - return do_smbus_send_byte(res->base, device, val); + return do_smbus_send_byte(res->base, device, val); } static int lsmbus_read_byte(device_t dev, uint8_t address) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.u.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); - return do_smbus_read_byte(res->base, device, address); + return do_smbus_read_byte(res->base, device, address); } static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) { - unsigned device; - struct resource *res; - struct bus *pbus; + unsigned device; + struct resource *res; + struct bus *pbus; - device = dev->path.u.i2c.device; - pbus = get_pbus_smbus(dev); + device = dev->path.u.i2c.device; + pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); + res = find_resource(pbus->dev, 0x20 + (pbus->link * 4)); - return do_smbus_write_byte(res->base, device, address, val); + return do_smbus_write_byte(res->base, device, address, val); } static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, }; static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations smbus_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = scan_static_bus, -// .enable = ck804_enable, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = scan_static_bus, +// .enable = ck804_enable, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_CK804_SM, }; Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_smbus.h 2008-09-18 16:27:00 UTC (rev 3584) @@ -11,7 +11,7 @@ #define SMBHSTDAT0 0x4 #define SMBHSTDAT1 0x5 -/* Between 1-10 seconds, We should never timeout normally +/* Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100*1000*10) @@ -45,7 +45,7 @@ do { unsigned char val; smbus_delay(); - + val = inb(smbus_io_base + SMBHSTSTAT); if ( (val & 0xff) != 0) { return 0; @@ -55,87 +55,87 @@ } static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { - unsigned char global_status_register; - unsigned char byte; -#if 0 + unsigned char global_status_register; + unsigned char byte; +#if 0 // Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } #endif - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); - smbus_delay(); - /* set the command/address... */ - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); - /* byte data recv */ - outb(0x05, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + /* set the command/address... */ + outb(0, smbus_io_base + SMBHSTCMD); + smbus_delay(); + /* byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); - if (global_status_register != 0x80) { // lose check, otherwise it should be 0 - return -1; - } - return byte; + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; } static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val) { - unsigned global_status_register; + unsigned global_status_register; #if 0 // Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } #endif - outb(val, smbus_io_base + SMBHSTDAT0); - smbus_delay(); + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); - smbus_delay(); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); - outb(0, smbus_io_base + SMBHSTCMD); - smbus_delay(); + outb(0, smbus_io_base + SMBHSTCMD); + smbus_delay(); - /* set up for a byte data write */ - outb(0x04, smbus_io_base + SMBHSTPRTCL); - smbus_delay(); + /* set up for a byte data write */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - if (global_status_register != 0x80) { - return -1; - } - return 0; + if (global_status_register != 0x80) { + return -1; + } + return 0; } static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { unsigned char global_status_register; unsigned char byte; -#if 0 +#if 0 // Don't need, when you write to PRTCL, the status will be cleared automatically if (smbus_wait_until_ready(smbus_io_base) < 0) { return -2; } #endif - + /* set the device I'm talking too */ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); smbus_delay(); @@ -165,38 +165,38 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val) { - unsigned global_status_register; + unsigned global_status_register; #if 0 // Don't need, when you write to PRTCL, the status will be cleared automatically - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; - } + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; + } #endif outb(val, smbus_io_base + SMBHSTDAT0); smbus_delay(); - /* set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); smbus_delay(); - outb(address & 0xff, smbus_io_base + SMBHSTCMD); + outb(address & 0xff, smbus_io_base + SMBHSTCMD); smbus_delay(); - /* set up for a byte data write */ - outb(0x06, smbus_io_base + SMBHSTPRTCL); + /* set up for a byte data write */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); smbus_delay(); - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; - } - global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; - if (global_status_register != 0x80) { - return -1; - } - return 0; + if (global_status_register != 0x80) { + return -1; + } + return 0; } Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -24,11 +24,11 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations usb_ops = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_usb2.c 2008-09-18 16:27:00 UTC (rev 3584) @@ -12,19 +12,19 @@ static void usb2_init(struct device *dev) { - uint32_t dword; - dword = pci_read_config32(dev, 0xf8); - dword |= 40; - pci_write_config32(dev, 0xf8, dword); + uint32_t dword; + dword = pci_read_config32(dev, 0xf8); + dword |= 40; + pci_write_config32(dev, 0xf8, dword); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); +{ + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); } static struct pci_operations lops_pci = { - .set_subsystem = lpci_set_subsystem, + .set_subsystem = lpci_set_subsystem, }; static struct device_operations usb2_ops = { Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/id.inc 2008-09-18 16:27:00 UTC (rev 3584) @@ -3,9 +3,9 @@ .globl __id_start __id_start: -vendor: +vendor: .asciz MAINBOARD_VENDOR -part: +part: .asciz MAINBOARD_PART_NUMBER .long __id_end + 0x80 - vendor /* Reverse offset to the vendor id */ .long __id_end + 0x80 - part /* Reverse offset to the part number */ Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc 2008-09-18 15:30:42 UTC (rev 3583) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/romstrap.inc 2008-09-18 16:27:00 UTC (rev 3584) @@ -8,28 +8,28 @@ .globl __romstrap_start __romstrap_start: rstables: - .long 0x2b16d065 - .long 0x0 - .long 0x0 - .long linkedlist + .long 0x2b16d065 + .long 0x0 + .long 0x0 + .long linkedlist linkedlist: .long 0x0003001C // 10h .long 0x08000000 // 14h .long 0x00000000 // 18h .long 0xFFFFFFFF // 1Ch - + .long 0xFFFFFFFF // 20h .long 0xFFFFFFFF // 24h .long 0xFFFFFFFF // 28h .long 0xFFFFFFFF // 2Ch - + .long 0x81543266 // 30h, MAC address low 4 byte ---> keep it in 0xffffffd0 .long 0x000000E0 // 34h, MAC address high 4 byte .long 0x002309CE // 38h, UUID low 4 byte .long 0x00E08100 // 3Ch, UUID high 4 byte - + rspointers: .long rstables // It will be 0xffffffe0 .long rstables

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r3583 build service
by coreboot information 18 Sep '08

18 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "myles" checked in revision 3583 to the coreboot source repository and caused the following changes: Change Log: Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1 that don't seem to clarify anything. Abuild tested. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3583&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3583&device=epia-cn&vendor… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3582 build service
by coreboot information 18 Sep '08

18 Sep '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "stepan" checked in revision 3582 to the coreboot source repository and caused the following changes: Change Log: fix two minor bugs in nvramtool. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3582&device=j7f24&vendor=j… Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3582&device=epia-cn&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot September 2008