coreboot August 2008

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[patch] vga cursor positioning and correct usage of VIDEO() macro fix (again) (w/ patch)
by Jonathan A. Kollasch 11 Aug '08

11 Aug '08

Make cursor positioning work by using both halves of the VGA cursor position register. Have vga_scroll_up() and vga_clear_line() present row/column arguments to the VIDEO() macro in the right order. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- This had previously been change set 3186, but was lost when console video support was restructured.

3 2

r3498 - trunk/payloads/libpayload/drivers/video
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: jcrouse Date: 2008-08-11 19:19:10 +0200 (Mon, 11 Aug 2008) New Revision: 3498 Modified: trunk/payloads/libpayload/drivers/video/vga.c Log: Make cursor positioning work by using both halves of the VGA cursor position register. Have vga_scroll_up() and vga_clear_line() present row/column arguments to the VIDEO() macro in the right order. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/drivers/video/vga.c =================================================================== --- trunk/payloads/libpayload/drivers/video/vga.c 2008-08-11 17:10:58 UTC (rev 3497) +++ trunk/payloads/libpayload/drivers/video/vga.c 2008-08-11 17:19:10 UTC (rev 3498) @@ -54,7 +54,7 @@ { unsigned int addr; addr = ((unsigned int) crtc_read(0x0E)) << 8; - addr += crtc_read(0x0E); + addr += crtc_read(0x0F); *x = addr % VIDEO_COLS; *y = addr / VIDEO_COLS; @@ -68,7 +68,7 @@ addr = x + (VIDEO_COLS * y); crtc_write(addr >> 8, 0x0E); - crtc_write(addr, 0x0E); + crtc_write(addr, 0x0F); } static void vga_enable_cursor(int state) @@ -87,7 +87,7 @@ static void vga_clear_line(u8 row, u8 ch, u8 attr) { int col; - u16 *ptr = VIDEO(0, row); + u16 *ptr = VIDEO(row, 0); for(col = 0; col < VIDEO_COLS; col++) ptr[col] = ((attr & 0xFF) << 8) | (ch & 0xFF); @@ -95,7 +95,7 @@ static void vga_scroll_up(void) { - u16 *src = VIDEO(0,1); + u16 *src = VIDEO(1,0); u16 *dst = VIDEO(0,0); int i;

1 0

notes on v3 transition
by ron minnich 11 Aug '08

11 Aug '08

I am putting stuff here: http://www.coreboot.org/Notes_for_v3_ports v3 is really different. Overall, it's much better. I will try to keep logging bits and pieces here. ron

1 0

r3497 - in trunk/payloads/libpayload: crypto curses i386 include
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: jcrouse Date: 2008-08-11 19:10:58 +0200 (Mon, 11 Aug 2008) New Revision: 3497 Modified: trunk/payloads/libpayload/crypto/sha1.c trunk/payloads/libpayload/curses/local.h trunk/payloads/libpayload/i386/coreboot.c trunk/payloads/libpayload/i386/sysinfo.c trunk/payloads/libpayload/include/libpayload.h Log: No really, _these_ should be the last occurences of CONFIG_ without config.h in libpayload - also removed CONFIG_ instance in libpayload which would have been dangerous. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/crypto/sha1.c =================================================================== --- trunk/payloads/libpayload/crypto/sha1.c 2008-08-11 16:58:23 UTC (rev 3496) +++ trunk/payloads/libpayload/crypto/sha1.c 2008-08-11 17:10:58 UTC (rev 3497) @@ -20,6 +20,7 @@ * 34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F */ +#include <config.h> #include <libpayload.h> typedef u8 u_int8_t; @@ -27,6 +28,14 @@ typedef u64 u_int64_t; typedef unsigned int u_int; +/* Moved from libpayload.h */ + +#ifdef CONFIG_TARGET_I386 +#define BYTE_ORDER LITTLE_ENDIAN +#else +#define BYTE_ORDER BIG_ENDIAN +#endif + #if 0 #include <sys/param.h> #include <string.h> Modified: trunk/payloads/libpayload/curses/local.h =================================================================== --- trunk/payloads/libpayload/curses/local.h 2008-08-11 16:58:23 UTC (rev 3496) +++ trunk/payloads/libpayload/curses/local.h 2008-08-11 17:10:58 UTC (rev 3497) @@ -58,6 +58,7 @@ #undef USE_TERMLIB +#include <config.h> #include <libpayload.h> #include <curses.h> #include <curses.priv.h> Modified: trunk/payloads/libpayload/i386/coreboot.c =================================================================== --- trunk/payloads/libpayload/i386/coreboot.c 2008-08-11 16:58:23 UTC (rev 3496) +++ trunk/payloads/libpayload/i386/coreboot.c 2008-08-11 17:10:58 UTC (rev 3497) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> #include <coreboot_tables.h> Modified: trunk/payloads/libpayload/i386/sysinfo.c =================================================================== --- trunk/payloads/libpayload/i386/sysinfo.c 2008-08-11 16:58:23 UTC (rev 3496) +++ trunk/payloads/libpayload/i386/sysinfo.c 2008-08-11 17:10:58 UTC (rev 3497) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> /** Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-08-11 16:58:23 UTC (rev 3496) +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-11 17:10:58 UTC (rev 3497) @@ -44,11 +44,6 @@ #define LITTLE_ENDIAN 1234 #define BIG_ENDIAN 4321 -#ifdef CONFIG_TARGET_I386 -#define BYTE_ORDER LITTLE_ENDIAN -#else -#define BYTE_ORDER BIG_ENDIAN -#endif #define EXIT_SUCCESS 0 #define EXIT_FAILURE 1

1 0

r3496 - in trunk/payloads/libpayload: curses drivers
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: stepan Date: 2008-08-11 18:58:23 +0200 (Mon, 11 Aug 2008) New Revision: 3496 Modified: trunk/payloads/libpayload/curses/keyboard.c trunk/payloads/libpayload/drivers/nvram.c trunk/payloads/libpayload/drivers/serial.c Log: these should be the last occurences of CONFIG_ without config.h in libpayload. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/curses/keyboard.c =================================================================== --- trunk/payloads/libpayload/curses/keyboard.c 2008-08-11 16:55:35 UTC (rev 3495) +++ trunk/payloads/libpayload/curses/keyboard.c 2008-08-11 16:58:23 UTC (rev 3496) @@ -37,6 +37,7 @@ * Actually cook the serial (handle special keys) */ +#include <config.h> #include "local.h" static int _halfdelay = 0; Modified: trunk/payloads/libpayload/drivers/nvram.c =================================================================== --- trunk/payloads/libpayload/drivers/nvram.c 2008-08-11 16:55:35 UTC (rev 3495) +++ trunk/payloads/libpayload/drivers/nvram.c 2008-08-11 16:58:23 UTC (rev 3496) @@ -39,7 +39,7 @@ * http://bochs.sourceforge.net/techspec/CMOS-reference.txt * http://www.bioscentral.com/misc/cmosmap.htm */ - +#include <config.h> #include <libpayload.h> Modified: trunk/payloads/libpayload/drivers/serial.c =================================================================== --- trunk/payloads/libpayload/drivers/serial.c 2008-08-11 16:55:35 UTC (rev 3495) +++ trunk/payloads/libpayload/drivers/serial.c 2008-08-11 16:58:23 UTC (rev 3496) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> #define IOBASE lib_sysinfo.ser_ioport

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r3495 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: stepan Date: 2008-08-11 18:55:35 +0200 (Mon, 11 Aug 2008) New Revision: 3495 Modified: trunk/payloads/libpayload/libc/console.c trunk/payloads/libpayload/libc/exec.c trunk/payloads/libpayload/libc/time.c Log: these use CONFIG_ variables, too. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/libc/console.c =================================================================== --- trunk/payloads/libpayload/libc/console.c 2008-08-11 16:52:14 UTC (rev 3494) +++ trunk/payloads/libpayload/libc/console.c 2008-08-11 16:55:35 UTC (rev 3495) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> void console_init(void) Modified: trunk/payloads/libpayload/libc/exec.c =================================================================== --- trunk/payloads/libpayload/libc/exec.c 2008-08-11 16:52:14 UTC (rev 3494) +++ trunk/payloads/libpayload/libc/exec.c 2008-08-11 16:55:35 UTC (rev 3495) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> #ifdef CONFIG_TARGET_I386 Modified: trunk/payloads/libpayload/libc/time.c =================================================================== --- trunk/payloads/libpayload/libc/time.c 2008-08-11 16:52:14 UTC (rev 3494) +++ trunk/payloads/libpayload/libc/time.c 2008-08-11 16:55:35 UTC (rev 3495) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> #include <arch/rdtsc.h>

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r3494 - trunk/payloads/libpayload/drivers/video
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: stepan Date: 2008-08-11 18:52:14 +0200 (Mon, 11 Aug 2008) New Revision: 3494 Modified: trunk/payloads/libpayload/drivers/video/video.c Log: video.c uses CONFIG_ variables, so it needs config.h (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/drivers/video/video.c =================================================================== --- trunk/payloads/libpayload/drivers/video/video.c 2008-08-09 20:17:22 UTC (rev 3493) +++ trunk/payloads/libpayload/drivers/video/video.c 2008-08-11 16:52:14 UTC (rev 3494) @@ -27,6 +27,7 @@ * SUCH DAMAGE. */ +#include <config.h> #include <libpayload.h> #include <video_console.h>

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r743 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-11 18:19:01 +0200 (Mon, 11 Aug 2008) New Revision: 743 Added: coreboot-v3/southbridge/nvidia/mcp55/pcie.c Log: pcie support for mcp55. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: coreboot-v3/southbridge/nvidia/mcp55/pcie.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pcie.c (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-11 16:19:01 UTC (rev 743) @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "mcp55.h" + +static void pcie_init(struct device *dev) +{ + + /* Enable pci error detecting */ + u32 dword; + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (1<<30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + +} + +struct device_operations mcp55_pcie_a = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_A}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &pci_dev_ops_pci, +}; + +struct device_operations mcp55_pcie_b_c = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_B_C}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &pci_dev_ops_pci, +}; + +struct device_operations mcp55_pcie_d = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &pci_dev_ops_pci, +}; + +struct device_operations mcp55_pcie_e = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_D}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &pci_dev_ops_pci, +}; + +struct device_operations mcp55_pcie_f = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCIE_F}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pcie_init, + .ops_pci = &pci_dev_ops_pci, +};

1 0

r742 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-11 18:12:58 +0200 (Mon, 11 Aug 2008) New Revision: 742 Added: coreboot-v3/southbridge/nvidia/mcp55/sata.c coreboot-v3/southbridge/nvidia/mcp55/sata.dts Log: .c and .dts for mcp 55 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: coreboot-v3/southbridge/nvidia/mcp55/sata.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/sata.c (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-11 16:12:58 UTC (rev 742) @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "mcp55.h" + + +static void sata_init(struct device *dev) +{ + u32 dword; + + struct southbridge_nvidia_mcp55_sata_config *conf = + (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration; + + dword = pci_read_config32(dev, 0x50); + /* Ensure prefetch is disabled */ + dword &= ~((1 << 15) | (1 << 13)); + if(conf) { + if (conf->sata1_enable) { + dword |= (1<<0); + printk(BIOS_DEBUG, "Enable secondary SATA interface\t"); + } + if (conf->sata0_enable) { + dword |= (1<<1); + printk(BIOS_DEBUG, "Enable primary SATA interface\n"); + } + } else { + dword |= (1<<1) | (1<<0); + printk(BIOS_DEBUG, "Enable primary and secondary SATA interfaces\n"); + } + + +#if 1 + dword &= ~(0x1f<<24); + dword |= (0x15<<24); +#endif + pci_write_config32(dev, 0x50, dword); + + dword = pci_read_config32(dev, 0xf8); + dword |= 2; + pci_write_config32(dev, 0xf8, dword); + + +#warning finish set subsystem in mcp55 sata +#if 0 + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +#endif +} + +struct device_operations mcp55_sata = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA1}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = sata_init, + .ops_pci = &pci_dev_ops_pci, +}; Added: coreboot-v3/southbridge/nvidia/mcp55/sata.dts =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/sata.dts (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/sata.dts 2008-08-11 16:12:58 UTC (rev 742) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-8 Ronald G. Minnich <rminnich(a)gmail.com> * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "mcp55_sata"; + + sata0_enable = "0"; + sata1_enable = "0"; + +};

1 0

r741 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-11 18:09:02 +0200 (Mon, 11 Aug 2008) New Revision: 741 Added: coreboot-v3/southbridge/nvidia/mcp55/pci.c Log: compiles with no errors. Add pci device. This compiles with no errors, no warnings. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> With the comments addressed: Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> I left the #if 1 in. It was there for a reason, we just don't know what it was. I am reluctant to move such 'markers' at present. Added: coreboot-v3/southbridge/nvidia/mcp55/pci.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pci.c (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-11 16:09:02 UTC (rev 741) @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "mcp55.h" + +static void pci_init(struct device *dev) +{ + + u32 dword; + u16 word; +#ifdef CONFIG_PCI_64BIT_PREF_MEM + struct device pci_domain_dev; + struct resource *mem1, *mem2; +#endif + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (1<<30); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + +#if 1 + //only need (a01,xx] + word = pci_read_config16(dev, 0x48); + word |= (1<<0); /* MRL2MRM */ + word |= (1<<2); /* MR2MRM */ + pci_write_config16(dev, 0x48, word); +#endif + +#if 1 + dword = pci_read_config32(dev, 0x4c); + dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ + pci_write_config32(dev, 0x4c, dword); +#endif + +#ifdef CONFIG_PCI_64BIT_PREF_MEM + pci_domain_dev = dev->bus->dev; + while(pci_domain_dev) { + if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; + pci_domain_dev = pci_domain_dev->bus->dev; + } + + if(!pci_domain_dev) return; // impossiable + mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit + mem2 = find_resource(pci_domain_dev, 2); // mem + if(mem1->base > mem2->base) { + dword = mem2->base & (0xffff0000UL); + printk(BIOS_DEBUG, "PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); + } else { + dword = mem1->base & (0xffff0000UL); + printk(BIOS_DEBUG, "PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); + } +#else + dword = dev_root.resource[1].base & (0xffff0000UL); + printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); +#endif + printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); + pci_write_config32(dev, 0x50, dword); //TOM + +} + +struct device_operations mcp55_pci = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = pci_scan_bridge, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pci_init, + .ops_pci = &pci_dev_ops_pci, +};

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coreboot August 2008