coreboot August 2008

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r745 - coreboot-v3/include/arch/x86
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-12 01:02:34 +0200 (Tue, 12 Aug 2008) New Revision: 745 Added: coreboot-v3/include/arch/x86/lapic.h coreboot-v3/include/arch/x86/lapic_def.h Log: Add lapic defines and support. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Marc Jones <marc.jones(a)amd.com> Added: coreboot-v3/include/arch/x86/lapic.h =================================================================== --- coreboot-v3/include/arch/x86/lapic.h (rev 0) +++ coreboot-v3/include/arch/x86/lapic.h 2008-08-11 23:02:34 UTC (rev 745) @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * Copyright (C) 2004 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * Copyright (C) 2005 Stefan Reinauer <stepan(a)coresystems.de> + * Copyright (C) 2007 AMD Marc Jones + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef CPU_X86_LAPIC_H +#define CPU_X86_LAPIC_H + +#include <cpu.h> +#include <lapic_def.h> +#include <msr.h> + +/* See if I need to initialize the local apic */ +#if defined(CONFIG_SMP) || defined(CONFIG_IOAPIC) +# define NEED_LAPIC 1 +#endif + +static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg) +{ + return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)); +} + +static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v) +{ + *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v; +} + +static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void) +{ + do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY ); +} + + + +static inline void enable_lapic(void) +{ + + struct msr msr; + msr = rdmsr(LAPIC_BASE_MSR); + msr.hi &= 0xffffff00; + msr.lo &= 0x000007ff; + msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11); + wrmsr(LAPIC_BASE_MSR, msr); +} + +static inline void disable_lapic(void) +{ + struct msr msr; + msr = rdmsr(LAPIC_BASE_MSR); + msr.lo &= ~(1 << 11); + wrmsr(LAPIC_BASE_MSR, msr); +} + +static inline __attribute__((always_inline)) unsigned long lapicid(void) +{ + return lapic_read(LAPIC_ID) >> 24; +} + +static inline __attribute__((always_inline)) void stop_this_cpu(void) +{ + + /* Called by an AP when it is ready to halt and wait for a new task */ + for(;;) { + hlt(); + } +} + +#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr)))) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((struct __xchg_dummy *)(x)) + +/* + * Note: no "lock" prefix even on SMP: xchg always implies lock anyway + * Note 2: xchg has side effect, so that attribute volatile is necessary, + * but generally the primitive is invalid, *ptr is output argument. --ANK + */ +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 1: + __asm__ __volatile__("xchgb %b0,%1" + :"=q" (x) + :"m" (*__xg(ptr)), "0" (x) + :"memory"); + break; + case 2: + __asm__ __volatile__("xchgw %w0,%1" + :"=r" (x) + :"m" (*__xg(ptr)), "0" (x) + :"memory"); + break; + case 4: + __asm__ __volatile__("xchgl %0,%1" + :"=r" (x) + :"m" (*__xg(ptr)), "0" (x) + :"memory"); + break; + } + return x; +} + + +extern inline void lapic_write_atomic(unsigned long reg, unsigned long v) +{ + xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); +} + + +#ifdef CONFIG_X86_GOOD_APIC +# define FORCE_READ_AROUND_WRITE 0 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x,y) lapic_write((x),(y)) +#else +# define FORCE_READ_AROUND_WRITE 1 +# define lapic_read_around(x) lapic_read(x) +# define lapic_write_around(x,y) lapic_write_atomic((x),(y)) +#endif + +static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) +{ + int timeout; + unsigned long status; + int result; + lapic_wait_icr_idle(); + lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); + timeout = 0; + do { +#if 0 + udelay(100); +#endif + status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; + } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); + + result = -1; + if (status == LAPIC_ICR_RR_VALID) { + *pvalue = lapic_read(LAPIC_RRR); + result = 0; + } + return result; +} + + +void setup_lapic(void); + + +#ifdef CONFIG_SMP +struct device; +int start_cpu(struct device *cpu); + +#endif /* CONFIG_SMP */ + +#endif /* CPU_X86_LAPIC_H */ Added: coreboot-v3/include/arch/x86/lapic_def.h =================================================================== --- coreboot-v3/include/arch/x86/lapic_def.h (rev 0) +++ coreboot-v3/include/arch/x86/lapic_def.h 2008-08-11 23:02:34 UTC (rev 745) @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * Copyright (C) 2004 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * Copyright (C) 2005 Stefan Reinauer <stepan(a)coresystems.de> + * Copyright (C) 2007 AMD Marc Jones + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef CPU_X86_LAPIC_DEF_H +#define CPU_X86_LAPIC_DEF_H + +#define LAPIC_BASE_MSR 0x1B +#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) +#define LAPIC_BASE_MSR_ENABLE (1 << 11) +#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 + +#define LAPIC_DEFAULT_BASE 0xfee00000 + +#define LAPIC_ID 0x020 +#define LAPIC_LVR 0x030 +#define LAPIC_TASKPRI 0x80 +#define LAPIC_TPRI_MASK 0xFF +#define LAPIC_ARBID 0x090 +#define LAPIC_RRR 0x0C0 +#define LAPIC_SVR 0x0f0 +#define LAPIC_SPIV 0x0f0 +#define LAPIC_SPIV_ENABLE 0x100 +#define LAPIC_ESR 0x280 +#define LAPIC_ESR_SEND_CS 0x00001 +#define LAPIC_ESR_RECV_CS 0x00002 +#define LAPIC_ESR_SEND_ACC 0x00004 +#define LAPIC_ESR_RECV_ACC 0x00008 +#define LAPIC_ESR_SENDILL 0x00020 +#define LAPIC_ESR_RECVILL 0x00040 +#define LAPIC_ESR_ILLREGA 0x00080 +#define LAPIC_ICR 0x300 +#define LAPIC_DEST_SELF 0x40000 +#define LAPIC_DEST_ALLINC 0x80000 +#define LAPIC_DEST_ALLBUT 0xC0000 +#define LAPIC_ICR_RR_MASK 0x30000 +#define LAPIC_ICR_RR_INVALID 0x00000 +#define LAPIC_ICR_RR_INPROG 0x10000 +#define LAPIC_ICR_RR_VALID 0x20000 +#define LAPIC_INT_LEVELTRIG 0x08000 +#define LAPIC_INT_ASSERT 0x04000 +#define LAPIC_ICR_BUSY 0x01000 +#define LAPIC_DEST_LOGICAL 0x00800 +#define LAPIC_DM_FIXED 0x00000 +#define LAPIC_DM_LOWEST 0x00100 +#define LAPIC_DM_SMI 0x00200 +#define LAPIC_DM_REMRD 0x00300 +#define LAPIC_DM_NMI 0x00400 +#define LAPIC_DM_INIT 0x00500 +#define LAPIC_DM_STARTUP 0x00600 +#define LAPIC_DM_EXTINT 0x00700 +#define LAPIC_VECTOR_MASK 0x000FF +#define LAPIC_ICR2 0x310 +#define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF) +#define SET_LAPIC_DEST_FIELD(x) ((x)<<24) +#define LAPIC_LVTT 0x320 +#define LAPIC_LVTPC 0x340 +#define LAPIC_LVT0 0x350 +#define LAPIC_LVT_TIMER_BASE_MASK (0x3<<18) +#define GET_LAPIC_TIMER_BASE(x) (((x)>>18)&0x3) +#define SET_LAPIC_TIMER_BASE(x) (((x)<<18)) +#define LAPIC_TIMER_BASE_CLKIN 0x0 +#define LAPIC_TIMER_BASE_TMBASE 0x1 +#define LAPIC_TIMER_BASE_DIV 0x2 +#define LAPIC_LVT_TIMER_PERIODIC (1<<17) +#define LAPIC_LVT_MASKED (1<<16) +#define LAPIC_LVT_LEVEL_TRIGGER (1<<15) +#define LAPIC_LVT_REMOTE_IRR (1<<14) +#define LAPIC_INPUT_POLARITY (1<<13) +#define LAPIC_SEND_PENDING (1<<12) +#define LAPIC_LVT_RESERVED_1 (1<<11) +#define LAPIC_DELIVERY_MODE_MASK (7<<8) +#define LAPIC_DELIVERY_MODE_FIXED (0<<8) +#define LAPIC_DELIVERY_MODE_NMI (4<<8) +#define LAPIC_DELIVERY_MODE_EXTINT (7<<8) +#define GET_LAPIC_DELIVERY_MODE(x) (((x)>>8)&0x7) +#define SET_LAPIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) +#define LAPIC_MODE_FIXED 0x0 +#define LAPIC_MODE_NMI 0x4 +#define LAPIC_MODE_EXINT 0x7 +#define LAPIC_LVT1 0x360 +#define LAPIC_LVTERR 0x370 +#define LAPIC_TMICT 0x380 +#define LAPIC_TMCCT 0x390 +#define LAPIC_TDCR 0x3E0 +#define LAPIC_TDR_DIV_TMBASE (1<<2) +#define LAPIC_TDR_DIV_1 0xB +#define LAPIC_TDR_DIV_2 0x0 +#define LAPIC_TDR_DIV_4 0x1 +#define LAPIC_TDR_DIV_8 0x2 +#define LAPIC_TDR_DIV_16 0x3 +#define LAPIC_TDR_DIV_32 0x8 +#define LAPIC_TDR_DIV_64 0x9 +#define LAPIC_TDR_DIV_128 0xA + +#endif /* CPU_X86_LAPIC_DEF_H */

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Re: [coreboot] r740 - coreboot-v3/util/dtc
by Uwe Hermann 11 Aug '08

11 Aug '08

On Mon, Aug 11, 2008 at 06:05:53PM +0200, svn(a)coreboot.org wrote: > Author: rminnich > Date: 2008-08-11 18:05:53 +0200 (Mon, 11 Aug 2008) > New Revision: 740 > > Modified: > coreboot-v3/util/dtc/dtc-parser.y > Log: > Add support for dtc files that end in .dtc, e.g. ide.dtc. > This is managed by stripping the .dtc from the name when it > is used to label the node in the tree. > This one's for you Peter! s/dtc/dts/ I think (wrong checkin message, but the code looks correct). > Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> > > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > > > Modified: coreboot-v3/util/dtc/dtc-parser.y > =================================================================== > --- coreboot-v3/util/dtc/dtc-parser.y 2008-08-11 16:04:38 UTC (rev 739) > +++ coreboot-v3/util/dtc/dtc-parser.y 2008-08-11 16:05:53 UTC (rev 740) > @@ -139,9 +139,17 @@ > switchback(); > > } > - ')' ';' { > + ')' ';' { > + int namelen; > + char *name = strdup((char *)$3.val); > /* convention: first property is labeled with path */ > - $6->label = strdup((char *)$3.val); > + $6->label = name; > + > + /* convention: if it ends in .dts, strip that off */ > + namelen = strlen($6->label); > + if ((namelen > 4) && (! strncmp(&name[namelen-4], ".dts", 4))) > + $6->label[namelen-4] = '\0'; > + > $$ = $6 > } > | Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

1 0

add v3 lapic support
by ron minnich 11 Aug '08

11 Aug '08

attached. ron

2 1

AMD64 BKDG questions
by Carl-Daniel Hailfinger 11 Aug '08

11 Aug '08

Hi Marc, sorry for the new load of questions. I'm trying to fully understand our AMD64 init sequence in the hope of adapting v3 to it. Especially multicode/multiprocessor support seems to be lacking a bit in v3. While reading and comparing the various BKDGs, I found an inconsistency. All BKDGs say the following: MSR0000_001B APIC Base Address Register (APIC_BAR) Bit 8 BSP/BSC is read-write. The AMD64 Architecture Programmer's Manual Volume 2 says the following: Bit 8 BSC is read-only. Which one is correct and does changing that bit even make sense? Family 10h BKDG, chapter 2.5 Processor State Transition Sequences is empty. Family 10h and 11h BKDGs suggest in chapter 2.3.3 "Using L2 Cache as General Storage During Boot" that it is possible to set CAR to WB-DRAM, fill it with code, then change it to WP-IO and execute code from it. Is that right? If so, is there a similar ability in older AMD processors? In the same chapter, the BKDGs also say it is possible to flush CAR contents to RAM during CAR disabling. "If DRAM is initialized and there is data in the cache that needs to get moved to main memory, CLFLUSH or WBINVD may be used instead of INVD". Older BKDGs are a bit fuzzy on this. Will this work on K8 and later? For additional bringup verification, we could follow the suggestion of "Performance monitor event EventSelect 07Fh [L2 Fill/Writeback], sub-event bit 1, titled 'L2 Writebacks to system', can be used to indicate whether L2 dirty data was victimized and sent to the disabled memory controller." I don't see any code in the tree performing this check. General initialization: I couldn't find the expected BSP/AP CAR/DRAM sequence. My current understanding is this: 1. Poweron 2. BSP(BSC) running, all APs halted 3. CAR enabled on BSP 4. HT link setup from BSP 5. DRAM on all cores enabled from BSP (did that change with Fam 10h?) 6. CAR disabled on BSP 7. BSP signals all APs to start 8. APs start execution at the reset vector 9. APs enable CAR 10. ??? Depending on the real sequence, my question is how to pass around data from the APs to the BSP, preferably by letting the APs write to BSP memory directly. Locking between cores/processors. Is there a way to atomically access a common memory location/register from all active cores, even if some of those cores are still in CAR? Will this work in MP systems? Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

K8 and Fam10 CAR
by Carl-Daniel Hailfinger 11 Aug '08

11 Aug '08

Hi Marc, I'm currently working to unify K8 and Fam10 CAR to use the same code at runtime (as opposed to buildtime #ifdefs). While this may not be a goal for v2, I definitely want to try it for v3. A few questions/comments about the CAR code: - Only Fam10 APs are treated specially. APs of older generations seem to be unhandled. Did older generations treat each core as BSP (code seems to suggest that) or were there other special provisions? - "Errata 193: Disable clean copybacks to L3 cache to allow cached ROM." Erratum 193 seems to be unlisted in public data sheets. If it is the famous L3 problem, we might want to enable the workaround only on affected revisions. - CAR goes from 0xC8000 to 0xCFFFF. Assuming GlobalVarSize=0 (untrue, but easier to calculate), BSP stack will be from 0xCC000 to 0xCFFFF and AP stacks will be below 0xCBFFF. * With the current settings (32k CAR total, 1k per AP, 16K for the BSP) the scheme will fall apart if the highest NodeID shifted by the number of CoreID bits is 16 or higher. The BKDG indicates that the number of CoreID bits is 2, so a NodeID of 4 or higher will break. * There is no good place to store the printk() buffer in CAR. On Geode and i586, the printk buffer runs from the lowest address of the CAR area to the middle. Keeping that design will result in the AP stacks colliding with the printk buffer. Limiting the size of the printk buffer dynamically would work unless there are more than 15 cores in the system, where even a printk buffer of zero size would clobber one AP stack. The other alternative is to keep the printk buffer size fixed and let the AP stacks eat into BSP stack space. - Is there any reason on any K8 or later processor supported by the current CAR code not to use 64k CAR? - Is 1k enough stack for the APs, given some stack-heavy functions in v3? - Can the K8 processors work reliably with 0x1e1e1e1e settings in the fixed MTRR or can the Fam10 processors work with 0x06060606? Regards, Carl-Daniel -- http://www.hailfinger.org/

7 22

r744 - in coreboot-v3: arch/x86 include/arch/x86 lib mainboard/artecgroup/dbe62 mainboard/gigabyte/m57sli southbridge/intel/i82371eb southbridge/nvidia/mcp55
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: uwe Date: 2008-08-11 23:01:54 +0200 (Mon, 11 Aug 2008) New Revision: 744 Modified: coreboot-v3/arch/x86/ldscript.ld coreboot-v3/arch/x86/pirq_routing.c coreboot-v3/arch/x86/resourcemap.c coreboot-v3/include/arch/x86/macros.h coreboot-v3/include/arch/x86/pirq_routing.h coreboot-v3/lib/ramtest.c coreboot-v3/lib/stage2.c coreboot-v3/mainboard/artecgroup/dbe62/initram.c coreboot-v3/mainboard/artecgroup/dbe62/stage1.c coreboot-v3/mainboard/gigabyte/m57sli/initram.c coreboot-v3/mainboard/gigabyte/m57sli/stage1.c coreboot-v3/southbridge/intel/i82371eb/i82371eb.c coreboot-v3/southbridge/nvidia/mcp55/dts coreboot-v3/southbridge/nvidia/mcp55/ide.dts coreboot-v3/southbridge/nvidia/mcp55/sata.dts coreboot-v3/southbridge/nvidia/mcp55/stage1.h coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c Log: Minor cosmetic and/or license header fixes (trivial). This includes using consistent (C) lines, adding email addresses, and so on. The file southbridge/nvidia/mcp55/dts was never edited by Yinghai Lu (thus removing his (C) line) and would be too trivial anyway... The changes (though trivial) were also informally acked by Ron on IRC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: coreboot-v3/arch/x86/ldscript.ld =================================================================== --- coreboot-v3/arch/x86/ldscript.ld 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/arch/x86/ldscript.ld 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Ron G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/arch/x86/pirq_routing.c =================================================================== --- coreboot-v3/arch/x86/pirq_routing.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/arch/x86/pirq_routing.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,10 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2000 Ollie Lo, Silicon Integrated Systems - * Copyright (C) 2000 Ron Minnich + * Copyright (C) 2000,2008 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2001 Eric Biederman * Copyright (C) 2002 Andrew Ip - * Copyright (C) 2008 Ron Minnich * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/arch/x86/resourcemap.c =================================================================== --- coreboot-v3/arch/x86/resourcemap.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/arch/x86/resourcemap.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2008 Ronald G. Minnich + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/include/arch/x86/macros.h =================================================================== --- coreboot-v3/include/arch/x86/macros.h 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/include/arch/x86/macros.h 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2000 Ron G. Minnich <rminnich(a)lanl.gov> + * Copyright (C) 2000 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2007 Stefan Reinauer <stepan(a)coresystems.de> * * This program is free software; you can redistribute it and/or modify Modified: coreboot-v3/include/arch/x86/pirq_routing.h =================================================================== --- coreboot-v3/include/arch/x86/pirq_routing.h 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/include/arch/x86/pirq_routing.h 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2000 Ollie Lo, Silicon Integrated Systems - * Copyright (C) 2008 Ron Minnich + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/lib/ramtest.c =================================================================== --- coreboot-v3/lib/ramtest.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/lib/ramtest.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2001 Tyson Sawyer, irobot - * Copyright (C) 2008 Ronald G. Minnich + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/lib/stage2.c =================================================================== --- coreboot-v3/lib/stage2.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/lib/stage2.c 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Ron Minnich <rminnich(a)lanl.gov> + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)lanl.gov> * Copyright (C) 2007 coresystems GmbH * (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) * Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2007 Ronald G. Minnich + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2008 Ronald G. Minnich + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2007 Ronald G. Minnich + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-11 21:01:54 UTC (rev 744) @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007 Advanced Micro Devices, Inc. - * Copyright (C) 2008 Ronald G. Minnich + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-08-11 21:01:54 UTC (rev 744) @@ -3,7 +3,7 @@ * * Copyright (C) 2004 Linux Networx * Copyright (C) 2005 Bitworks - * Copyright (C) 2007 Ronald G. Minnich + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/southbridge/nvidia/mcp55/dts =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/dts 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/southbridge/nvidia/mcp55/dts 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 YingHai Lu * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify @@ -27,4 +26,3 @@ mac_eeprom_smbus = "0"; mac_eeprom_addr "0"; }; - Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.dts =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/ide.dts 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/southbridge/nvidia/mcp55/ide.dts 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-8 Ronald G. Minnich <rminnich(a)gmail.com> * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.dts =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/sata.dts 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/southbridge/nvidia/mcp55/sata.dts 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-8 Ronald G. Minnich <rminnich(a)gmail.com> * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -22,5 +23,4 @@ sata0_enable = "0"; sata1_enable = "0"; - }; Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.h =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.h 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.h 2008-08-11 21:01:54 UTC (rev 744) @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Ronald G. Minnich + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-08-11 16:19:01 UTC (rev 743) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-08-11 21:01:54 UTC (rev 744) @@ -5,7 +5,7 @@ * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * Copyright (C) 2006,2007 AMD * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * Copyright (C) 2008 Ronald G. Minnich (for v3) + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by

1 0

patch: simple fixes in arch
by ron minnich 11 Aug '08

11 Aug '08

attached. ron

2 1

r3501 - trunk/payloads/coreinfo
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: jcrouse Date: 2008-08-11 22:35:32 +0200 (Mon, 11 Aug 2008) New Revision: 3501 Modified: trunk/payloads/coreinfo/coreinfo.c trunk/payloads/coreinfo/lar_module.c trunk/payloads/coreinfo/nvram_module.c trunk/payloads/coreinfo/pci_module.c Log: This patch updates coreinfo to use the ACS_ macros for line graphics. Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/coreinfo/coreinfo.c =================================================================== --- trunk/payloads/coreinfo/coreinfo.c 2008-08-11 20:34:50 UTC (rev 3500) +++ trunk/payloads/coreinfo/coreinfo.c 2008-08-11 20:35:32 UTC (rev 3501) @@ -89,7 +89,7 @@ wmove(win, 1, 1); for (i = 0; i < 78; i++) - waddch(win, '\304'); + waddch(win, ACS_HLINE); } static void print_submenu(struct coreinfo_cat *cat) Modified: trunk/payloads/coreinfo/lar_module.c =================================================================== --- trunk/payloads/coreinfo/lar_module.c 2008-08-11 20:34:50 UTC (rev 3500) +++ trunk/payloads/coreinfo/lar_module.c 2008-08-11 20:35:32 UTC (rev 3501) @@ -66,7 +66,7 @@ /* Draw a line down the middle. */ for (i = 2; i < 21; i++) - mvwaddch(win, i, 30, '\263'); + mvwaddch(win, i, 30, ACS_VLINE); /* Draw the names down the left side. */ for (i = 0; i < lcount; i++) { Modified: trunk/payloads/coreinfo/nvram_module.c =================================================================== --- trunk/payloads/coreinfo/nvram_module.c 2008-08-11 20:34:50 UTC (rev 3500) +++ trunk/payloads/coreinfo/nvram_module.c 2008-08-11 20:35:32 UTC (rev 3501) @@ -36,9 +36,9 @@ /* Print vertical and horizontal line. */ for (i = 0; i < 18; i++) - mvwaddch(win, 3 + i, 3, '\263'); + mvwaddch(win, 3 + i, 3, ACS_VLINE); for (i = 0; i < 48; i++) - mvwaddch(win, 3, 3 + i, (i == 0) ? '\332' : '\304'); + mvwaddch(win, 3, 3 + i, (i == 0) ? ACS_ULCORNER : ACS_HLINE); /* Dump NVRAM contents. */ for (i = 1; i < 257; i++) { Modified: trunk/payloads/coreinfo/pci_module.c =================================================================== --- trunk/payloads/coreinfo/pci_module.c 2008-08-11 20:34:50 UTC (rev 3500) +++ trunk/payloads/coreinfo/pci_module.c 2008-08-11 20:35:32 UTC (rev 3501) @@ -144,11 +144,11 @@ if (i == 0) { if (item != 0) - mvwprintw(win, 2 + i, 19, "\30"); + mvwaddch(win, 2 + i, 19, ACS_UARROW); } if (i == MENU_VISIBLE - 1) { if ((item + 1) < devices_index) - mvwprintw(win, 2 + i, 19, "\31"); + mvwaddch(win, 2 + i, 19, ACS_DARROW); } } @@ -160,12 +160,12 @@ wmove(win, 3, 25); for (i = 0; i < 48; i++) - waddch(win, (i == 0) ? '\332' : '\304'); + waddch(win, (i == 0) ? ACS_ULCORNER : ACS_HLINE); for (i = 0; i < 4; i++) { mvwprintw(win, 4 + i, 23, "%2.2X", i * 16); wmove(win, 4 + i, 25); - waddch(win, '\263'); + waddch(win, ACS_VLINE); } show_config_space(win, 4, 26, menu_selected);

1 0

r3500 - in trunk/payloads/libpayload: . drivers/video
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: uwe Date: 2008-08-11 22:34:50 +0200 (Mon, 11 Aug 2008) New Revision: 3500 Modified: trunk/payloads/libpayload/LICENSES trunk/payloads/libpayload/drivers/video/font8x16.c Log: Document all of the external code we use in libpayload (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/payloads/libpayload/LICENSES =================================================================== --- trunk/payloads/libpayload/LICENSES 2008-08-11 20:34:28 UTC (rev 3499) +++ trunk/payloads/libpayload/LICENSES 2008-08-11 20:34:50 UTC (rev 3500) @@ -48,7 +48,7 @@ * util/kconfig/*: GPLv2 Source: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 - Current version we use: TODO + Current version we use: 587c90616a5b44e6ccfac38e64d4fecee51d588c (03/2008) * include/curses.priv.h: BSD-like license Source: ncurses, http://www.gnu.org/software/ncurses/ @@ -60,6 +60,11 @@ Original files: include/curses.h.in Current version we use: 5.6 +* include/lar.h: GPLv2 or revised BSD license + Source: coreboot v3, svn://coreboot.org/repository/coreboot-v3 + Original file: util/lar/lar.h + Current version we use: r647 + * libc/ipchecksum.c: 2-clause BSD license Source: FreeBSD's base system libraries, http://www.freebsd.org http://www.freebsd.org/cgi/cvsweb.cgi/src/lib/libalias/Attic/alias_util.c?r… @@ -92,6 +97,13 @@ kernel/generic/src/printf/vprintf.c Current version we use: r2745 +* drivers/video/font8x16.c: 3-clause BSD license + Source: HelenOS, http://www.helenos.eu + svn checkout svn://svn.helenos.eu/HelenOS/trunk HelenOS + http://svn.helenos.eu/chora/browse.php?f=%2Ftrunk%2F + Original file: kernel/genarch/src/fb/font-8x16.c + Current version we use: r3293 + * crypto/sha1.c: Public domain Source: OpenBSD http://www.openbsd.org/cgi-bin/cvsweb/src/lib/libc/hash/sha1.c Modified: trunk/payloads/libpayload/drivers/video/font8x16.c =================================================================== --- trunk/payloads/libpayload/drivers/video/font8x16.c 2008-08-11 20:34:28 UTC (rev 3499) +++ trunk/payloads/libpayload/drivers/video/font8x16.c 2008-08-11 20:34:50 UTC (rev 3500) @@ -1,8 +1,8 @@ /* - * This file is part of libpayload + * This file is part of the libpayload project. * * It has originally been taken from the HelenOS project - * (http://www.helenos.eu) + * (http://www.helenos.eu), and slightly modified for our purposes. * * Copyright (c) 2005 Martin Decky * All rights reserved.

1 0

r3499 - in trunk/payloads/libpayload: curses drivers include
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: jcrouse Date: 2008-08-11 22:34:28 +0200 (Mon, 11 Aug 2008) New Revision: 3499 Modified: trunk/payloads/libpayload/curses/tinycurses.c trunk/payloads/libpayload/drivers/serial.c trunk/payloads/libpayload/include/libpayload.h Log: Add support for line drawing characters and the alternate character set. This enables using the ACS_ curses macros with libpayload. The translation from ACS_ macros (or characters with attribute A_ALTCHARSET) is done using one acs map for the video console, one for serial console (xterm/vt100/vt220), and one fallback, from which an ASCII substitute is taken if the device specific map doesn't contain an entry (ie NUL). Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/curses/tinycurses.c =================================================================== --- trunk/payloads/libpayload/curses/tinycurses.c 2008-08-11 17:19:10 UTC (rev 3498) +++ trunk/payloads/libpayload/curses/tinycurses.c 2008-08-11 20:34:28 UTC (rev 3499) @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2008 Ulf Jordan <jordan(a)chalmers.se> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -88,6 +89,69 @@ SCREEN *SP; chtype acs_map[128]; +/* See terminfo(5). */ +chtype fallback_acs_map[128] = + { + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', '>', '<', '^', 'v', ' ', + '#', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + '+', ':', ' ', ' ', ' ', ' ', '\\', '#', + '#', '#', '+', '+', '+', '+', '+', '~', + '-', '-', '-', '_', '+', '+', '+', '+', + '|', '<', '>', '*', '!', 'f', 'o', ' ', + }; + +/* See acsc of vt100. */ +chtype serial_acs_map[128] = + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + '`', 'a', 0, 0, 0, 0, 'f', 'g', + 0, 0, 'j', 'k', 'l', 'm', 'n', 'o', + 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', + 'x', 'y', 'z', '{', '|', '}', '~', 0, + }; + +/* See acsc of linux. */ +chtype console_acs_map[128] = + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, '\020', '\021', '\030', '\031', 0, + '\333', 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + '\004', '\261', 0, 0, 0, 0, '\370', '\361', + '\260', '\316', '\331', '\277', '\332', '\300', '\305', '~', + '\304', '\304', '\304', '_', '\303', '\264', '\301', '\302', + '\263', '\363', '\362', '\342', '\330', '\234', '\376', 0, + }; + // FIXME: Ugly (and insecure!) hack! char sprintf_tmp[1024]; @@ -213,11 +277,14 @@ /** Note: Must _not_ be called twice! */ WINDOW *initscr(void) { - int x, y; + int x, y, i; // newterm(name, stdout, stdin); // def_prog_mode(); + for (i = 0; i < 128; i++) + acs_map[i] = (chtype) i | A_ALTCHARSET; + if (curses_flags & F_ENABLE_SERIAL) { serial_clear(); } @@ -409,12 +476,12 @@ // NCURSES_CH_T wch; // SetChar2(wch, ch); - win->_line[win->_cury].text[win->_curx].chars[0] = ch; + win->_line[win->_cury].text[win->_curx].chars[0] = + ((ch) & (chtype)A_CHARTEXT); - /* Use the window attributes - perhaps we also pull attributes from - the ch itself, I don't know */ - win->_line[win->_cury].text[win->_curx].attr = WINDOW_ATTRS(win); + win->_line[win->_cury].text[win->_curx].attr |= + ((ch) & (chtype)A_ATTRIBUTES); win->_curx++; // FIXME // if (win && (waddch_nosync(win, wch) != ERR)) { @@ -595,10 +662,14 @@ { // FIXME. int serial_is_bold = 0; + int serial_is_altcharset = 0; int x, y; + chtype ch; + int need_altcharset; serial_end_bold(); + serial_end_altcharset(); for (y = 0; y <= win->_maxy; y++) { @@ -614,6 +685,7 @@ ((int)color_pairs[PAIR_NUMBER(attr)]) << 8; if (curses_flags & F_ENABLE_SERIAL) { + ch = win->_line[y].text[x].chars[0]; if (attr & A_BOLD) { if (!serial_is_bold) { @@ -628,10 +700,28 @@ } } - serial_putchar(win->_line[y].text[x].chars[0]); + need_altcharset = 0; + if (attr & A_ALTCHARSET) { + if (serial_acs_map[ch & 0x7f]) { + ch = serial_acs_map[ch & 0x7f]; + need_altcharset = 1; + } else + ch = fallback_acs_map[ch & 0x7f]; + } + if (need_altcharset && !serial_is_altcharset) { + serial_start_altcharset(); + serial_is_altcharset = 1; + } + if (!need_altcharset && serial_is_altcharset) { + serial_end_altcharset(); + serial_is_altcharset = 0; + } + + serial_putchar(ch); } if (curses_flags & F_ENABLE_CONSOLE) { + ch = win->_line[y].text[x].chars[0]; /* Handle some of the attributes. */ if (attr & A_BOLD) @@ -643,6 +733,12 @@ c = (c >> 4) & 0xf00; c |= tmp << 12; } + if (attr & A_ALTCHARSET) { + if (console_acs_map[ch & 0x7f]) + ch = console_acs_map[ch & 0x7f]; + else + ch = fallback_acs_map[ch & 0x7f]; + } /* * FIXME: Somewhere along the line, the @@ -650,7 +746,7 @@ * For now grab just the 8 bit character, * but this will break wide characters! */ - c |= (chtype) (win->_line[y].text[x].chars[0] & 0xff); + c |= (chtype) (ch & 0xff); video_console_putc(win->_begy + y, win->_begx + x, c); } } Modified: trunk/payloads/libpayload/drivers/serial.c =================================================================== --- trunk/payloads/libpayload/drivers/serial.c 2008-08-11 17:19:10 UTC (rev 3498) +++ trunk/payloads/libpayload/drivers/serial.c 2008-08-11 20:34:28 UTC (rev 3499) @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ulf Jordan <jordan(a)chalmers.se> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -105,6 +106,10 @@ #define VT100_SBOLD "\e[1m" #define VT100_EBOLD "\e[m" #define VT100_CURSOR_ADDR "\e[%d;%dH" +/* The following smacs/rmacs are actually for xterm; a real vt100 has + enacs=\E(B\E)0, smacs=^N, rmacs=^O. */ +#define VT100_SMACS "\e(0" +#define VT100_RMACS "\e(B" static void serial_putcmd(char *str) { @@ -127,6 +132,16 @@ serial_putcmd(VT100_EBOLD); } +void serial_start_altcharset(void) +{ + serial_putcmd(VT100_SMACS); +} + +void serial_end_altcharset(void) +{ + serial_putcmd(VT100_RMACS); +} + void serial_set_cursor(int y, int x) { char buffer[32]; Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-08-11 17:19:10 UTC (rev 3498) +++ trunk/payloads/libpayload/include/libpayload.h 2008-08-11 20:34:28 UTC (rev 3499) @@ -105,6 +105,8 @@ void serial_clear(void); void serial_start_bold(void); void serial_end_bold(void); +void serial_start_altcharset(void); +void serial_end_altcharset(void); void serial_set_cursor(int y, int x); /* drivers/speaker.c */

1 0

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coreboot August 2008