coreboot August 2008

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593 discussions

r751 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 12 Aug '08

12 Aug '08

Author: hailfinger Date: 2008-08-13 01:54:25 +0200 (Wed, 13 Aug 2008) New Revision: 751 Modified: coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c Log: northbridge/amd/k8/get_sblk_pci1234.c license updated to GPL v2. This mirrors commit 3504 in coreboot v2. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c =================================================================== --- coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c 2008-08-12 03:39:39 UTC (rev 750) +++ coreboot-v3/northbridge/amd/k8/get_sblk_pci1234.c 2008-08-12 23:54:25 UTC (rev 751) @@ -1,36 +1,24 @@ -/*============================================================================ -Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. -This software and any related documentation (the "Materials") are the -confidential proprietary information of AMD. Unless otherwise provided in a -software agreement specifically licensing the Materials, the Materials are -provided in confidence and may not be distributed, modified, or reproduced in -whole or in part by any means. -LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY -EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO -WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY -PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR -USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY -DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, -BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR -INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE -POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION -OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE -LIMITATION MAY NOT APPLY TO YOU. -AMD does not assume any responsibility for any errors which may appear in the -Materials nor any responsibility to support or update the Materials. AMD -retains the right to modify the Materials at any time, without notice, and is -not obligated to provide such modified Materials to you. -NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any -further information, software, technical information, know-how, or show-how -available to you. -U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED -RIGHTS." Use, duplication, or disclosure by the Government is subject to the -restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or -its successor. Use of the Materials by the Government constitutes -acknowledgement of AMD's proprietary rights in them. -============================================================================*/ -/* Copyright 2007 coresystems GmbH */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 - 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2007 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + // 2005.9 yhlu serengeti support // 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB // 2007.9 stepan improve code documentation

1 0

v2: is this a bug ? (in device_util.c)
by JasonZhao＠viatech.com.cn 12 Aug '08

12 Aug '08

Hardwaremain()-> dev_configure();-> void root_dev_read_resources(device_t root) -> void compact_resources(device_t dev)-> memmove(resource, resource + 1, dev->resources - i); The third parameter should be (dev->resources-I)* sizeof(*resource)

4 3

[PATCH] libpayload: fix incorrect mapping of ACS_PI for VGA console
by Ulf Jordan 12 Aug '08

12 Aug '08

See attached patch. Compile tested against svn HEAD. Nothing under payloads/ use ACS_PI yet, so it's not runtime tested. I've tested the raw character on the linux console manually, and there it looks correct. /ulf

2 1

r3505 - trunk/payloads/libpayload/curses
by svn＠coreboot.org 12 Aug '08

12 Aug '08

Author: jcrouse Date: 2008-08-12 22:23:00 +0200 (Tue, 12 Aug 2008) New Revision: 3505 Modified: trunk/payloads/libpayload/curses/tinycurses.c Log: Fix incorrect mapping of ACS_PI for VGA console. A pi should look like pi and not like Gamma. Signed-off-by: Ulf Jordan <jordan(a)chalmers.se> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/curses/tinycurses.c =================================================================== --- trunk/payloads/libpayload/curses/tinycurses.c 2008-08-12 19:45:12 UTC (rev 3504) +++ trunk/payloads/libpayload/curses/tinycurses.c 2008-08-12 20:23:00 UTC (rev 3505) @@ -149,7 +149,7 @@ '\004', '\261', 0, 0, 0, 0, '\370', '\361', '\260', '\316', '\331', '\277', '\332', '\300', '\305', '~', '\304', '\304', '\304', '_', '\303', '\264', '\301', '\302', - '\263', '\363', '\362', '\342', '\330', '\234', '\376', 0, + '\263', '\363', '\362', '\343', '\330', '\234', '\376', 0, }; // FIXME: Ugly (and insecure!) hack!

1 0

[patch][v2] update license to GPLv2
by Marc Jones 12 Aug '08

12 Aug '08

No reason this shouldn't be GPL. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors License updated to GPL v2. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2008-08-12 12:09:11.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2008-08-12 11:02:39.000000000 -0600 @@ -1,35 +1,23 @@ -/*============================================================================ -Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. -This software and any related documentation (the "Materials") are the -confidential proprietary information of AMD. Unless otherwise provided in a -software agreement specifically licensing the Materials, the Materials are -provided in confidence and may not be distributed, modified, or reproduced in -whole or in part by any means. -LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY -EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO -WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY -PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR -USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY -DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, -BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR -INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE -POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION -OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE -LIMITATION MAY NOT APPLY TO YOU. -AMD does not assume any responsibility for any errors which may appear in the -Materials nor any responsibility to support or update the Materials. AMD -retains the right to modify the Materials at any time, without notice, and is -not obligated to provide such modified Materials to you. -NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any -further information, software, technical information, know-how, or show-how -available to you. -U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED -RIGHTS." Use, duplication, or disclosure by the Government is subject to the -restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or -its successor. Use of the Materials by the Government constitutes -acknowledgement of AMD's proprietary rights in them. -============================================================================*/ -/* Copyright 2007 coresystems GmbH */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 - 2008 Advanced Micro Devices, Inc. + * Copyright 2007 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + // 2005.9 yhlu serengeti support // 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB

3 3

r3504 - trunk/coreboot-v2/src/northbridge/amd/amdk8
by svn＠coreboot.org 12 Aug '08

12 Aug '08

Author: mjones Date: 2008-08-12 21:45:12 +0200 (Tue, 12 Aug 2008) New Revision: 3504 Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c Log: License updated to GPL v2. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2008-08-12 14:19:40 UTC (rev 3503) +++ trunk/coreboot-v2/src/northbridge/amd/amdk8/get_sblk_pci1234.c 2008-08-12 19:45:12 UTC (rev 3504) @@ -1,36 +1,24 @@ -/*============================================================================ -Copyright 2005 ADVANCED MICRO DEVICES, INC. All Rights Reserved. -This software and any related documentation (the "Materials") are the -confidential proprietary information of AMD. Unless otherwise provided in a -software agreement specifically licensing the Materials, the Materials are -provided in confidence and may not be distributed, modified, or reproduced in -whole or in part by any means. -LIMITATION OF LIABILITY: THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY -EXPRESS OR IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO -WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY -PARTICULAR PURPOSE, OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR -USAGE OF TRADE. IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY -DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, -BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR -INABILITY TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE -POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE EXCLUSION -OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE -LIMITATION MAY NOT APPLY TO YOU. -AMD does not assume any responsibility for any errors which may appear in the -Materials nor any responsibility to support or update the Materials. AMD -retains the right to modify the Materials at any time, without notice, and is -not obligated to provide such modified Materials to you. -NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any -further information, software, technical information, know-how, or show-how -available to you. -U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with "RESTRICTED -RIGHTS." Use, duplication, or disclosure by the Government is subject to the -restrictions as set forth in FAR 52.227-14 and DFAR 252.227-7013, et seq., or -its successor. Use of the Materials by the Government constitutes -acknowledgement of AMD's proprietary rights in them. -============================================================================*/ -/* Copyright 2007 coresystems GmbH */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 - 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2007 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + // 2005.9 yhlu serengeti support // 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB // 2007.9 stepan improve code documentation

1 0

[PATCH 1/2] libpayload, coreinfo: ACS support
by Ulf Jordan 12 Aug '08

12 Aug '08

This patch adds support for handling ACS (the alternate/special graphics character set) both on VGA and serial console in libpayload. It also updates coreinfo to use the ACS_ macros for line graphics. Build tested against svn HEAD. To actually get any output, the previously sent libpayload-kconfig patch, or equivalent, is needed too. Runtime tested with coreboot-v3 in QEMU. /ulf

2 6

More about that Google Mail outage
by Gregg Levine 12 Aug '08

12 Aug '08

Hello! This surfaced while reading Google Mail. (While I find that ironic, I did so inform my Google Mail screens to do the work of finding interesting articles.) Anyway here goes: http://tinyurl.com/62rgqp Ideally it should explain something. However I am considering it to be not even close. I'll say everyone my description of what is considered to be "Close rule" for certain applications. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature was once found posting rude messages in English in the Moscow subway."

1 0

[PATCH] v3: move mcp55 subsystem ID setting to v3 model
by Carl-Daniel Hailfinger 12 Aug '08

12 Aug '08

Move mcp55 subsystem ID setting to the v3 model. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Arbeitskopie) @@ -22,6 +22,8 @@ #ifndef MCP55_H #define MCP55_H +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); +struct pci_operations mcp55_pci_dev_ops_pci; - #endif /* MCP55_H */ Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Arbeitskopie) @@ -68,12 +68,6 @@ #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif - -#warning set subsystem id on mcp55 ide -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_ide = { @@ -86,6 +80,6 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Arbeitskopie) @@ -44,11 +44,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); -#warning mange set subsystem in mcp55 usb2 -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } static void usb2_set_resources(struct device *dev) @@ -84,5 +79,5 @@ .phase4_set_resources = usb2_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb2_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Arbeitskopie) @@ -67,13 +67,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); - - -#warning finish set subsystem in mcp55 sata -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_sata = { @@ -86,5 +79,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Arbeitskopie) @@ -34,11 +34,6 @@ static void usb_init(struct device * dev) { -#warning handle subsystem set in mcp55 usb -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_usb = { @@ -51,5 +46,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie) @@ -248,6 +248,18 @@ } +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +/** MCP55 specific device operation for PCI devices. */ +struct pci_operations mcp55_pci_dev_ops_pci = { + .set_subsystem = mcp55_pci_dev_set_subsystem, +}; + struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Arbeitskopie) @@ -127,24 +127,19 @@ if (res) pm_base = res->base; #endif -#warning finish subsystem set in mcp55 smbus -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = mcp55_sm_init, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .phase6_init = mcp55_sm_init, + .ops_pci = &mcp55_pci_dev_ops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; -- http://www.hailfinger.org/ Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Arbeitskopie) @@ -22,6 +22,8 @@ #ifndef MCP55_H #define MCP55_H +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); +struct pci_operations mcp55_pci_dev_ops_pci; - #endif /* MCP55_H */ Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Arbeitskopie) @@ -68,12 +68,6 @@ #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif - -#warning set subsystem id on mcp55 ide -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_ide = { @@ -86,6 +80,6 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Arbeitskopie) @@ -44,11 +44,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); -#warning mange set subsystem in mcp55 usb2 -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } static void usb2_set_resources(struct device *dev) @@ -84,5 +79,5 @@ .phase4_set_resources = usb2_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb2_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Arbeitskopie) @@ -67,13 +67,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); - - -#warning finish set subsystem in mcp55 sata -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_sata = { @@ -86,5 +79,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Arbeitskopie) @@ -34,11 +34,6 @@ static void usb_init(struct device * dev) { -#warning handle subsystem set in mcp55 usb -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_usb = { @@ -51,5 +46,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie) @@ -248,6 +248,18 @@ } +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +/** MCP55 specific device operation for PCI devices. */ +struct pci_operations mcp55_pci_dev_ops_pci = { + .set_subsystem = mcp55_pci_dev_set_subsystem, +}; + struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Revision 749) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Arbeitskopie) @@ -127,24 +127,19 @@ if (res) pm_base = res->base; #endif -#warning finish subsystem set in mcp55 smbus -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = mcp55_sm_init, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .phase6_init = mcp55_sm_init, + .ops_pci = &mcp55_pci_dev_ops_pci, + .ops_smbus_bus = &lops_smbus_bus, };

2 2

[libpayload] patch: add cbtables code to libpayload
by Sean Nelson 12 Aug '08

12 Aug '08

patch to move coreboot table code into libpayload. Allows payloads using libpayload to access coreboot tables. Signed-Off-By: Sean Nelson <snelson(a)nmt.edu> --- patch for coreinfo, coming next message.

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coreboot August 2008