coreboot August 2008

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r763 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: rminnich Date: 2008-08-14 18:16:07 +0200 (Thu, 14 Aug 2008) New Revision: 763 Removed: coreboot-v3/southbridge/nvidia/mcp55/stage1.h Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c coreboot-v3/southbridge/nvidia/mcp55/lpc.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.c coreboot-v3/southbridge/nvidia/mcp55/pci.c coreboot-v3/southbridge/nvidia/mcp55/pcie.c coreboot-v3/southbridge/nvidia/mcp55/sata.c coreboot-v3/southbridge/nvidia/mcp55/stage1.c coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c coreboot-v3/southbridge/nvidia/mcp55/usb2.c Log: Fix up references to pci functions now in stage 0. Remove stage1.h -- not needed. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-14 16:16:07 UTC (rev 763) @@ -41,7 +41,7 @@ u16 word; u8 byte; - word = pci_read_config16(dev, 0x50); + word = pci_conf1_read_config16(dev, 0x50); /* Ensure prefetch is disabled */ word &= ~((1 << 15) | (1 << 13)); if (conf->ide1_enable) { @@ -56,15 +56,15 @@ word |= (1<<12); word |= (1<<14); - pci_write_config16(dev, 0x50, word); + pci_conf1_write_config16(dev, 0x50, word); byte = 0x20 ; // Latency: 64-->32 - pci_write_config8(dev, 0xd, byte); + pci_conf1_write_config8(dev, 0xd, byte); - dword = pci_read_config32(dev, 0xf8); + dword = pci_conf1_read_config32(dev, 0xf8); dword |= 12; - pci_write_config32(dev, 0xf8, dword); + pci_conf1_write_config32(dev, 0xf8, dword); #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-14 16:16:07 UTC (rev 763) @@ -144,10 +144,10 @@ u32 dword; /* IO APIC initialization */ - byte = pci_read_config8(dev, 0x74); + byte = pci_conf1_read_config8(dev, 0x74); byte |= (1<<0); // enable APIC - pci_write_config8(dev, 0x74, byte); - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 + pci_conf1_write_config8(dev, 0x74, byte); + dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14 setup_ioapic(dword, master); } @@ -162,8 +162,8 @@ { unsigned long hpet_address; - pci_write_config32(dev,0x44, 0xfed00001); - hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; + pci_conf1_write_config32(dev,0x44, 0xfed00001); + hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe; printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); } #endif @@ -180,20 +180,20 @@ #warning posted memory write enable disabled in mcp55 lpc? #if 0 /* posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1<<0)); + byte = pci_conf1_read_config8(dev, 0x46); + pci_conf1_write_config8(dev, 0x46, byte | (1<<0)); #endif /* power after power fail */ #if 1 on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); - byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; if (!on) { byte |= 0x40; } - pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte); printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); #endif /* Throttle the CPU speed down for testing */ @@ -202,7 +202,7 @@ if(on) { u16 pm10_bar; u32 dword; - pm10_bar = (pci_read_config16(dev, 0x60)&0xff00); + pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00); outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; @@ -213,16 +213,16 @@ #if 0 // default is enabled /* Enable Port 92 fast reset */ - byte = pci_read_config8(dev, 0xe8); + byte = pci_conf1_read_config8(dev, 0xe8); byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); + pci_conf1_write_config8(dev, 0xe8, byte); #endif /* Enable Error reporting */ /* Set up sync flood detected */ - byte = pci_read_config8(dev, 0x47); + byte = pci_conf1_read_config8(dev, 0x47); byte |= (1 << 1); - pci_write_config8(dev, 0x47, byte); + pci_conf1_write_config8(dev, 0x47, byte); /* Set up NMI on errors */ byte = inb(0x70); // RTC70 @@ -286,7 +286,7 @@ int i; int var_num = 0; - reg = pci_read_config32(dev, 0xa0); + reg = pci_conf1_read_config32(dev, 0xa0); for (link = 0; link < dev->links; link++) { struct device *child; @@ -324,9 +324,9 @@ } } } - pci_write_config32(dev, 0xa0, reg); + pci_conf1_write_config32(dev, 0xa0, reg); for(i=0;i<var_num;i++) { - pci_write_config32(dev, 0xa8 + i*4, reg_var[i]); + pci_conf1_write_config32(dev, 0xa8 + i*4, reg_var[i]); } Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-14 16:16:07 UTC (rev 763) @@ -52,7 +52,7 @@ (lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) ) ) { u32 id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); + id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID); if ( (id < (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) || (id > (PCI_VENDOR_ID_NVIDIA | (PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16))) ) { @@ -82,7 +82,7 @@ /* sorry. Again, anonymous unions etc. would make this easier. */ if(dev->id.pci.device==0x0000) { - vendorid = pci_read_config32(dev, PCI_VENDOR_ID); + vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; // vendorid &= 0xffff; } else { @@ -180,14 +180,14 @@ if(!sm_dev) return; if ( sm_dev ) { - reg_old = reg = pci_read_config32(sm_dev, 0xe4); + reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4); if (!dev->enabled) { //disable it reg |= (1<<index2); } if (reg != reg_old) { - pci_write_config32(sm_dev, 0xe4, reg); + pci_conf1_write_config32(sm_dev, 0xe4, reg); } } @@ -199,14 +199,14 @@ if ( index == 0) { // for LPC // expose ioapic base - byte = pci_read_config8(lpc_dev, 0x74); + byte = pci_conf1_read_config8(lpc_dev, 0x74); byte |= ((1<<1)); // expose the BAR - pci_write_config8(dev, 0x74, byte); + pci_conf1_write_config8(dev, 0x74, byte); // expose trap base - byte = pci_read_config8(lpc_dev, 0xdd); + byte = pci_conf1_read_config8(lpc_dev, 0xdd); byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write - pci_write_config8(dev, 0xdd, byte); + pci_conf1_write_config8(dev, 0xdd, byte); return; @@ -216,16 +216,16 @@ sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); if(!sm_dev) return; - final_reg = pci_read_config32(sm_dev, 0xe8); + final_reg = pci_conf1_read_config32(sm_dev, 0xe8); final_reg &= ~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9)); - pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at first + pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all at first #if 0 - reg_old = reg = pci_read_config32(sm_dev, 0xe4); + reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4); // reg |= (1<<0); reg &= ~(0x3f<<4); if (reg != reg_old) { printk_debug("mcp55.c pcie enabled\n"); - pci_write_config32(sm_dev, 0xe4, reg); + pci_conf1_write_config32(sm_dev, 0xe4, reg); } #endif } @@ -238,9 +238,9 @@ if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8 sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1); if(!sm_dev) return; - reg_old = pci_read_config32(sm_dev, 0xe8); + reg_old = pci_conf1_read_config32(sm_dev, 0xe8); if (final_reg != reg_old) { - pci_write_config32(sm_dev, 0xe8, final_reg); + pci_conf1_write_config32(sm_dev, 0xe8, final_reg); } } @@ -251,7 +251,7 @@ void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { - pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, ((device & 0xffff) << 16) | (vendor & 0xffff)); } Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-14 16:16:07 UTC (rev 763) @@ -43,23 +43,23 @@ #endif /* System error enable */ - dword = pci_read_config32(dev, 0x04); + dword = pci_conf1_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); + pci_conf1_write_config32(dev, 0x04, dword); #if 1 //only need (a01,xx] - word = pci_read_config16(dev, 0x48); + word = pci_conf1_read_config16(dev, 0x48); word |= (1<<0); /* MRL2MRM */ word |= (1<<2); /* MR2MRM */ - pci_write_config16(dev, 0x48, word); + pci_conf1_write_config16(dev, 0x48, word); #endif #if 1 - dword = pci_read_config32(dev, 0x4c); + dword = pci_conf1_read_config32(dev, 0x4c); dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/ - pci_write_config32(dev, 0x4c, dword); + pci_conf1_write_config32(dev, 0x4c, dword); #endif #ifdef CONFIG_PCI_64BIT_PREF_MEM @@ -84,7 +84,7 @@ printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); #endif printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); - pci_write_config32(dev, 0x50, dword); //TOM + pci_conf1_write_config32(dev, 0x50, dword); //TOM } Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-14 16:16:07 UTC (rev 763) @@ -39,10 +39,10 @@ u32 dword; /* System error enable */ - dword = pci_read_config32(dev, 0x04); + dword = pci_conf1_read_config32(dev, 0x04); dword |= (1<<8); /* System error enable */ dword |= (1<<30); /* Clear possible errors */ - pci_write_config32(dev, 0x04, dword); + pci_conf1_write_config32(dev, 0x04, dword); } Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-14 16:16:07 UTC (rev 763) @@ -40,7 +40,7 @@ struct southbridge_nvidia_mcp55_sata_config *conf = (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration; - dword = pci_read_config32(dev, 0x50); + dword = pci_conf1_read_config32(dev, 0x50); /* Ensure prefetch is disabled */ dword &= ~((1 << 15) | (1 << 13)); if(conf) { @@ -62,11 +62,11 @@ dword &= ~(0x1f<<24); dword |= (0x15<<24); #endif - pci_write_config32(dev, 0x50, dword); + pci_conf1_write_config32(dev, 0x50, dword); - dword = pci_read_config32(dev, 0xf8); + dword = pci_conf1_read_config32(dev, 0xf8); dword |= 2; - pci_write_config32(dev, 0xf8, dword); + pci_conf1_write_config32(dev, 0xf8, dword); } struct device_operations mcp55_sata = { Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-14 16:16:07 UTC (rev 763) @@ -27,7 +27,6 @@ #include <cpu.h> #include <amd/k8/k8.h> #include "mcp55.h" -#include "stage1.h" #warning fix disgusting define of MCP55_NUM it is mainboard dependent #define MCP55_NUM 1 @@ -148,9 +147,9 @@ u32 dword; int i; u32 bdf = PCI_BDF(busnx, devnx+1, 1); - dword = pci_read_config32(bdf, 0xe4); + dword = pci_conf1_read_config32(bdf, 0xe4); dword |= 0x3f0; // disable it at first - pci_write_config32(bdf, 0xe4, dword); + pci_conf1_write_config32(bdf, 0xe4, dword); for(i=0; i<3; i++) { tgio_ctrl = inl(anactrl_io_base + 0xcc); @@ -172,9 +171,9 @@ // wait 100us udelay(100); - dword = pci_read_config32(bdf, 0xe4); + dword = pci_conf1_read_config32(bdf, 0xe4); dword &= ~(0x3f0); // enable - pci_write_config32(bdf, 0xe4, dword); + pci_conf1_write_config32(bdf, 0xe4, dword); // need to wait 100ms udelay(100000); @@ -397,7 +396,7 @@ u32 id; u32 bdf; bdf = PCI_BDF(busnx, devnx, 0); - id = pci_read_config32(bdf, PCI_VENDOR_ID); + id = pci_conf1_read_config32(bdf, PCI_VENDOR_ID); if(id == 0x036910de) { busn[mcp55_num] = busnx; devn[mcp55_num] = devnx; @@ -434,7 +433,7 @@ /* Find the device. */ u32 bdf; - if (!pci_locate_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) { + if (!pci_conf1_find_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) { die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n"); } Deleted: coreboot-v3/southbridge/nvidia/mcp55/stage1.h =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.h 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.h 2008-08-14 16:16:07 UTC (rev 763) @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#define pci_read_config32(bdf, where) pci_cf8_conf1.read32(bdf, where) -#define pci_write_config32(bdf, where, what) pci_cf8_conf1.write32(bdf, where, what) -#define pci_read_config16(bdf, where) pci_cf8_conf1.read32(bdf, where) -#define pci_write_config16(bdf, where, what) pci_cf8_conf1.write32(bdf, where, what) -#define pci_locate_device(vid, did, slot) pci_cf8_conf1.find(vid, did, slot) Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-08-14 16:16:07 UTC (rev 763) @@ -27,7 +27,6 @@ #include <device/device.h> #include <device/pci.h> #include "mcp55.h" -#include "stage1.h" #include "mcp55_smbus.h" #define SMBUS0_IO_BASE 0x1000 @@ -192,16 +191,16 @@ void enable_smbus(void) { u32 bdf; - if (!pci_locate_device(0x10de, 0x0368, &bdf)) { + if (!pci_conf1_find_device(0x10de, 0x0368, &bdf)) { die("SMBUS controller not found\r\n"); } printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ - pci_write_config32(bdf, 0x20, SMBUS0_IO_BASE | 1); - pci_write_config32(bdf, 0x24, SMBUS1_IO_BASE | 1); + pci_conf1_write_config32(bdf, 0x20, SMBUS0_IO_BASE | 1); + pci_conf1_write_config32(bdf, 0x24, SMBUS1_IO_BASE | 1); /* Set smbus iospace enable */ - pci_write_config16(bdf, 0x4, 0x01); + pci_conf1_write_config16(bdf, 0x4, 0x01); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT); outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT); Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c 2008-08-14 16:16:07 UTC (rev 763) @@ -33,15 +33,14 @@ #define EHCI_DEBUG_OFFSET 0x98 #include "pci.h" -#include "stage1.h" static void set_debug_port(unsigned port) { u32 dword; u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1); - dword = pci_read_config32(bdf, 0x74); + dword = pci_conf1_read_config32(bdf, 0x74); dword &= ~(0xf<<12); dword |= (port<<12); - pci_write_config32(bdf, 0x74, dword); + pci_conf1_write_config32(bdf, 0x74, dword); } @@ -49,7 +48,7 @@ { u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1); set_debug_port(port); - pci_write_config32(bdf, EHCI_BAR_INDEX, EHCI_BAR); - pci_write_config8(bdf, 0x04, 0x2); // mem space enable + pci_conf1_write_config32(bdf, EHCI_BAR_INDEX, EHCI_BAR); + pci_conf1_write_config8(bdf, 0x04, 0x2); // mem space enable } Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-08-14 09:37:46 UTC (rev 762) +++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-08-14 16:16:07 UTC (rev 763) @@ -41,9 +41,9 @@ static void usb2_init(struct device *dev) { u32 dword; - dword = pci_read_config32(dev, 0xf8); + dword = pci_conf1_read_config32(dev, 0xf8); dword |= 40; - pci_write_config32(dev, 0xf8, dword); + pci_conf1_write_config32(dev, 0xf8, dword); } static void usb2_set_resources(struct device *dev)

1 0

[PATCH] [libpayload] fix memory allocator free list corruption
by Stefan Reinauer 14 Aug '08

14 Aug '08

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 * fix memory allocator bug that lead to freelist corruption on the first malloc (and spent 8 bytes too much per malloc) * if the memory allocator detects freelist corruption, print a message instead of silently dying. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: libc/malloc.c =================================================================== --- libc/malloc.c (revision 3509) +++ libc/malloc.c (working copy) @@ -92,13 +92,15 @@ header = *((hdrtype_t *) ptr); int size = SIZE(header); - if (!HAS_MAGIC(header) || size == 0) + if (!HAS_MAGIC(header) || size == 0) { + printf("memory allocator panic.\n"); halt(); + } if (header & FLAG_FREE) { if (len <= size) { void *nptr = ptr + (HDRSIZE + len); - int nsize = size - (len + 8); + int nsize = size - (HDRSIZE + len); /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(len); @@ -109,7 +111,7 @@ if (nsize > 0) *((hdrtype_t *) nptr) = - FREE_BLOCK(nsize - 4); + FREE_BLOCK(nsize); return (void *)(ptr + HDRSIZE); }

2 2

r3510 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: stepan Date: 2008-08-14 16:40:10 +0200 (Thu, 14 Aug 2008) New Revision: 3510 Modified: trunk/payloads/libpayload/libc/malloc.c Log: * fix memory allocator bug that lead to freelist corruption on the first malloc (and spent 8 bytes too much per malloc) * if the memory allocator detects freelist corruption, print a message instead of silently dying. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: trunk/payloads/libpayload/libc/malloc.c =================================================================== --- trunk/payloads/libpayload/libc/malloc.c 2008-08-13 12:16:15 UTC (rev 3509) +++ trunk/payloads/libpayload/libc/malloc.c 2008-08-14 14:40:10 UTC (rev 3510) @@ -92,13 +92,15 @@ header = *((hdrtype_t *) ptr); int size = SIZE(header); - if (!HAS_MAGIC(header) || size == 0) + if (!HAS_MAGIC(header) || size == 0) { + printf("memory allocator panic.\n"); halt(); + } if (header & FLAG_FREE) { if (len <= size) { void *nptr = ptr + (HDRSIZE + len); - int nsize = size - (len + 8); + int nsize = size - (HDRSIZE + len); /* Mark the block as used. */ *((hdrtype_t *) ptr) = USED_BLOCK(len); @@ -109,7 +111,7 @@ if (nsize > 0) *((hdrtype_t *) nptr) = - FREE_BLOCK(nsize - 4); + FREE_BLOCK(nsize); return (void *)(ptr + HDRSIZE); }

1 0

Re: [coreboot] [PATCH] v3: move mcp55 subsystem ID setting to v3 model
by Carl-Daniel Hailfinger 14 Aug '08

14 Aug '08

Use the correct MCP55 PCI subsystem ID setting function. This fixes a genuine bug in the MCP55 code. Moving this away from PCI ops is the next goal. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Arbeitskopie) @@ -22,6 +22,10 @@ #ifndef MCP55_H #define MCP55_H +#define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40 +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); +struct pci_operations mcp55_pci_dev_ops_pci; #endif /* MCP55_H */ Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Arbeitskopie) @@ -68,12 +68,6 @@ #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif - -#warning set subsystem id on mcp55 ide -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_ide = { @@ -86,6 +80,6 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pci.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pci.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pci.c (Arbeitskopie) @@ -99,5 +99,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Arbeitskopie) @@ -44,11 +44,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); -#warning mange set subsystem in mcp55 usb2 -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } static void usb2_set_resources(struct device *dev) @@ -84,5 +79,5 @@ .phase4_set_resources = usb2_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb2_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/lpc.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/lpc.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/lpc.c (Arbeitskopie) @@ -338,13 +338,6 @@ mcp55_lpc_enable_childrens_resources(dev); } -/* This is awaiting the subsystem support in dtc/dts -static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -*/ struct device_operations mcp55_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, @@ -355,7 +348,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pro = { @@ -368,7 +361,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc2 = { @@ -381,7 +374,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc3 = { @@ -394,7 +387,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc4 = { @@ -407,7 +400,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc5 = { @@ -420,7 +413,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc6 = { @@ -433,7 +426,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpcslave = { @@ -446,5 +439,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = lpc_slave_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pcie.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pcie.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pcie.c (Arbeitskopie) @@ -57,7 +57,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_b_c = { @@ -71,7 +71,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_d = { @@ -85,7 +85,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_e = { @@ -99,7 +99,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_f = { @@ -113,5 +113,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Arbeitskopie) @@ -67,13 +67,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); - - -#warning finish set subsystem in mcp55 sata -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_sata = { @@ -86,5 +79,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Arbeitskopie) @@ -34,11 +34,6 @@ static void usb_init(struct device * dev) { -#warning handle subsystem set in mcp55 usb -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_usb = { @@ -51,5 +46,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie) @@ -248,6 +248,18 @@ } +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +/** MCP55 specific device operation for PCI devices. */ +struct pci_operations mcp55_pci_dev_ops_pci = { + .set_subsystem = mcp55_pci_dev_set_subsystem, +}; + struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Arbeitskopie) @@ -127,24 +127,19 @@ if (res) pm_base = res->base; #endif -#warning finish subsystem set in mcp55 smbus -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = mcp55_sm_init, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .phase6_init = mcp55_sm_init, + .ops_pci = &mcp55_pci_dev_ops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; -- http://www.hailfinger.org/ Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Arbeitskopie) @@ -22,6 +22,10 @@ #ifndef MCP55_H #define MCP55_H +#define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40 +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); +struct pci_operations mcp55_pci_dev_ops_pci; #endif /* MCP55_H */ Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Arbeitskopie) @@ -68,12 +68,6 @@ #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif - -#warning set subsystem id on mcp55 ide -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_ide = { @@ -86,6 +80,6 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pci.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pci.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pci.c (Arbeitskopie) @@ -99,5 +99,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Arbeitskopie) @@ -44,11 +44,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); -#warning mange set subsystem in mcp55 usb2 -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } static void usb2_set_resources(struct device *dev) @@ -84,5 +79,5 @@ .phase4_set_resources = usb2_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb2_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/lpc.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/lpc.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/lpc.c (Arbeitskopie) @@ -338,13 +338,6 @@ mcp55_lpc_enable_childrens_resources(dev); } -/* This is awaiting the subsystem support in dtc/dts -static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -*/ struct device_operations mcp55_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, @@ -355,7 +348,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pro = { @@ -368,7 +361,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc2 = { @@ -381,7 +374,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc3 = { @@ -394,7 +387,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc4 = { @@ -407,7 +400,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc5 = { @@ -420,7 +413,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc6 = { @@ -433,7 +426,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpcslave = { @@ -446,5 +439,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = lpc_slave_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pcie.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pcie.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/pcie.c (Arbeitskopie) @@ -57,7 +57,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_b_c = { @@ -71,7 +71,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_d = { @@ -85,7 +85,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_e = { @@ -99,7 +99,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_f = { @@ -113,5 +113,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Arbeitskopie) @@ -67,13 +67,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); - - -#warning finish set subsystem in mcp55 sata -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_sata = { @@ -86,5 +79,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Arbeitskopie) @@ -34,11 +34,6 @@ static void usb_init(struct device * dev) { -#warning handle subsystem set in mcp55 usb -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_usb = { @@ -51,5 +46,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie) @@ -248,6 +248,18 @@ } +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +/** MCP55 specific device operation for PCI devices. */ +struct pci_operations mcp55_pci_dev_ops_pci = { + .set_subsystem = mcp55_pci_dev_set_subsystem, +}; + struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c =================================================================== --- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Revision 759) +++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Arbeitskopie) @@ -127,24 +127,19 @@ if (res) pm_base = res->base; #endif -#warning finish subsystem set in mcp55 smbus -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = mcp55_sm_init, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .phase6_init = mcp55_sm_init, + .ops_pci = &mcp55_pci_dev_ops_pci, + .ops_smbus_bus = &lops_smbus_bus, };

2 2

r762 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: hailfinger Date: 2008-08-14 11:37:46 +0200 (Thu, 14 Aug 2008) New Revision: 762 Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c coreboot-v3/southbridge/nvidia/mcp55/lpc.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.h coreboot-v3/southbridge/nvidia/mcp55/pci.c coreboot-v3/southbridge/nvidia/mcp55/pcie.c coreboot-v3/southbridge/nvidia/mcp55/sata.c coreboot-v3/southbridge/nvidia/mcp55/smbus.c coreboot-v3/southbridge/nvidia/mcp55/usb.c coreboot-v3/southbridge/nvidia/mcp55/usb2.c Log: Use the correct MCP55 PCI subsystem ID setting function. This fixes a genuine bug in the MCP55 code. Moving this away from PCI ops is the next goal. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-14 09:37:46 UTC (rev 762) @@ -68,12 +68,6 @@ #ifdef CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif - -#warning set subsystem id on mcp55 ide -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_ide = { @@ -86,6 +80,6 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = ide_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-14 09:37:46 UTC (rev 762) @@ -338,13 +338,6 @@ mcp55_lpc_enable_childrens_resources(dev); } -/* This is awaiting the subsystem support in dtc/dts -static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) -{ - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -*/ struct device_operations mcp55_lpc = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, @@ -355,7 +348,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pro = { @@ -368,7 +361,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc2 = { @@ -381,7 +374,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc3 = { @@ -394,7 +387,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc4 = { @@ -407,7 +400,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc5 = { @@ -420,7 +413,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpc6 = { @@ -433,7 +426,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = mcp55_lpc_enable_resources, .phase6_init = lpc_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_lpcslave = { @@ -446,5 +439,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = lpc_slave_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-14 09:37:46 UTC (rev 762) @@ -248,6 +248,18 @@ } +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) +{ + pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +/** MCP55 specific device operation for PCI devices. */ +struct pci_operations mcp55_pci_dev_ops_pci = { + .set_subsystem = mcp55_pci_dev_set_subsystem, +}; + struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-08-14 09:37:46 UTC (rev 762) @@ -22,6 +22,10 @@ #ifndef MCP55_H #define MCP55_H +#define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40 +void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device); +struct pci_operations mcp55_pci_dev_ops_pci; #endif /* MCP55_H */ Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-14 09:37:46 UTC (rev 762) @@ -99,5 +99,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pci_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-14 09:37:46 UTC (rev 762) @@ -57,7 +57,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_b_c = { @@ -71,7 +71,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_d = { @@ -85,7 +85,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_e = { @@ -99,7 +99,7 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; struct device_operations mcp55_pcie_f = { @@ -113,5 +113,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_bus_enable_resources, .phase6_init = pcie_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-14 09:37:46 UTC (rev 762) @@ -67,13 +67,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 2; pci_write_config32(dev, 0xf8, dword); - - -#warning finish set subsystem in mcp55 sata -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_sata = { @@ -86,5 +79,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/smbus.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/smbus.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/smbus.c 2008-08-14 09:37:46 UTC (rev 762) @@ -127,24 +127,19 @@ if (res) pm_base = res->base; #endif -#warning finish subsystem set in mcp55 smbus -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_smbus = { .id = {.type = DEVICE_ID_PCI, {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}}, - .constructor = default_device_constructor, - .phase3_scan = scan_static_bus, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, .phase4_read_resources = mcp55_sm_read_resources, .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = mcp55_sm_init, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, + .phase6_init = mcp55_sm_init, + .ops_pci = &mcp55_pci_dev_ops_pci, + .ops_smbus_bus = &lops_smbus_bus, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/usb.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/usb.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/usb.c 2008-08-14 09:37:46 UTC (rev 762) @@ -34,11 +34,6 @@ static void usb_init(struct device * dev) { -#warning handle subsystem set in mcp55 usb -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } struct device_operations mcp55_usb = { @@ -51,5 +46,5 @@ .phase4_set_resources = pci_dev_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, }; Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-08-14 09:28:28 UTC (rev 761) +++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-08-14 09:37:46 UTC (rev 762) @@ -44,11 +44,6 @@ dword = pci_read_config32(dev, 0xf8); dword |= 40; pci_write_config32(dev, 0xf8, dword); -#warning mange set subsystem in mcp55 usb2 -#if 0 - pci_write_config32(dev, 0x40, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -#endif } static void usb2_set_resources(struct device *dev) @@ -84,5 +79,5 @@ .phase4_set_resources = usb2_set_resources, .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = usb2_init, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &mcp55_pci_dev_ops_pci, };

1 0

[PATCH] v3: factor out PCI subsystem ID setting
by Carl-Daniel Hailfinger 14 Aug '08

14 Aug '08

Factor out PCI subsystem ID setting. This cleans up the code as well, arguably fixes some strange behaviour and prepares the code for per-device subsystem ID setting. It's the first step to achieve the per-device subsystem goal. Boot tested on qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-pci_device_subsystem_id/device/pci_device.c =================================================================== --- corebootv3-pci_device_subsystem_id/device/pci_device.c (Revision 759) +++ corebootv3-pci_device_subsystem_id/device/pci_device.c (Arbeitskopie) @@ -620,26 +620,47 @@ printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); } -void pci_dev_enable_resources(struct device *dev) +void pci_dev_set_subsystem_wrapper(struct device *dev) { const struct pci_operations *ops; - u16 command; + u16 vendor = 0; + u16 device = 0; +#warning Per-device subsystem ID has to be set here, but for that we have to extend the dts. + +#ifdef HAVE_MAINBOARD_PCI_SUBSYSTEM_ID + /* If there's no explicit subsystem ID for this device and the device + * is onboard, use the board defaults. */ + if (dev->on_mainboard) { + if (!vendor) + vendor = mainboard_pci_subsystem_vendor; + if (!device) + device = mainboard_pci_subsystem_device; + } +#endif /* Set the subsystem vendor and device ID for mainboard devices. */ ops = ops_pci(dev); -#ifdef HAVE_MAINBOARD_PCI_SUBSYSTEM_ID - if (dev->on_mainboard && ops && ops->set_subsystem) { + /* If either vendor or device is zero, we leave it as is. */ + if (ops && ops->set_subsystem && vendor && device) { printk(BIOS_DEBUG, "%s: Setting subsystem VID/DID to %02x/%02x\n", - dev_path(dev), mainboard_pci_subsystem_vendor, - mainboard_pci_subsystem_device); + dev_path(dev), vendor, device); - ops->set_subsystem(dev, mainboard_pci_subsystem_vendor, - mainboard_pci_subsystem_device); + ops->set_subsystem(dev, vendor, device); + } else { + printk(BIOS_DEBUG, "%s: Not setting subsystem VID/DID\n", + dev_path(dev)); } -#endif + +} +void pci_dev_enable_resources(struct device *dev) +{ + u16 command; + + pci_dev_set_subsystem_wrapper(dev); + command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check. @@ -1008,6 +1029,7 @@ dev->irq_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); dev->min_gnt = pci_read_config8(dev, PCI_MIN_GNT); dev->max_lat = pci_read_config8(dev, PCI_MAX_LAT); +#warning Per-device subsystem ID should only be read from the device if none has been specified for the device in the dts. dev->subsystem_vendor = pci_read_config16(dev, PCI_SUBSYSTEM_VENDOR_ID); dev->subsystem_device = pci_read_config16(dev, PCI_SUBSYSTEM_ID); -- http://www.hailfinger.org/ Index: corebootv3-pci_device_subsystem_id/device/pci_device.c =================================================================== --- corebootv3-pci_device_subsystem_id/device/pci_device.c (Revision 759) +++ corebootv3-pci_device_subsystem_id/device/pci_device.c (Arbeitskopie) @@ -620,26 +620,47 @@ printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); } -void pci_dev_enable_resources(struct device *dev) +void pci_dev_set_subsystem_wrapper(struct device *dev) { const struct pci_operations *ops; - u16 command; + u16 vendor = 0; + u16 device = 0; +#warning Per-device subsystem ID has to be set here, but for that we have to extend the dts. + +#ifdef HAVE_MAINBOARD_PCI_SUBSYSTEM_ID + /* If there's no explicit subsystem ID for this device and the device + * is onboard, use the board defaults. */ + if (dev->on_mainboard) { + if (!vendor) + vendor = mainboard_pci_subsystem_vendor; + if (!device) + device = mainboard_pci_subsystem_device; + } +#endif /* Set the subsystem vendor and device ID for mainboard devices. */ ops = ops_pci(dev); -#ifdef HAVE_MAINBOARD_PCI_SUBSYSTEM_ID - if (dev->on_mainboard && ops && ops->set_subsystem) { + /* If either vendor or device is zero, we leave it as is. */ + if (ops && ops->set_subsystem && vendor && device) { printk(BIOS_DEBUG, "%s: Setting subsystem VID/DID to %02x/%02x\n", - dev_path(dev), mainboard_pci_subsystem_vendor, - mainboard_pci_subsystem_device); + dev_path(dev), vendor, device); - ops->set_subsystem(dev, mainboard_pci_subsystem_vendor, - mainboard_pci_subsystem_device); + ops->set_subsystem(dev, vendor, device); + } else { + printk(BIOS_DEBUG, "%s: Not setting subsystem VID/DID\n", + dev_path(dev)); } -#endif + +} +void pci_dev_enable_resources(struct device *dev) +{ + u16 command; + + pci_dev_set_subsystem_wrapper(dev); + command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check. @@ -1008,6 +1029,7 @@ dev->irq_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); dev->min_gnt = pci_read_config8(dev, PCI_MIN_GNT); dev->max_lat = pci_read_config8(dev, PCI_MAX_LAT); +#warning Per-device subsystem ID should only be read from the device if none has been specified for the device in the dts. dev->subsystem_vendor = pci_read_config16(dev, PCI_SUBSYSTEM_VENDOR_ID); dev->subsystem_device = pci_read_config16(dev, PCI_SUBSYSTEM_ID);

2 2

r761 - coreboot-v3/device
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: hailfinger Date: 2008-08-14 11:28:28 +0200 (Thu, 14 Aug 2008) New Revision: 761 Modified: coreboot-v3/device/pci_device.c Log: Factor out PCI subsystem ID setting. This cleans up the code as well, arguably fixes some strange behaviour and prepares the code for per-device subsystem ID setting. It's the first step to achieve the per-device subsystem goal. Boot tested on qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2008-08-14 09:25:58 UTC (rev 760) +++ coreboot-v3/device/pci_device.c 2008-08-14 09:28:28 UTC (rev 761) @@ -620,26 +620,47 @@ printk(BIOS_SPEW, "Adding RAM resource (%lld bytes)\n", res->size); } -void pci_dev_enable_resources(struct device *dev) +void pci_dev_set_subsystem_wrapper(struct device *dev) { const struct pci_operations *ops; - u16 command; + u16 vendor = 0; + u16 device = 0; +#warning Per-device subsystem ID has to be set here, but for that we have to extend the dts. + +#ifdef HAVE_MAINBOARD_PCI_SUBSYSTEM_ID + /* If there's no explicit subsystem ID for this device and the device + * is onboard, use the board defaults. */ + if (dev->on_mainboard) { + if (!vendor) + vendor = mainboard_pci_subsystem_vendor; + if (!device) + device = mainboard_pci_subsystem_device; + } +#endif /* Set the subsystem vendor and device ID for mainboard devices. */ ops = ops_pci(dev); -#ifdef HAVE_MAINBOARD_PCI_SUBSYSTEM_ID - if (dev->on_mainboard && ops && ops->set_subsystem) { + /* If either vendor or device is zero, we leave it as is. */ + if (ops && ops->set_subsystem && vendor && device) { printk(BIOS_DEBUG, "%s: Setting subsystem VID/DID to %02x/%02x\n", - dev_path(dev), mainboard_pci_subsystem_vendor, - mainboard_pci_subsystem_device); + dev_path(dev), vendor, device); - ops->set_subsystem(dev, mainboard_pci_subsystem_vendor, - mainboard_pci_subsystem_device); + ops->set_subsystem(dev, vendor, device); + } else { + printk(BIOS_DEBUG, "%s: Not setting subsystem VID/DID\n", + dev_path(dev)); } -#endif + +} +void pci_dev_enable_resources(struct device *dev) +{ + u16 command; + + pci_dev_set_subsystem_wrapper(dev); + command = pci_read_config16(dev, PCI_COMMAND); command |= dev->command; command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check. @@ -1008,6 +1029,7 @@ dev->irq_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); dev->min_gnt = pci_read_config8(dev, PCI_MIN_GNT); dev->max_lat = pci_read_config8(dev, PCI_MAX_LAT); +#warning Per-device subsystem ID should only be read from the device if none has been specified for the device in the dts. dev->subsystem_vendor = pci_read_config16(dev, PCI_SUBSYSTEM_VENDOR_ID); dev->subsystem_device = pci_read_config16(dev, PCI_SUBSYSTEM_ID);

1 0

[PATCH] v3: introduce generic global variable storage
by Carl-Daniel Hailfinger 14 Aug '08

14 Aug '08

Introduce a generic global variable storage mechanism and switch the printk buffer management to it. Build tested and boot tested and result tested on Qemu. Please note the following pitfalls: - Adding a new global variable is not as easy as it looks. - Don't try to add one without consulting me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-global_vars/include/console.h =================================================================== --- corebootv3-global_vars/include/console.h (Revision 730) +++ corebootv3-global_vars/include/console.h (Arbeitskopie) @@ -60,6 +60,12 @@ }; #endif +struct global_vars { +#ifdef CONFIG_CONSOLE_BUFFER + struct printk_buffer *printk_buffer; +#endif +}; + SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))), int msg_level, const char *fmt, ...); SHARED(banner, void, int msg_level, const char *msg); Index: corebootv3-global_vars/include/arch/x86/cpu.h =================================================================== --- corebootv3-global_vars/include/arch/x86/cpu.h (Revision 730) +++ corebootv3-global_vars/include/arch/x86/cpu.h (Arbeitskopie) @@ -198,6 +198,7 @@ } SHARED(bottom_of_stack, void *, void); +SHARED(global_vars, struct global_vars *, void); #ifdef CONFIG_CONSOLE_BUFFER #define PRINTK_BUF_SIZE_CAR (CONFIG_CARSIZE / 2) Index: corebootv3-global_vars/lib/console.c =================================================================== --- corebootv3-global_vars/lib/console.c (Revision 730) +++ corebootv3-global_vars/lib/console.c (Arbeitskopie) @@ -35,13 +35,16 @@ } #ifdef CONFIG_CONSOLE_BUFFER +struct printk_buffer *printk_buffer_addr(void) +{ + return global_vars()->printk_buffer; +} + void printk_buffer_move(void *newaddr, int newsize) { - struct printk_buffer **p; struct printk_buffer *oldbuf, *newbuf; int copylen; - p = bottom_of_stack(); - oldbuf = *p; + oldbuf = printk_buffer_addr(); newbuf = newaddr; newbuf->len = newsize; newbuf->readoffset = 0; @@ -68,17 +71,10 @@ &oldbuf->buffer[0], copylen); newbuf->writeoffset += copylen; } - *p = newbuf; + global_vars()->printk_buffer = newbuf; return; } -struct printk_buffer *printk_buffer_addr(void) -{ - struct printk_buffer **p; - p = bottom_of_stack(); - return *p; -} - void printk_buffer_init(void) { struct printk_buffer *buf = printk_buffer_addr(); Index: corebootv3-global_vars/arch/x86/stage1.c =================================================================== --- corebootv3-global_vars/arch/x86/stage1.c (Revision 730) +++ corebootv3-global_vars/arch/x86/stage1.c (Arbeitskopie) @@ -70,12 +70,21 @@ } +/* + * The name is slightly misleading because this is the initial stack pointer, + * not the address of the first element on the stack. + */ void *bottom_of_stack(void) { - /* -4-4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ - return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4 - 4); + /* -4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ + return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4); } +struct global_vars *global_vars(void) +{ + return (struct global_vars *)(bottom_of_stack() - sizeof(struct global_vars)); +} + void dump_mem_range(int msg_level, unsigned char *buf, int size) { int i; -- http://www.hailfinger.org/ Index: corebootv3-global_vars/include/console.h =================================================================== --- corebootv3-global_vars/include/console.h (Revision 730) +++ corebootv3-global_vars/include/console.h (Arbeitskopie) @@ -60,6 +60,12 @@ }; #endif +struct global_vars { +#ifdef CONFIG_CONSOLE_BUFFER + struct printk_buffer *printk_buffer; +#endif +}; + SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))), int msg_level, const char *fmt, ...); SHARED(banner, void, int msg_level, const char *msg); Index: corebootv3-global_vars/include/arch/x86/cpu.h =================================================================== --- corebootv3-global_vars/include/arch/x86/cpu.h (Revision 730) +++ corebootv3-global_vars/include/arch/x86/cpu.h (Arbeitskopie) @@ -198,6 +198,7 @@ } SHARED(bottom_of_stack, void *, void); +SHARED(global_vars, struct global_vars *, void); #ifdef CONFIG_CONSOLE_BUFFER #define PRINTK_BUF_SIZE_CAR (CONFIG_CARSIZE / 2) Index: corebootv3-global_vars/lib/console.c =================================================================== --- corebootv3-global_vars/lib/console.c (Revision 730) +++ corebootv3-global_vars/lib/console.c (Arbeitskopie) @@ -35,13 +35,16 @@ } #ifdef CONFIG_CONSOLE_BUFFER +struct printk_buffer *printk_buffer_addr(void) +{ + return global_vars()->printk_buffer; +} + void printk_buffer_move(void *newaddr, int newsize) { - struct printk_buffer **p; struct printk_buffer *oldbuf, *newbuf; int copylen; - p = bottom_of_stack(); - oldbuf = *p; + oldbuf = printk_buffer_addr(); newbuf = newaddr; newbuf->len = newsize; newbuf->readoffset = 0; @@ -68,17 +71,10 @@ &oldbuf->buffer[0], copylen); newbuf->writeoffset += copylen; } - *p = newbuf; + global_vars()->printk_buffer = newbuf; return; } -struct printk_buffer *printk_buffer_addr(void) -{ - struct printk_buffer **p; - p = bottom_of_stack(); - return *p; -} - void printk_buffer_init(void) { struct printk_buffer *buf = printk_buffer_addr(); Index: corebootv3-global_vars/arch/x86/stage1.c =================================================================== --- corebootv3-global_vars/arch/x86/stage1.c (Revision 730) +++ corebootv3-global_vars/arch/x86/stage1.c (Arbeitskopie) @@ -70,12 +70,21 @@ } +/* + * The name is slightly misleading because this is the initial stack pointer, + * not the address of the first element on the stack. + */ void *bottom_of_stack(void) { - /* -4-4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ - return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4 - 4); + /* -4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ + return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4); } +struct global_vars *global_vars(void) +{ + return (struct global_vars *)(bottom_of_stack() - sizeof(struct global_vars)); +} + void dump_mem_range(int msg_level, unsigned char *buf, int size) { int i;

4 9

r760 - in coreboot-v3: arch/x86 include include/arch/x86 lib
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: hailfinger Date: 2008-08-14 11:25:58 +0200 (Thu, 14 Aug 2008) New Revision: 760 Modified: coreboot-v3/arch/x86/stage1.c coreboot-v3/include/arch/x86/cpu.h coreboot-v3/include/console.h coreboot-v3/lib/console.c Log: Introduce a generic global variable storage mechanism and switch the printk buffer management to it. Build tested and boot tested and result tested on Qemu. Adding a new global variable is not as easy as it looks, but the comments in the code should be good enough to tell you how. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/stage1.c =================================================================== --- coreboot-v3/arch/x86/stage1.c 2008-08-14 01:40:31 UTC (rev 759) +++ coreboot-v3/arch/x86/stage1.c 2008-08-14 09:25:58 UTC (rev 760) @@ -70,12 +70,21 @@ } +/* + * The name is slightly misleading because this is the initial stack pointer, + * not the address of the first element on the stack. + */ void *bottom_of_stack(void) { - /* -4-4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ - return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4 - 4); + /* -4 because CONFIG_CARBASE + CONFIG_CARSIZE - 4 is initial %esp */ + return (void *)(CONFIG_CARBASE + CONFIG_CARSIZE - 4); } +struct global_vars *global_vars(void) +{ + return (struct global_vars *)(bottom_of_stack() - sizeof(struct global_vars)); +} + void dump_mem_range(int msg_level, unsigned char *buf, int size) { int i; Modified: coreboot-v3/include/arch/x86/cpu.h =================================================================== --- coreboot-v3/include/arch/x86/cpu.h 2008-08-14 01:40:31 UTC (rev 759) +++ coreboot-v3/include/arch/x86/cpu.h 2008-08-14 09:25:58 UTC (rev 760) @@ -202,6 +202,7 @@ } SHARED(bottom_of_stack, void *, void); +SHARED(global_vars, struct global_vars *, void); #ifdef CONFIG_CONSOLE_BUFFER #define PRINTK_BUF_SIZE_CAR (CONFIG_CARSIZE / 2) Modified: coreboot-v3/include/console.h =================================================================== --- coreboot-v3/include/console.h 2008-08-14 01:40:31 UTC (rev 759) +++ coreboot-v3/include/console.h 2008-08-14 09:25:58 UTC (rev 760) @@ -59,6 +59,18 @@ }; #endif +/* + * If you change struct global_vars in any way, you have to fix all stage0 asm + * code. The stage0 asm code modification is nontrivial (size of the struct, + * alignment, initialization, order of struct members, initialization). + * Depending on your compiler, real breakage may happen. + */ +struct global_vars { +#ifdef CONFIG_CONSOLE_BUFFER + struct printk_buffer *printk_buffer; +#endif +}; + SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))), int msg_level, const char *fmt, ...); SHARED(banner, void, int msg_level, const char *msg); Modified: coreboot-v3/lib/console.c =================================================================== --- coreboot-v3/lib/console.c 2008-08-14 01:40:31 UTC (rev 759) +++ coreboot-v3/lib/console.c 2008-08-14 09:25:58 UTC (rev 760) @@ -35,13 +35,16 @@ } #ifdef CONFIG_CONSOLE_BUFFER +struct printk_buffer *printk_buffer_addr(void) +{ + return global_vars()->printk_buffer; +} + void printk_buffer_move(void *newaddr, int newsize) { - struct printk_buffer **p; struct printk_buffer *oldbuf, *newbuf; int copylen; - p = bottom_of_stack(); - oldbuf = *p; + oldbuf = printk_buffer_addr(); newbuf = newaddr; newbuf->len = newsize; newbuf->readoffset = 0; @@ -68,17 +71,10 @@ &oldbuf->buffer[0], copylen); newbuf->writeoffset += copylen; } - *p = newbuf; + global_vars()->printk_buffer = newbuf; return; } -struct printk_buffer *printk_buffer_addr(void) -{ - struct printk_buffer **p; - p = bottom_of_stack(); - return *p; -} - void printk_buffer_init(void) { struct printk_buffer *buf = printk_buffer_addr();

1 0

v3: ROMCC artifact TODO
by Carl-Daniel Hailfinger 14 Aug '08

14 Aug '08

Hi, attached is a list of occurences where we use the plain "unsigned" type which was once the preferred type for ROMCC compiled code. For v3, an adjustment to the real desired sizes of these types would be beneficial. Be warned that this can't be automated. Regards, Carl-Daniel -- http://www.hailfinger.org/ ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c: unsigned device; ./southbridge/nvidia/mcp55/smbus.c:unsigned pm_base; ./southbridge/nvidia/mcp55/lpc.c: unsigned link; ./southbridge/nvidia/mcp55/lpc.c:static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) ./southbridge/nvidia/mcp55/stage1_usbdebug.c:static void set_debug_port(unsigned port) ./southbridge/nvidia/mcp55/stage1_usbdebug.c:static void mcp55_enable_usbdebug_direct(unsigned port) ./southbridge/nvidia/mcp55/usb2.c: unsigned base; ./southbridge/nvidia/mcp55/usb2.c: unsigned old_debug; ./southbridge/nvidia/mcp55/mcp55.c:static struct device *find_lpc_dev( struct device *dev, unsigned devfn) ./southbridge/nvidia/mcp55/mcp55.c: unsigned index = 0; ./southbridge/nvidia/mcp55/mcp55.c: unsigned index2 = 0; ./southbridge/nvidia/mcp55/mcp55.c: unsigned deviceid; ./southbridge/nvidia/mcp55/mcp55.c: unsigned vendorid; ./southbridge/nvidia/mcp55/mcp55.c: unsigned devfn; ./southbridge/nvidia/mcp55/stage1.c: int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); ./southbridge/nvidia/mcp55/stage1.c: unsigned vendorid = 0x10de; ./southbridge/nvidia/mcp55/stage1.c: unsigned val = 0x01610109; ./southbridge/nvidia/mcp55/stage1.c:void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) ./southbridge/nvidia/mcp55/stage1.c: unsigned val; ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) ./southbridge/nvidia/mcp55/stage1.c:static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) ./southbridge/nvidia/mcp55/stage1.c: unsigned busn[HT_CHAIN_NUM_MAX]; ./southbridge/nvidia/mcp55/stage1.c: unsigned devn[HT_CHAIN_NUM_MAX]; ./southbridge/nvidia/mcp55/stage1.c: unsigned io_base[HT_CHAIN_NUM_MAX]; ./southbridge/nvidia/mcp55/stage1.c: unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 }; ./southbridge/nvidia/mcp55/stage1.c: unsigned busnx; ./southbridge/nvidia/mcp55/stage1.c: unsigned devnx; ./southbridge/nvidia/mcp55/stage1.c:void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) ./northbridge/amd/geodelx/vsmsetup.c: unsigned eax, ebx, ecx, edx; ./northbridge/amd/geodelx/vsmsetup.c: unsigned eax, ebx, ecx, edx; ./northbridge/amd/k8/northbridge.c:static u32 f1_read_config32(unsigned reg) ./northbridge/amd/k8/northbridge.c:static void f1_write_config32(unsigned reg, u32 value) ./northbridge/amd/k8/northbridge.c:static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) ./northbridge/amd/k8/northbridge.c: unsigned free_reg, config_reg; ./northbridge/amd/k8/northbridge.c: unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain ./northbridge/amd/k8/northbridge.c: unsigned max_bus; ./northbridge/amd/k8/northbridge.c: unsigned min_bus; ./northbridge/amd/k8/northbridge.c: unsigned max_devfn; ./northbridge/amd/k8/northbridge.c: unsigned temp = 0; ./northbridge/amd/k8/northbridge.c: unsigned nodeid; ./northbridge/amd/k8/northbridge.c: unsigned link; ./northbridge/amd/k8/northbridge.c: unsigned sblink = 0; ./northbridge/amd/k8/northbridge.c: unsigned offset_unitid = 0; ./northbridge/amd/k8/northbridge.c:static int reg_useable(unsigned reg, ./northbridge/amd/k8/northbridge.c: struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c:static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) ./northbridge/amd/k8/northbridge.c: unsigned free_reg, reg; ./northbridge/amd/k8/northbridge.c:static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) ./northbridge/amd/k8/northbridge.c: unsigned free_reg, reg; ./northbridge/amd/k8/northbridge.c:static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c:static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) ./northbridge/amd/k8/northbridge.c: unsigned reg, link; ./northbridge/amd/k8/northbridge.c:static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) ./northbridge/amd/k8/northbridge.c: unsigned link; ./northbridge/amd/k8/northbridge.c: unsigned reg; ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c: unsigned reg; ./northbridge/amd/k8/northbridge.c: unsigned nodeid, link; ./northbridge/amd/k8/northbridge.c: unsigned hole_startk; ./northbridge/amd/k8/northbridge.c: unsigned base_k, limit_k; ./northbridge/amd/k8/northbridge.c: unsigned reset_memhole = 1; ./northbridge/amd/k8/northbridge.c: unsigned basek, limitk, sizek; ./northbridge/amd/k8/northbridge.c: unsigned pre_sizek; ./northbridge/amd/k8/northbridge.c: unsigned reg; ./northbridge/amd/k8/northbridge.c: unsigned nb_cfg_54; ./northbridge/amd/k8/northbridge.c: unsigned siblings; ./northbridge/amd/k8/northbridge.c: unsigned jj; ./northbridge/amd/k8/incoherent_ht.c:static void ht_collapse_previous_enumeration(u8 bus, unsigned offset_unitid) ./northbridge/amd/k8/incoherent_ht.c: u32 bdf1, u8 pos1, unsigned offs1, ./northbridge/amd/k8/incoherent_ht.c: u32 bdf2, u8 pos2, unsigned offs2) ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid, struct sys_info *sysinfo); ./northbridge/amd/k8/incoherent_ht.c:int scan_pci_bus( unsigned bus , struct sys_info *sysinfo) ./northbridge/amd/k8/incoherent_ht.c: unsigned new_bus; ./northbridge/amd/k8/incoherent_ht.c: unsigned max_bus; ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid, struct sys_info *sysinfo) ./northbridge/amd/k8/incoherent_ht.c: unsigned uoffs; ./northbridge/amd/k8/incoherent_ht.c: unsigned real_last_unitid; ./northbridge/amd/k8/incoherent_ht.c: unsigned offs; ./northbridge/amd/k8/incoherent_ht.c:void ht_setup_chain(u32 bdf, unsigned upos, struct sys_info *sysinfo) ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid = 0; ./northbridge/amd/k8/incoherent_ht.c: unsigned devn = 1; ./northbridge/amd/k8/incoherent_ht.c:int set_ht_link_buffer_count(u8 node, u8 linkn, u8 linkt, unsigned val) ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c:int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val) ./northbridge/amd/k8/incoherent_ht.c: unsigned devn; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned bus; ./northbridge/amd/k8/incoherent_ht.c: unsigned offset_unitid = 0; ./northbridge/amd/k8/incoherent_ht.c:unsigned get_nodes(void); ./northbridge/amd/k8/incoherent_ht.c: unsigned next_io_base; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned regpos; ./northbridge/amd/k8/incoherent_ht.c: unsigned link_pair_num = sysinfo->link_pair_num; ./northbridge/amd/k8/coherent_ht.c: unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp2(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp4(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp6(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp8(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned setup_smp(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c:unsigned verify_mp_capabilities(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node, mask; ./northbridge/amd/k8/coherent_ht.c:void clear_dead_routes(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c:unsigned verify_dualcore(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node, totalcpus, tmp; ./northbridge/amd/k8/coherent_ht.c:void coherent_ht_finalize(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node; ./northbridge/amd/k8/coherent_ht.c: unsigned total_cpus; ./northbridge/amd/k8/coherent_ht.c:int apply_cpu_errata_fixes(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node; ./northbridge/amd/k8/coherent_ht.c:int optimize_link_read_pointers(unsigned nodes) ./northbridge/amd/k8/coherent_ht.c: unsigned node; ./northbridge/amd/k8/coherent_ht.c: unsigned reg; ./northbridge/amd/k8/coherent_ht.c:inline unsigned get_nodes(void) ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/coherent_ht.c: unsigned nodes; ./northbridge/amd/k8/get_sblk_pci1234.c:unsigned node_link_to_bus(unsigned node, unsigned link) ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned reg; ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned dst_node; ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned dst_link; ./northbridge/amd/k8/get_sblk_pci1234.c: unsigned bus_base; ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/get_sblk_pci1234.c: * unsigned pci1234[] = { ./northbridge/amd/k8/raminit.c:static struct dimm_size spd_get_dimm_size(unsigned device) ./northbridge/amd/k8/raminit.c:static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) ./northbridge/amd/k8/raminit.c:static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz, unsigned index) ./northbridge/amd/k8/raminit.c: static const unsigned cs_map_aa[] = { ./northbridge/amd/k8/raminit.c: unsigned node_id; ./northbridge/amd/k8/raminit.c: unsigned limit; ./northbridge/amd/k8/raminit.c: unsigned base; ./northbridge/amd/k8/raminit.c: unsigned index; ./northbridge/amd/k8/raminit.c: unsigned limit_reg, base_reg; ./northbridge/amd/k8/raminit.c:static void set_top_mem(unsigned tom_k, unsigned hole_startk) ./northbridge/amd/k8/raminit.c: unsigned common_size; ./northbridge/amd/k8/raminit.c: unsigned common_cs_mode; ./northbridge/amd/k8/raminit.c: unsigned size; ./northbridge/amd/k8/raminit.c: unsigned cs_mode; ./northbridge/amd/k8/raminit.c: unsigned index, candidate; ./northbridge/amd/k8/raminit.c: unsigned size; ./northbridge/amd/k8/raminit.c: unsigned node_id; ./northbridge/amd/k8/raminit.c: unsigned end_k; ./northbridge/amd/k8/raminit.c: unsigned index; ./northbridge/amd/k8/raminit.c:static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) ./northbridge/amd/k8/raminit.c: unsigned dimm_mask; ./northbridge/amd/k8/raminit.c: unsigned device; ./northbridge/amd/k8/raminit.c: unsigned device0, device1; ./northbridge/amd/k8/raminit.c: unsigned addr; ./northbridge/amd/k8/raminit.c:static const struct mem_param *get_mem_param(unsigned min_cycle_time) ./northbridge/amd/k8/raminit.c: unsigned min_cycle_time, min_latency, bios_cycle_time; ./northbridge/amd/k8/raminit.c: static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 }; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks, old_clocks; ./northbridge/amd/k8/raminit.c: unsigned tref, old_tref; ./northbridge/amd/k8/raminit.c: unsigned index; ./northbridge/amd/k8/raminit.c: unsigned latency; ./northbridge/amd/k8/raminit.c: unsigned clocks; ./northbridge/amd/k8/raminit.c: unsigned clocks; ./northbridge/amd/k8/raminit.c: unsigned rdpreamble; ./northbridge/amd/k8/raminit.c: unsigned async_lat; ./northbridge/amd/k8/raminit.c:static u32 hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) ./northbridge/amd/k8/raminit.c: unsigned base_k; ./northbridge/amd/k8/raminit.c: unsigned base_k, limit_k; ./northbridge/amd/k8/raminit.c: unsigned end_k; ./northbridge/amd/k8/raminit.c:void set_sysinfo_in_ram(unsigned val) ./superio/winbond/w83627hf/superio.c: unsigned hwm_reg_values[] = { ./device/hypertransport.c:static unsigned ht_read_freq_cap(struct device *dev, unsigned pos) ./device/hypertransport.c: unsigned freq_cap; ./device/pci_device.c: unsigned ctl; ./device/pci_device.c: unsigned short intBits = inb(0x4d0) | (((unsigned)inb(0x4d1)) << 8); ./include/uart8250.h:unsigned char uart8250_rx_byte(unsigned base_port); ./include/uart8250.h:int uart8250_can_rx_byte(unsigned base_port); ./include/uart8250.h:void uart8250_tx_byte(unsigned base_port, unsigned char data); ./include/uart8250.h:void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); ./include/device/agp.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/hypertransport.h: unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); ./include/device/device.h: unsigned bridge_ctrl; /* Bridge control register */ ./include/device/device.h: unsigned reset_needed : 1; ./include/device/device.h: unsigned disable_relaxed_ordering : 1; ./include/device/pcix.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/pcix.h:const char *pcix_speed(unsigned sstatus); ./include/device/path.h: unsigned domain; ./include/device/path.h: unsigned bus; ./include/device/path.h: unsigned devfn; ./include/device/path.h: unsigned port; ./include/device/path.h: unsigned device; ./include/device/path.h: unsigned device; ./include/device/path.h: unsigned apic_id; ./include/device/path.h: unsigned node_id; ./include/device/path.h: unsigned core_id; ./include/device/path.h: unsigned cluster; ./include/device/path.h: unsigned id; ./include/device/path.h: unsigned id; ./include/device/path.h: unsigned iobase; ./include/device/pci_ops.h:u8 pci_read_config8(struct device * dev, unsigned where); ./include/device/pci_ops.h:u16 pci_read_config16(struct device * dev, unsigned where); ./include/device/pci_ops.h:u32 pci_read_config32(struct device * dev, unsigned where); ./include/device/pci_ops.h:void pci_write_config8(struct device * dev, unsigned where, u8 val); ./include/device/pci_ops.h:void pci_write_config16(struct device * dev, unsigned where, u16 val); ./include/device/pci_ops.h:void pci_write_config32(struct device * dev, unsigned where, u32 val); ./include/device/pci.h: void (*set_subsystem)(struct device * dev, unsigned vendor, unsigned device); ./include/device/pci.h:struct device * pci_probe_dev(struct device * dev, struct bus *bus, unsigned devfn); ./include/device/pci.h: unsigned min_devfn, unsigned max_devfn, unsigned int max)); ./include/device/pci.h:unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/pci.h:u8 pci_moving_config8(struct device *dev, unsigned reg); ./include/device/pci.h:u16 pci_moving_config16(struct device *dev, unsigned reg); ./include/device/pci.h:u32 pci_moving_config32(struct device *dev, unsigned reg); ./include/device/pci.h:unsigned pci_find_next_capability(struct device * dev, unsigned cap, unsigned last); ./include/device/pci.h:unsigned pci_find_capability(struct device * dev, unsigned cap); ./include/device/pci.h:void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned device); ./include/device/pnp.h:void pnp_set_iobase(struct device * dev, unsigned index, unsigned iobase); ./include/device/pnp.h:void pnp_set_irq(struct device * dev, unsigned index, unsigned irq); ./include/device/pnp.h:void pnp_set_drq(struct device * dev, unsigned index, unsigned drq); ./include/device/pnp.h: unsigned mask, set; ./include/device/pnp.h: unsigned function; ./include/device/pnp.h: unsigned flags; ./include/device/pnp.h:struct resource *pnp_get_resource(struct device * dev, unsigned index); ./include/device/pnp.h: unsigned functions, struct pnp_info *info); ./include/device/resource.h:extern struct resource *probe_resource(struct device *dev, unsigned index); ./include/device/resource.h:extern struct resource *new_resource(struct device * dev, unsigned index); ./include/device/resource.h:extern struct resource *find_resource(struct device * dev, unsigned index); ./include/device/pcie.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/device/cardbus.h: unsigned min_devfn, unsigned max_devfn, unsigned int max); ./include/arch/x86/amd/k8/raminit.h: unsigned node_id; ./include/arch/x86/amd/k8/sysconf.h: unsigned nodes; ./include/arch/x86/amd/k8/sysconf.h: unsigned hc_possible_num; ./include/arch/x86/amd/k8/sysconf.h: unsigned pci1234[HC_POSSIBLE_NUM]; ./include/arch/x86/amd/k8/sysconf.h: unsigned hcdn[HC_POSSIBLE_NUM]; ./include/arch/x86/amd/k8/sysconf.h: unsigned hcid[HC_POSSIBLE_NUM]; //record ht chain type ./include/arch/x86/amd/k8/sysconf.h: unsigned sbdn; ./include/arch/x86/amd/k8/sysconf.h: unsigned sblk; ./include/arch/x86/amd/k8/sysconf.h: unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234 ./include/arch/x86/amd/k8/sysconf.h: unsigned lift_bsp_apicid; ./include/arch/x86/amd/k8/k8.h: unsigned node_id; ./include/arch/x86/amd/k8/k8.h: unsigned nodeid; ./include/arch/x86/amd/k8/k8.h: unsigned coreid; ./include/arch/x86/amd/k8/k8.h:unsigned get_apicid_base(unsigned ioapic_num); ./include/arch/x86/mtrr.h:void x86_setup_var_mtrrs(unsigned address_bits); ./include/arch/x86/mtrr.h:void x86_setup_mtrrs(unsigned address_bits); ./lib/nrv2b.c: (((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1) ./lib/nrv2b.c: unsigned bc = 0; ./lib/uart8250.c:static inline int uart8250_can_tx_byte(unsigned base_port) ./lib/uart8250.c:static inline void uart8250_wait_to_tx_byte(unsigned base_port) ./lib/uart8250.c:static inline void uart8250_wait_until_sent(unsigned base_port) ./lib/uart8250.c:void uart8250_tx_byte(unsigned base_port, unsigned char data) ./lib/uart8250.c:int uart8250_can_rx_byte(unsigned base_port) ./lib/uart8250.c:unsigned char uart8250_rx_byte(unsigned base_port) ./lib/uart8250.c:void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs) ./doc/design/newboot.lyx: The simplest function is called smbus_read_byte(unsigned device, unsigned ./arch/x86/resourcemap.c: unsigned where; ./arch/x86/serial.c: unsigned ttysx_div; ./arch/x86/serial.c: unsigned ttysx_index; ./arch/x86/archtables.c: unsigned mptable_size = new_low_table_end - low_table_end - SMP_FLOATING_TABLE_LEN; ./arch/x86/mc146818rtc.c: unsigned sum, old_sum; ./arch/x86/mc146818rtc.c: unsigned sum; ./arch/x86/mc146818rtc.c:unsigned read_option(unsigned start, unsigned size, unsigned def) ./arch/x86/mc146818rtc.c: unsigned byte; ./arch/x86/pci_ops_auto.c: unsigned bus;

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coreboot August 2008