coreboot August 2008

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593 discussions

r3509 - in trunk/coreboot-v2/src: cpu/emulation/qemu-x86 pc80
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: stepan Date: 2008-08-13 14:16:15 +0200 (Wed, 13 Aug 2008) New Revision: 3509 Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c trunk/coreboot-v2/src/pc80/udelay_io.c Log: Fix outb to 0x80 delay functions to use inb instead (fixes excessive post codes in a couple of occurences) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c =================================================================== --- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2008-08-13 09:38:12 UTC (rev 3508) +++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c 2008-08-13 12:16:15 UTC (rev 3509) @@ -147,7 +147,7 @@ { int i; for(i = 0; i < usecs; i++) - outb(i&0xff, 0x80); + inb(0x80); } Modified: trunk/coreboot-v2/src/pc80/udelay_io.c =================================================================== --- trunk/coreboot-v2/src/pc80/udelay_io.c 2008-08-13 09:38:12 UTC (rev 3508) +++ trunk/coreboot-v2/src/pc80/udelay_io.c 2008-08-13 12:16:15 UTC (rev 3509) @@ -4,6 +4,6 @@ { int i; for(i = 0; i < usecs; i++) - outb(i&0xff, 0x80); + inb(0x80); }

1 0

r3508 - trunk/payloads/coreinfo
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: stepan Date: 2008-08-13 11:38:12 +0200 (Wed, 13 Aug 2008) New Revision: 3508 Modified: trunk/payloads/coreinfo/pci_module.c Log: off by 1. (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/coreinfo/pci_module.c =================================================================== --- trunk/payloads/coreinfo/pci_module.c 2008-08-13 08:23:06 UTC (rev 3507) +++ trunk/payloads/coreinfo/pci_module.c 2008-08-13 09:38:12 UTC (rev 3508) @@ -178,7 +178,7 @@ unsigned int val; unsigned char hdr; - for (slot = 0; slot < 0x1f; slot++) { + for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { pcidev_t dev = PCI_DEV(bus, slot, func);

1 0

r3507 - trunk/payloads/coreinfo
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: stepan Date: 2008-08-13 10:23:06 +0200 (Wed, 13 Aug 2008) New Revision: 3507 Modified: trunk/payloads/coreinfo/pci_module.c Log: commit real fix to pci module of coreinfo (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/coreinfo/pci_module.c =================================================================== --- trunk/payloads/coreinfo/pci_module.c 2008-08-13 08:21:27 UTC (rev 3506) +++ trunk/payloads/coreinfo/pci_module.c 2008-08-13 08:23:06 UTC (rev 3507) @@ -18,13 +18,14 @@ */ #include <arch/io.h> +#include <pci.h> #include <libpayload.h> #include "coreinfo.h" #ifdef CONFIG_MODULE_PCI struct pci_devices { - unsigned short device; + pcidev_t device; unsigned int id; }; @@ -86,18 +87,16 @@ static void show_config_space(WINDOW *win, int row, int col, int index) { - unsigned char cspace[64]; - int bus, devfn; + unsigned char cspace[256]; + pcidev_t dev; int i, x, y; - bus = (devices[index].device >> 8) & 0xff; - devfn = devices[index].device & 0xff; + dev = devices[index].device; - for (i = 0; i < 64; i += 4) - cspace[i] = pci_read_config32(PCI_DEV(bus, PCI_SLOT(devfn), - PCI_FUNC(devfn)), i); + for (i = 0; i < 256; i ++) + cspace[i] = pci_read_config8(dev, i); - for (y = 0; y < 4; y++) { + for (y = 0; y < 16; y++) { for (x = 0; x < 16; x++) mvwprintw(win, row + y, col + (x * 3), "%2.2X ", cspace[(y * 16) + x]); @@ -106,7 +105,7 @@ static int pci_module_redraw(WINDOW *win) { - unsigned int bus, devfn, func; + unsigned int bus, slot, func; int i, last; print_module_title(win, "PCI Device List"); @@ -126,9 +125,9 @@ continue; } - bus = (devices[item].device >> 8) & 0xff; - devfn = (devices[item].device & 0xff) / 8; - func = (devices[item].device & 0xff) % 8; + bus = PCI_BUS(devices[item].device); + slot = PCI_SLOT(devices[item].device); + func = PCI_FUNC(devices[item].device); if (item == menu_selected) wattrset(win, COLOR_PAIR(3) | A_BOLD); @@ -136,7 +135,7 @@ wattrset(win, COLOR_PAIR(2)); mvwprintw(win, 2 + i, 1, "%X:%2.2X.%2.2X %04X:%04X ", - bus, devfn, func, + bus, slot, func, devices[item].id & 0xffff, (devices[item].id >> 16) & 0xffff); @@ -162,7 +161,7 @@ for (i = 0; i < 48; i++) waddch(win, (i == 0) ? ACS_ULCORNER : ACS_HLINE); - for (i = 0; i < 4; i++) { + for (i = 0; i < 16; i++) { mvwprintw(win, 4 + i, 23, "%2.2X", i * 16); wmove(win, 4 + i, 25); waddch(win, ACS_VLINE); @@ -175,14 +174,13 @@ static void pci_scan_bus(int bus) { - int devfn, func; + int slot, func; unsigned int val; unsigned char hdr; - for (devfn = 0; devfn < 0x100;) { - for (func = 0; func < 8; func++, devfn++) { - pcidev_t dev = PCI_DEV(bus, PCI_SLOT(devfn), - PCI_FUNC(devfn)); + for (slot = 0; slot < 0x1f; slot++) { + for (func = 0; func < 8; func++) { + pcidev_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, REG_VENDOR_ID); @@ -195,8 +193,8 @@ if (devices_index >= 64) return; - devices[devices_index].device = - ((bus & 0xff) << 8) | (devfn & 0xff); + devices[devices_index].device = + PCI_DEV(bus, slot, func); devices[devices_index++].id = val;

1 0

r3506 - trunk/payloads/libpayload/include
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: stepan Date: 2008-08-13 10:21:27 +0200 (Wed, 13 Aug 2008) New Revision: 3506 Modified: trunk/payloads/libpayload/include/pci.h Log: add PCI_BUS macro (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/libpayload/include/pci.h =================================================================== --- trunk/payloads/libpayload/include/pci.h 2008-08-12 20:23:00 UTC (rev 3505) +++ trunk/payloads/libpayload/include/pci.h 2008-08-13 08:21:27 UTC (rev 3506) @@ -49,6 +49,7 @@ #define PCI_DEV(_bus, _dev, _fn) \ (0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8)) +#define PCI_BUS(_d) ((_d >> 16) & 0xff) #define PCI_SLOT(_d) ((_d >> 11) & 0x1f) #define PCI_FUNC(_d) ((_d >> 8) & 0x7)

1 0

r755 - coreboot-v3/util/options
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: rminnich Date: 2008-08-13 05:07:21 +0200 (Wed, 13 Aug 2008) New Revision: 755 Modified: coreboot-v3/util/options/build_opt_tbl.c Log: Emergency commit as I have broken this tool. Basically, anything that includes files from include/ should define STANDALONE, so that the includes don't try to created SHARED symbols. This was not a problem until we made get_option SHARED. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/util/options/build_opt_tbl.c =================================================================== --- coreboot-v3/util/options/build_opt_tbl.c 2008-08-13 02:49:03 UTC (rev 754) +++ coreboot-v3/util/options/build_opt_tbl.c 2008-08-13 03:07:21 UTC (rev 755) @@ -10,6 +10,7 @@ #define u16 uint16_t #define u8 uint8_t +#define STANDALONE #include <mc146818rtc.h> #include <tables.h>

1 0

trivial patches to m57sli
by ron minnich 13 Aug '08

13 Aug '08

yea, it's ugly, but I want to get it in. It's a work in progress. ron

2 2

r754 - in coreboot-v3/mainboard/gigabyte: . m57sli
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: rminnich Date: 2008-08-13 04:49:03 +0200 (Wed, 13 Aug 2008) New Revision: 754 Modified: coreboot-v3/mainboard/gigabyte/Kconfig coreboot-v3/mainboard/gigabyte/m57sli/Makefile coreboot-v3/mainboard/gigabyte/m57sli/dts coreboot-v3/mainboard/gigabyte/m57sli/initram.c coreboot-v3/mainboard/gigabyte/m57sli/stage1.c Log: yea, it's ugly, but I want to get it in. It's a work in progress. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com Acked-by: Marc Jones <marc.jones(a)amd.com> Modified: coreboot-v3/mainboard/gigabyte/Kconfig =================================================================== --- coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/Kconfig 2008-08-13 02:49:03 UTC (rev 754) @@ -31,6 +31,7 @@ select NORTHBRIDGE_AMD_K8 select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_ITE_IT8716F + select IOAPIC help Gigabyte M57SLI Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-13 02:49:03 UTC (rev 754) @@ -20,17 +20,19 @@ ## STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(obj)/mainboard/$(MAINBOARDDIR)/option_table.o \ $(obj)/southbridge/nvidia/mcp55/stage1_smbus.o \ - $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \ - $(obj)/northbridge/amd/k8/raminit.o \ $(obj)/northbridge/amd/k8/coherent_ht.o \ - $(obj)/northbridge/amd/k8/incoherent_ht.o + $(obj)/northbridge/amd/k8/incoherent_ht.o \ + $(obj)/lib/clog2.o -# I can't get this to work -- if you can fix it do so. The file above -# from "initram" on should be here. -INITRAM_SRC= +INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/k8/raminit.c \ + $(src)/arch/x86/pci_ops_conf1.c \ + $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ + $(src)/lib/clog2.c + STAGE2_MAINBOARD_SRC = $(obj)/coreboot.vpd: Modified: coreboot-v3/mainboard/gigabyte/m57sli/dts =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/dts 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/dts 2008-08-13 02:49:03 UTC (rev 754) @@ -17,6 +17,25 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/*00:00.0 RAM memory: nVidia Corporation MCP55 Memory Controller (rev a1) +00:01.0 ISA bridge: nVidia Corporation MCP55 LPC Bridge (rev a2) +00:01.1 SMBus: nVidia Corporation MCP55 SMBus (rev a2) +00:02.0 USB Controller: nVidia Corporation MCP55 USB Controller (rev a1) +00:02.1 USB Controller: nVidia Corporation MCP55 USB Controller (rev a2) +00:04.0 IDE interface: nVidia Corporation MCP55 IDE (rev a1) +00:05.0 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) +00:05.1 IDE interface: nVidia Corporation MCP55 SATA Controller (rev a2) +00:06.0 PCI bridge: nVidia Corporation MCP55 PCI bridge (rev a2) +00:06.1 Audio device: nVidia Corporation MCP55 High Definition Audio (rev a2) +00:08.0 Bridge: nVidia Corporation MCP55 Ethernet (rev a2) +00:0f.0 PCI bridge: nVidia Corporation MCP55 PCI Express bridge (rev a2) +00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map +00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller +00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +01:0a.0 FireWire (IEEE 1394): Texas Instruments TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) +02:00.0 VGA compatible controller: nVidia Corporation G72 [GeForce 7300 LE] (rev a1) +*/ /{ mainboard_vendor = "Gigabyte"; @@ -25,8 +44,16 @@ apic@0 { }; domain@0 { + pci@1,0{ + }; pci@18,0 { /config/("northbridge/amd/k8/pci"); + pci@0,0 { + /config/("southbridge/nvidia/mcp55/ide.dts"); + }; + pci@0,1 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + }; }; }; }; Modified: coreboot-v3/mainboard/gigabyte/m57sli/initram.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/initram.c 2008-08-13 02:49:03 UTC (rev 754) @@ -31,8 +31,28 @@ #include <io.h> #include <cpu.h> #include <amd/k8/k8.h> +#include <southbridge/nvidia/mcp55/mcp55_smbus.h> +#include <mc146818rtc.h> #include <spd.h> +# warning fix hard_reset +void hard_reset(void) +{ +} +void memreset_setup(void) +{ +} + +void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + + /** * main for initram for the Gigabyte m57sli. */ Modified: coreboot-v3/mainboard/gigabyte/m57sli/stage1.c =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-13 02:44:46 UTC (rev 753) +++ coreboot-v3/mainboard/gigabyte/m57sli/stage1.c 2008-08-13 02:49:03 UTC (rev 754) @@ -32,20 +32,7 @@ #include <io.h> #include <arch/x86/msr.h> -void memreset_setup(void) -{ -} -void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - - void hardware_stage1(void) { post_code(POST_START_OF_MAIN);

1 0

r753 - coreboot-v3/arch/x86
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: rminnich Date: 2008-08-13 04:44:46 +0200 (Wed, 13 Aug 2008) New Revision: 753 Modified: coreboot-v3/arch/x86/Kconfig coreboot-v3/arch/x86/Makefile coreboot-v3/arch/x86/resourcemap.c Log: The change to Kconfig is self-acked. Add a depend clause so that we don't see these things on Geode. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> The other changes are: Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-08-13 02:41:29 UTC (rev 752) +++ coreboot-v3/arch/x86/Kconfig 2008-08-13 02:44:46 UTC (rev 753) @@ -133,6 +133,7 @@ config IOAPIC boolean + depends ARCH_X86 default 0 help If you want to configure an IOAPIC, set this. @@ -209,5 +210,6 @@ config APIC_ID_OFFSET hex "APIC ID offset" default 0x10 + depends IO_APIC help This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting. Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-08-13 02:41:29 UTC (rev 752) +++ coreboot-v3/arch/x86/Makefile 2008-08-13 02:44:46 UTC (rev 753) @@ -183,7 +183,7 @@ compute_ip_checksum.c string.c STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c -STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c +STAGE2_ARCH_X86_SRC += pci_ops_auto.c STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c ifeq ($(CONFIG_PIRQ_TABLE),y) Modified: coreboot-v3/arch/x86/resourcemap.c =================================================================== --- coreboot-v3/arch/x86/resourcemap.c 2008-08-13 02:41:29 UTC (rev 752) +++ coreboot-v3/arch/x86/resourcemap.c 2008-08-13 02:44:46 UTC (rev 753) @@ -47,8 +47,6 @@ /* NOTE: By doing the config write in this manner we guarantee that this * will work in stage1 or stage2. */ -#define pci_read_config32(busdevfn, where) pci_cf8_conf1.read32(busdevfn, where) -#define pci_write_config32(busdevfn, where, what) pci_cf8_conf1.write32(busdevfn, where, what) void setup_resource_map_x_offset(const struct rmap *rm, u32 max, u32 offset_bdf, u32 offset_pciio, @@ -77,10 +75,10 @@ dev <<= 3; dev |= rm->pcm.fn; dev += offset_devfn; - reg = pci_read_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where); + reg = pci_conf1_read_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where); reg &= rm->pcm.and; reg |= rm->pcm.or + offset_pciio; - pci_write_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where, reg); + pci_conf1_write_config32(PCI_BDEVFN(rm->pcm.bus + offset_bus, dev), where, reg); } break; case TIO8:

1 0

r752 - in coreboot-v3: arch/x86 include/device
by svn＠coreboot.org 13 Aug '08

13 Aug '08

Author: rminnich Date: 2008-08-13 04:41:29 +0200 (Wed, 13 Aug 2008) New Revision: 752 Modified: coreboot-v3/arch/x86/pci_ops_auto.c coreboot-v3/arch/x86/pci_ops_conf1.c coreboot-v3/include/device/pci_ops.h Log: Here we start to see the good design of 3. In v2, there were pci ops in all stages, blighting everything with the same code, compiled different ways. In this change, we see that: - basic conf ops are compiled into stage0, where they are used. - they are called directly from initram - they are used to initialize the pci_cf8_conf1 structure in stage 2, but the call still goes to stage0! one copy of the code. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/pci_ops_auto.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_auto.c 2008-08-12 23:54:25 UTC (rev 751) +++ coreboot-v3/arch/x86/pci_ops_auto.c 2008-08-13 02:41:29 UTC (rev 752) @@ -7,6 +7,18 @@ #include <types.h> #include <io.h> + +const struct pci_bus_operations pci_cf8_conf1 = { + .read8 = pci_conf1_read_config8, + .read16 = pci_conf1_read_config16, + .read32 = pci_conf1_read_config32, + .write8 = pci_conf1_write_config8, + .write16 = pci_conf1_write_config16, + .write32 = pci_conf1_write_config32, + .find = pci_conf1_find_device, +}; + + /* * Before we decide to use direct hardware access mechanisms, we try to do some * trivial checks to ensure it at least _seems_ to be working -- we just test Modified: coreboot-v3/arch/x86/pci_ops_conf1.c =================================================================== --- coreboot-v3/arch/x86/pci_ops_conf1.c 2008-08-12 23:54:25 UTC (rev 751) +++ coreboot-v3/arch/x86/pci_ops_conf1.c 2008-08-13 02:41:29 UTC (rev 752) @@ -56,37 +56,37 @@ #define CONFIG_CMD(bdf, where) (0x80000000 | (bdf) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) ) #endif -static u8 pci_conf1_read_config8(u32 bdf, int where) +u8 pci_conf1_read_config8(u32 bdf, int where) { outl(CONFIG_CMD(bdf, where), 0xCF8); return inb(0xCFC + (where & 3)); } -static u16 pci_conf1_read_config16(u32 bdf, int where) +u16 pci_conf1_read_config16(u32 bdf, int where) { outl(CONFIG_CMD(bdf, where), 0xCF8); return inw(0xCFC + (where & 2)); } -static u32 pci_conf1_read_config32(u32 bdf, int where) +u32 pci_conf1_read_config32(u32 bdf, int where) { outl(CONFIG_CMD(bdf, where), 0xCF8); return inl(0xCFC); } -static void pci_conf1_write_config8(u32 bdf, int where, u8 value) +void pci_conf1_write_config8(u32 bdf, int where, u8 value) { outl(CONFIG_CMD(bdf, where), 0xCF8); outb(value, 0xCFC + (where & 3)); } -static void pci_conf1_write_config16(u32 bdf, int where, u16 value) +void pci_conf1_write_config16(u32 bdf, int where, u16 value) { outl(CONFIG_CMD(bdf, where), 0xCF8); outw(value, 0xCFC + (where & 2)); } -static void pci_conf1_write_config32(u32 bdf, int where, u32 value) +void pci_conf1_write_config32(u32 bdf, int where, u32 value) { outl(CONFIG_CMD(bdf, where), 0xCF8); outl(value, 0xCFC); @@ -111,7 +111,7 @@ * @return 1 if found, 0 otherwise */ -static int find_on_bus(u16 bus, u16 vid, u16 did, u32 *busdevfn) +int pci_conf1_find_on_bus(u16 bus, u16 vid, u16 did, u32 *busdevfn) { u16 devfn; @@ -139,7 +139,7 @@ if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) { unsigned int busses; busses = pci_conf1_read_config32(confaddr, PCI_PRIMARY_BUS); - if (find_on_bus((busses >> 8) & 0xFF, vid, did, busdevfn)) + if (pci_conf1_find_on_bus((busses >> 8) & 0xFF, vid, did, busdevfn)) return 1; } } @@ -147,17 +147,7 @@ return 0; } -static int pci_find_device(u16 vid, u16 did, u32 * dev) +int pci_conf1_find_device(u16 vid, u16 did, u32 * dev) { - return find_on_bus(0, vid, did, dev); + return pci_conf1_find_on_bus(0, vid, did, dev); } - -const struct pci_bus_operations pci_cf8_conf1 = { - .read8 = pci_conf1_read_config8, - .read16 = pci_conf1_read_config16, - .read32 = pci_conf1_read_config32, - .write8 = pci_conf1_write_config8, - .write16 = pci_conf1_write_config16, - .write32 = pci_conf1_write_config32, - .find = pci_find_device, -}; Modified: coreboot-v3/include/device/pci_ops.h =================================================================== --- coreboot-v3/include/device/pci_ops.h 2008-08-12 23:54:25 UTC (rev 751) +++ coreboot-v3/include/device/pci_ops.h 2008-08-13 02:41:29 UTC (rev 752) @@ -21,6 +21,7 @@ #include <types.h> #include <device/device.h> #include <pci_ops.h> +#include <shared.h> u8 pci_read_config8(struct device * dev, unsigned where); u16 pci_read_config16(struct device * dev, unsigned where); @@ -29,4 +30,13 @@ void pci_write_config16(struct device * dev, unsigned where, u16 val); void pci_write_config32(struct device * dev, unsigned where, u32 val); +SHARED(pci_conf1_read_config8, u8, u32 bdf, int where); +SHARED(pci_conf1_read_config16, u16, u32 bdf, int where); +SHARED(pci_conf1_read_config32, u32, u32 bdf, int where); +SHARED(pci_conf1_write_config8, void , u32 bdf, int where, u8 value); +SHARED(pci_conf1_write_config16, void, u32 bdf, int where, u16 value); +SHARED(pci_conf1_write_config32, void, u32 bdf, int where, u32 value); +SHARED(pci_conf1_find_on_bus, int, u16 bus, u16 vid, u16 did, u32 *busdevfn); +SHARED(pci_conf1_find_device, int, u16 vid, u16 did, u32 * dev); + #endif /* DEVICE_PCI_OPS_H */

1 0

patch: latest k8 north diff
by ron minnich 13 Aug '08

13 Aug '08

two new files and a few typo fixes. ron

4 7

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2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2008