coreboot August 2008

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r768 - coreboot-v3/southbridge/amd/amd8111
by svn＠coreboot.org 15 Aug '08

15 Aug '08

Author: hailfinger Date: 2008-08-15 21:21:22 +0200 (Fri, 15 Aug 2008) New Revision: 768 Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/amd8111.h Log: device_t -> struct device conversions. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-08-15 19:08:44 UTC (rev 767) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-08-15 19:21:22 UTC (rev 768) @@ -24,7 +24,7 @@ #include <device/pci_ops.h> #include "amd8111.h" -static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); Modified: coreboot-v3/southbridge/amd/amd8111/amd8111.h =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.h 2008-08-15 19:08:44 UTC (rev 767) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.h 2008-08-15 19:21:22 UTC (rev 768) @@ -1,6 +1,6 @@ #ifndef AMD8111_H #define AMD8111_H -void amd8111_enable(device_t dev); +void amd8111_enable(struct device * dev); #endif /* AMD8111_H */

1 0

r767 - in coreboot-v3/southbridge/amd: . amd8111
by svn＠coreboot.org 15 Aug '08

15 Aug '08

Author: rminnich Date: 2008-08-15 21:08:44 +0200 (Fri, 15 Aug 2008) New Revision: 767 Added: coreboot-v3/southbridge/amd/amd8111/ coreboot-v3/southbridge/amd/amd8111/Makefile coreboot-v3/southbridge/amd/amd8111/ac97.c coreboot-v3/southbridge/amd/amd8111/ac97audio.dts coreboot-v3/southbridge/amd/amd8111/ac97modem.dts coreboot-v3/southbridge/amd/amd8111/acpi.c coreboot-v3/southbridge/amd/amd8111/acpi.dts coreboot-v3/southbridge/amd/amd8111/amd8111.c coreboot-v3/southbridge/amd/amd8111/amd8111.h coreboot-v3/southbridge/amd/amd8111/amd8111_smbus.h coreboot-v3/southbridge/amd/amd8111/ide.c coreboot-v3/southbridge/amd/amd8111/ide.dts coreboot-v3/southbridge/amd/amd8111/lpc.c coreboot-v3/southbridge/amd/amd8111/lpc.dts coreboot-v3/southbridge/amd/amd8111/nic.c coreboot-v3/southbridge/amd/amd8111/nic.dts coreboot-v3/southbridge/amd/amd8111/pci.c coreboot-v3/southbridge/amd/amd8111/pci.dts coreboot-v3/southbridge/amd/amd8111/smbus.c coreboot-v3/southbridge/amd/amd8111/smbus.dts coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c coreboot-v3/southbridge/amd/amd8111/stage1_enable_rom.c coreboot-v3/southbridge/amd/amd8111/stage1_reset.c coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c coreboot-v3/southbridge/amd/amd8111/usb.c coreboot-v3/southbridge/amd/amd8111/usb.dts coreboot-v3/southbridge/amd/amd8111/usb2.c coreboot-v3/southbridge/amd/amd8111/usb2.dts Log: Bring 8111 over to v3. Rename files and functions as needed. There is regularity to the naming. Stage1 stuff is called stage1_*. The rest is not. Most .c files have a corresponding .dts. The code is simpler and smaller and has less duplication. Most (all) romcc artifacts removed. I've made a lot of effort to get copyright headers done correctly, using 'svn log'. next are the 8132, 8151, and serengeti, then comes simnow. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Added: coreboot-v3/southbridge/amd/amd8111/Makefile =================================================================== --- coreboot-v3/southbridge/amd/amd8111/Makefile (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/Makefile 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer <stepan(a)coresystems.de> for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_AMD8111),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/amd8111/amd8111.c + +STAGE2_CHIPSET_SRC += \ + $(src)/southbridge/amd/amd8111/ac97.c \ + $(src)/southbridge/amd/amd8111/acpi.c \ + $(src)/southbridge/amd/amd8111/ide.c \ + $(src)/southbridge/amd/amd8111/lpc.c \ + $(src)/southbridge/amd/amd8111/nic.c \ + $(src)/southbridge/amd/amd8111/pci.c \ + $(src)/southbridge/amd/amd8111/smbus.c \ + $(src)/southbridge/amd/amd8111/usb.c \ + $(src)/southbridge/amd/amd8111/usb2.c + +STAGE0_CHIPSET_OBJ += $(obj)/southbridge/amd/amd8111/stage1.o + + +endif Added: coreboot-v3/southbridge/amd/amd8111/ac97.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux NetworX + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "amd8111.h" + +static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x2c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations ac97audio = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x746D}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = NULL, + .ops_pci = &lops_pci, +}; + +struct device_operations ac97modem = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x746E}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = NULL, + .ops_pci = &lops_pci, +}; + Added: coreboot-v3/southbridge/amd/amd8111/ac97audio.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97audio.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/ac97audio.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +{ + device_operations = "ac97modem"; + /* configuration variables go here */ +}; Added: coreboot-v3/southbridge/amd/amd8111/ac97modem.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ac97modem.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/ac97modem.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "ac97modem"; + /* configuration variables go here */ +}; Added: coreboot-v3/southbridge/amd/amd8111/acpi.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,238 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux NetworX + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <device/device.h> +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h>#include "amd8111.h" +#include "amd8111_smbus.h" + +#define PREVIOUS_POWER_STATE 0x43 +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define SLOW_CPU_OFF 0 +#define SLOW_CPU__ON 1 + +#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + + +static int lsmbus_recv_byte(struct device * dev) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_recv_byte(res->base, device); +} + +static int lsmbus_send_byte(struct device * dev, u8 val) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_send_byte(res->base, device, val); +} + + +static int lsmbus_read_byte(struct device * dev, u8 address) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(struct device * dev, u8 address, u8 val) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_write_byte(res->base, device, address, val); +} + +#ifdef CONFIG_ACPI_TABLE +unsigned pm_base; +#endif + +static void acpi_init(struct device *dev) +{ + u8 byte; + u16 word; + u16 pm10_bar; + u32 dword; + int on; + +#if 0 + printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); + byte = pci_read_config8(dev, 0x49); + pci_write_config8(dev, 0x49, byte | (1<<2)); + + + byte = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2)); + + /* added from sourceforge */ + byte = pci_read_config8(dev, 0x48); + pci_write_config8(dev, 0x48, byte | (1<<3)); + + printk(BIOS_DEBUG, "done.\n"); + + + printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. "); + word = pci_read_config16(dev, 0x46); + pci_write_config16(dev, 0x46, word | (1<<9)); + printk(BIOS_DEBUG, "done.\n"); + + +#endif + /* To enable the register 0xcf9 in the IO space + * bit [D5] is set in the amd8111 configuration register. + * The config. reg. is devBx41. Register 0xcf9 allows + * hard reset capability to the system. For the ACPI + * reset.reg values in fadt.c to work this register + * must be enabled. + */ + byte = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); + + /* power on after power fail */ + on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&on, "power_on_after_fail"); + byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); + byte &= ~0x40; + if (!on) { + byte |= 0x40; + } + pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); + printk_info("set power %s after power fail\n", on?"on":"off"); + + /* switch serial irq logic from quiet mode to continuous + * mode for Winbond W83627HF Rev. 17 + */ + byte = pci_read_config8(dev, 0x4a); + pci_write_config8(dev, 0x4a, byte | (1<<6)); + + /* Throttle the CPU speed down for testing */ + on = SLOW_CPU_OFF; + get_option(&on, "slow_cpu"); + if(on) { + pm10_bar = (pci_read_config16(dev, 0x58)&0xff00); + outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); + dword = inl(pm10_bar + 0x10); + on = 8-on; + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", + (on*12)+(on>>1),(on&1)*5); + } + +#ifdef CONFIG_ACPI_TABLE + pm_base = pci_read_config16(dev, 0x58) & 0xff00; + printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); +#endif + +} + +static void acpi_read_resources(struct device * dev) +{ + struct resource *resource; + + /* Handle the generic bars */ + pci_dev_read_resources(dev); + + /* Add the ACPI/SMBUS bar */ + resource = new_resource(dev, 0x58); + resource->base = 0; + resource->size = 256; + resource->align = log2(256); + resource->gran = log2(256); + resource->limit = 65536; + resource->flags = IORESOURCE_IO; + resource->index = 0x58; +} + +static void acpi_enable_resources(struct device * dev) +{ + u8 byte; + /* Enable the generic pci resources */ + pci_dev_enable_resources(dev); + + /* Enable the ACPI/SMBUS Bar */ + byte = pci_read_config8(dev, 0x41); + byte |= (1 << 7); + pci_write_config8(dev, 0x41, byte); + + /* Set the class code */ + pci_write_config32(dev, 0x60, 0x06800000); + +} + +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x7c, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations ac97audio = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_ACPI}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = acpi_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = acpi_enable_resources, + .phase6_init = acpi_init, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; Added: coreboot-v3/southbridge/amd/amd8111/acpi.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/acpi.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/acpi.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "ac97modem"; + /* configuration variables go here */ +}; Added: coreboot-v3/southbridge/amd/amd8111/amd8111.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,106 @@ +/* + * AMD 8111 "southbridge" + * This file is part of the coreboot project. + * Copyright (C) 2004-2005 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Ollie Lo + * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "amd8111.h" + +void amd8111_enable(struct device * dev) +{ + struct device * lpc_dev; + struct device * bus_dev; + unsigned index; + unsigned reg_old, reg; + + /* See if we are behind the amd8111 pci bridge */ + bus_dev = dev->bus->dev; + if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) && + (bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI)) + { + unsigned devfn; + devfn = bus_dev->path.pci.devfn + (1 << 3); + lpc_dev = dev_find_slot(bus_dev->bus->secondary, devfn); + index = ((dev->path.u.pci.devfn & ~7) >> 3) + 8; + if (dev->path.u.pci.devfn == 2) { /* EHCI */ + index = 16; + } + } else { + unsigned devfn; + devfn = (dev->path.u.pci.devfn) & ~7; + lpc_dev = dev_find_slot(dev->bus->secondary, devfn); + index = dev->path.u.pci.devfn & 7; + } + if ((!lpc_dev) || (index >= 17)) { + return; + } + if ((lpc_dev->vendor != PCI_VENDOR_ID_AMD) || + (lpc_dev->device != PCI_DEVICE_ID_AMD_8111_ISA)) + { + u32 id; + id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); + if (id != (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8111_ISA << 16))) { + return; + } + } + + if (index < 16) { + reg = reg_old = pci_read_config16(lpc_dev, 0x48); + reg &= ~(1 << index); + if (dev->enabled) { + reg |= (1 << index); + } + if (reg != reg_old) { + pci_write_config16(lpc_dev, 0x48, reg); + } + } + else if (index == 16) { + reg = reg_old = pci_read_config8(lpc_dev, 0x47); + reg &= ~(1 << 7); + if (!dev->enabled) { + reg |= (1 << 7); + } + if (reg != reg_old) { + pci_write_config8(lpc_dev, 0x47, reg); + } + } +} + +struct device_operations mcp55_ide = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase6_init = NULL, + .ops_pci = &pci_dev_ops_pci, +}; Added: coreboot-v3/southbridge/amd/amd8111/amd8111.h =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111.h (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/amd8111.h 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,6 @@ +#ifndef AMD8111_H +#define AMD8111_H + +void amd8111_enable(device_t dev); + +#endif /* AMD8111_H */ Added: coreboot-v3/southbridge/amd/amd8111/amd8111_smbus.h =================================================================== --- coreboot-v3/southbridge/amd/amd8111/amd8111_smbus.h (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/amd8111_smbus.h 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,17 @@ +#include <device/smbus_def.h> + +#define SMBGSTATUS 0xe0 +#define SMBGCTL 0xe2 +#define SMBHSTADDR 0xe4 +#define SMBHSTDAT 0xe6 +#define SMBHSTCMD 0xe8 +#define SMBHSTFIFO 0xe9 + +#define SMBUS_TIMEOUT (100*1000*10) +#define SMBUS_STATUS_MASK 0xfbff + +static inline void smbus_delay(void) +{ + outb(0x80, 0x80); +} + Added: coreboot-v3/southbridge/amd/amd8111/ide.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux NetworX + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#nclude "amd8111.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_amd_amd8111_ide_config *conf; + /* Enable ide devices so the linux ide driver will work */ + u16 word; + u8 byte; + conf = dev->chip_info; + + word = pci_read_config16(dev, 0x40); + /* Ensure prefetch is disabled */ + word &= ~((1 << 15) | (1 << 13)); + if (conf->ide1_enable) { + /* Enable secondary ide interface */ + word |= (1<<0); + printk(BIOS_DEBUG, "IDE1 "); + } + if (conf->ide0_enable) { + /* Enable primary ide interface */ + word |= (1<<1); + printk(BIOS_DEBUG, "IDE0 "); + } + + word |= (1<<12); + word |= (1<<14); + + pci_write_config16(dev, 0x40, word); + + + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); + + word = 0x0f; + pci_write_config16(dev, 0x42, word); +} + +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations mcp55_ide = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_IDE}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init, + .ops_pci = &lops_pci +}; Added: coreboot-v3/southbridge/amd/amd8111/ide.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/ide.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/ide.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_ide"; + ide0_enable = "0"; + ide1_enable = "1"; +}; Added: coreboot-v3/southbridge/amd/amd8111/lpc.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux NetworX, SuSE Linux AG + * Copyright (C) 2006 AMD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "amd8111.h" + +#define NMI_OFF 0 + +struct ioapicreg { + unsigned int reg; + unsigned int value_low, value_high; +}; + +static struct ioapicreg ioapicregvalues[] = { +#define ALL (0xff << 24) +#define NONE (0) +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + /* IO-APIC virtual wire mode configuration */ + /* mask, trigger, polarity, destination, delivery, vector */ + { 0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT, NONE}, + { 1, DISABLED, NONE}, + { 2, DISABLED, NONE}, + { 3, DISABLED, NONE}, + { 4, DISABLED, NONE}, + { 5, DISABLED, NONE}, + { 6, DISABLED, NONE}, + { 7, DISABLED, NONE}, + { 8, DISABLED, NONE}, + { 9, DISABLED, NONE}, + { 10, DISABLED, NONE}, + { 11, DISABLED, NONE}, + { 12, DISABLED, NONE}, + { 13, DISABLED, NONE}, + { 14, DISABLED, NONE}, + { 15, DISABLED, NONE}, + { 16, DISABLED, NONE}, + { 17, DISABLED, NONE}, + { 18, DISABLED, NONE}, + { 19, DISABLED, NONE}, + { 20, DISABLED, NONE}, + { 21, DISABLED, NONE}, + { 22, DISABLED, NONE}, + { 23, DISABLED, NONE}, + /* Be careful and don't write past the end... */ +}; + +static void setup_ioapic(void) +{ + int i; + unsigned long value_low, value_high; + unsigned long ioapic_base = 0xfec00000; + volatile unsigned long *l; + struct ioapicreg *a = ioapicregvalues; + unsigned long bsp_apicid = lapicid(); + + l = (unsigned long *) ioapic_base; + + ioapicregvalues[0].value_high = bsp_apicid<<(56-32); + printk(BIOS_DEBUG, "amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); + + for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]); + i++, a++) { + l[0] = (a->reg * 2) + 0x10; + l[4] = a->value_low; + value_low = l[4]; + l[0] = (a->reg *2) + 0x11; + l[4] = a->value_high; + value_high = l[4]; + if ((i==0) && (value_low == 0xffffffff)) { + printk_warning("IO APIC not responding.\n"); + return; + } + printk(BIOS_SPEW, "for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", + a->reg, a->value_low, a->value_high); + } +} + +static void enable_hpet(struct device *dev) +{ + unsigned long hpet_address; + + pci_write_config32(dev,0xa0, 0xfed00001); + hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; + printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); + +} + +static void lpc_init(struct device *dev) +{ + u8 byte; + int nmi_option; + + /* IO APIC initialization */ + byte = pci_read_config8(dev, 0x4B); + byte |= 1; + pci_write_config8(dev, 0x4B, byte); + setup_ioapic(); + + /* posted memory write enable */ + byte = pci_read_config8(dev, 0x46); + pci_write_config8(dev, 0x46, byte | (1<<0)); + + /* Enable 5Mib Rom window */ + byte = pci_read_config8(dev, 0x43); + byte |= 0xc0; + pci_write_config8(dev, 0x43, byte); + + /* Enable Port 92 fast reset */ + byte = pci_read_config8(dev, 0x41); + byte |= (1 << 5); + pci_write_config8(dev, 0x41, byte); + + /* Enable Error reporting */ + /* Set up sync flood detected */ + byte = pci_read_config8(dev, 0x47); + byte |= (1 << 1); + pci_write_config8(dev, 0x47, byte); + + /* Set up NMI on errors */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 1); /* clear PW2LPC error */ + byte |= (1 << 6); /* clear LPCERR */ + pci_write_config8(dev, 0x40, byte); + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte |= (1 << 7); /* set NMI */ + pci_write_config8(dev, 0x40, byte); + } + + /* Initialize the real time clock */ + rtc_init(0); + + /* Initialize isa dma */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers */ + enable_hpet(dev); +} + +static void amd8111_lpc_read_resources(struct device * dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void amd8111_lpc_enable_resources(struct device * dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations amd8111_lpc = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_ISA}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = amd8111_lpc_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = amd8111_lpc_enable_resources, + .phase6_init = lpc_init, + .ops_pci = &lops_pci, +}; Added: coreboot-v3/southbridge/amd/amd8111/lpc.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/lpc.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/lpc.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_lpc"; +}; Added: coreboot-v3/southbridge/amd/amd8111/nic.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,107 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "amd8111.h" + + +#define CMD3 0x54 + +typedef enum { + VAL3 = (1 << 31), /* VAL bit for byte 3 */ + VAL2 = (1 << 23), /* VAL bit for byte 2 */ + VAL1 = (1 << 15), /* VAL bit for byte 1 */ + VAL0 = (1 << 7), /* VAL bit for byte 0 */ +}VAL_BITS; + +typedef enum { + /* VAL3 */ + ASF_INIT_DONE_ALIAS = (1 << 29), + /* VAL2 */ + JUMBO = (1 << 21), + VSIZE = (1 << 20), + VLONLY = (1 << 19), + VL_TAG_DEL = (1 << 18), + /* VAL1 */ + EN_PMGR = (1 << 14), + INTLEVEL = (1 << 13), + FORCE_FULL_DUPLEX = (1 << 12), + FORCE_LINK_STATUS = (1 << 11), + APEP = (1 << 10), + MPPLBA = (1 << 9), + /* VAL0 */ + RESET_PHY_PULSE = (1 << 2), + RESET_PHY = (1 << 1), + PHY_RST_POL = (1 << 0), +}CMD3_BITS; + +static void nic_init(struct device *dev) +{ + struct southbridge_amd_amd8111_nic_config *conf; + struct resource *resource; + unsigned long mmio; + + conf = dev->device_configuration; + resource = find_resource(dev, PCI_BASE_ADDRESS_0); + mmio = resource->base; + + /* Hard Reset PHY */ + printk(BIOS_DEBUG, "Reseting PHY... "); + if (conf->phy_lowreset) { + writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3)); + } else { + writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3)); + } + mdelay(15); + writel(RESET_PHY, (void *)(mmio + CMD3)); + printk(BIOS_DEBUG, "Done\n"); +} + +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0xc8, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations amd8111_nic = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_NIC}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = nic_init, + .ops_pci = &lops_pci, +}; + Added: coreboot-v3/southbridge/amd/amd8111/nic.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/nic.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/nic.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_nic"; +}; Added: coreboot-v3/southbridge/amd/amd8111/pci.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/pci.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/pci.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,83 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2003 Linux Networx + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "amd8111.h" + +static void pci_init(struct device *dev) +{ + + /* Enable pci error detecting */ + u32 dword; + + /* System error enable */ + dword = pci_read_config32(dev, 0x04); + dword |= (1<<8); /* System error enable */ + dword |= (7<<28); /* Clear possible errors */ + pci_write_config32(dev, 0x04, dword); + + /* System,Parity,timer,and abort error enable */ + dword = pci_read_config32(dev, 0x3c); + dword |= (1<<16); /* Parity */ + dword |= (1<<17); /* System */ + dword |= (1<<21); /* Master abort */ +// dword &= ~(1<<21); /* Master abort */ +// dword |= (1<<27); /* Discard timer */ + dword &= ~(1<<27); /* Discard timer */ + dword |= (1<<26); /* DTSTAT error clear */ + pci_write_config32(dev, 0x3c, dword); + + /* CRC flood enable */ + dword = pci_read_config32(dev, 0xc4); + dword |= (1<<1); /* CRC Flood enable */ + dword |= (1<<8); /* Clear any CRC errors */ + dword |= (1<<4); /* Clear any LKFAIL errors */ + pci_write_config32(dev, 0xc4, dword); + + /* Clear possible errors */ + dword = pci_read_config32(dev, 0x1c); + dword |= (1<<27); /* STA */ + dword |= (1<<28); /* RTA */ + dword |= (1<<29); /* RMA */ + dword |= (1<<30); /* RSE */ + dword |= (1<<31); /* DPE */ + dword |= (1<<24); /* MDPE */ + pci_write_config32(dev, 0x1c, dword); +} + +struct device_operations amd8111_pci = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_PCI}}}, + .constructor = default_device_constructor, + .phase3_scan = pci_scan_bridge, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_bus_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = pci_init, +}; Added: coreboot-v3/southbridge/amd/amd8111/pci.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/pci.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/pci.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_pci"; +}; Added: coreboot-v3/southbridge/amd/amd8111/smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,64 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2004 Linux Networx + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/smbus.h> +#include <arch/io.h> +#include "amd8111.h" + +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x44, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct smbus_bus_operations lops_smbus_bus = { + /* I haven't seen the 2.0 SMBUS controller used yet. */ +}; +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations amd8111_smbus = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_SMB}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_enable_disable = amd8111_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = NULL, + .ops_pci = &lops_pci + .ops_smbus_bus = &lops_smbus_bus, +}; Added: coreboot-v3/southbridge/amd/amd8111/smbus.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/smbus.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/smbus.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_smbus"; +}; Added: coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/stage1_ctrl.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,146 @@ +/* + * AMD 8111 "southbridge" + * This file is part of the coreboot project. + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Marc Jones, AMD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "amd8111.h" + + +/* by yhlu 2005.10 */ +/** + * Get the device fn for the 8111. + * @param bus the bus on which to search + * @return The device number, in the range 0-31 + */ +static u32 get_sbdn(unsigned bus) +{ + u32 dev; + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + + pci_conf1_find_on_bus(bus, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI, &dev); + + /* this makes no sense. At all. I wonder if this is an ancient bug. >> 15? */ +#warning shift right 15? makes no sense. + + return (dev>>15) & 0x1f; + +} + +/** + * Get the device fn for the 8111. + * @param bus the bus on which to search + * @return The device number, in the range 0-31 + */ +static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) +{ + u32 dev; + u8 byte; + + dev = PCI_BDF(sbbusn, sbdn+1, 3); //ACPI + /* enable cf9 */ + byte = pci_conf1_read_config8(dev, 0x41); + byte |= (1<<6) | (1<<5); + pci_conf1+write_config8(dev, 0x41, byte); +} + +/** + * Enable "cf9". cf9 is a commonly used 8-bit IO address for reset, overlapping the 32-bit cf8 config address. + */ +static void enable_cf9(void) +{ + u32 sblk = get_sblk(); + u32 sbbusn = get_sbbusn(sblk); + u32 sbdn = get_sbdn(sbbusn); + + enable_cf9_x(sbbusn, sbdn); +} + +/** + * Perform a hard reset. Set the "bios reset" indicator to be used by subsequent coreboot to know we + * came out of a coreboot-initiated reset. + * @return Never returns. + */ +static void hard_reset(void) +{ + set_bios_reset(); + /* reset */ + enable_cf9(); + outb(0x0e, 0x0cf9); // make sure cf9 is enabled +} + +/** + * Enable a FID change on the southbridge. + * @param sbbusn south bridge bus number + * @param sbdn southbridge device numer + */ +static void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn) +{ + u32 dev; + + dev = PCI_BDF(sbbusn, sbdn+1, 3); // ACPI + + pci_conf1_write_config8(dev, 0x74, 4); + + /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + pci_conf1_write_config32(dev, 0x70, 2<<12); + +} + +/** + * Initiate a soft reset given a bus and device number. Indicate via set_bios_reset that we did so. + * @param sbbusn south bridge bus number + * @param sbdn southbridge device numer + * @return never + */ +static void soft_reset_x(unsigned sbbusn, unsigned sbdn) +{ + u32 dev; + + dev = PCI_BDF(sbbusn, sbdn+1, 0); //ISA + + /* Reset */ + set_bios_reset(); + pci_conf1_write_config8(dev, 0x47, 1); + +} + +/** + * Initiate a soft reset by finding the southbridge and calling soft_reset_x + * @return never + */ +static void soft_reset(void) +{ + + unsigned sblk = get_sblk(); + unsigned sbbusn = get_sbbusn(sblk); + unsigned sbdn = get_sbdn(sbbusn); + + return soft_reset_x(sbbusn, sbdn); + +} Added: coreboot-v3/southbridge/amd/amd8111/stage1_enable_rom.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_enable_rom.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/stage1_enable_rom.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,48 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2003 Linux NetworX + * Copyright (C) 2004 Ollie Lo + * Copyright (C) 2006 YingHai Lu + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> + +/** + * Enable the 5 MB address space for the ROM + */ +static void amd8111_enable_rom(void) +{ + u8 byte; + u32 dev; + + /* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */ + /* Locate the amd8111 */ + pci_locate_device_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA, &dev); + + /* Set the 5MB enable bits */ + byte = pci_conf1_read_config8(dev, 0x43); + byte |= 0xC0; + pci_conf1_write_config8(dev, 0x43, byte); +} Added: coreboot-v3/southbridge/amd/amd8111/stage1_reset.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_reset.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/stage1_reset.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,47 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2004 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> + +void hard_reset(void) +{ + u32 dev; + unsigned int bus; + unsigned int node = 0; + unsigned int link = get_sblk(); + + /* Find the device. + * There can only be one 8111 on a hypertransport chain/bus. + */ + bus = node_link_to_bus(node, link); + pci_locate_device_on_bus(0, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA, &dev); + + /* Reset */ + set_bios_reset(); + pci_write_config8(dev, 0x47, 1); +} Added: coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/stage1_smbus.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,291 @@ +/* + * AMD 8111 "southbridge" + * This file is part of the coreboot project. + * Copyright (C) 2004-2005 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Ollie Lo + * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "amd8111.h" +#include "amd8111_smbus.h" + +#define SMBUS_IO_BASE 0x0f00 + +void enable_smbus(void) +{ + u32 bdf; + u8 enable; + + /* this 746b is the ACPI device. This is from original code. It's weird however. */ + pci_locate_device_on_bus(0, PCI_VENDOR_ID_AMD, 0x746b, &dev); + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\r\n"); + } + + pci_conf1_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); + enable = pci_conf1_read_config8(dev, 0x41); + pci_conf1_write_config8(dev, 0x41, enable | (1 << 7)); + + /* check that we can see the smbus controller I/O. */ + if (inw(SMBUS_IO_BASE)==0xFF){ + die("SMBUS controller I/O not found\n"); + } + + /* clear any lingering errors, so the transaction will run */ + outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); + printk(BIOS_SPEW, "SMBus controller enabled\r\n"); +} + +int smbus_wait_until_ready(u16 smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + u16 val; + smbus_delay(); + val = inw(smbus_io_base + SMBGSTATUS); + if ((val & 0x800) == 0) { + break; + } + if(loops == (SMBUS_TIMEOUT / 2)) { + outw(inw(smbus_io_base + SMBGSTATUS), + smbus_io_base + SMBGSTATUS); + } + } while(--loops); + return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT; +} + +int smbus_wait_until_done(u16 smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + u16 val; + smbus_delay(); + + val = inw(smbus_io_base + SMBGSTATUS); + if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) { + break; + } + } while(--loops); + return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT; +} + +int do_smbus_recv_byte(u16 smbus_io_base, u16 device) +{ + u16 global_status_register; + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(0, smbus_io_base + SMBHSTCMD); + /* set up for a send byte */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* set the data word...*/ + outw(0, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + /* read results of transaction */ + byte = inw(smbus_io_base + SMBHSTDAT) & 0xff; + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return byte; +} + +int do_smbus_send_byte(u16 smbus_io_base, u16 device, u16 value) +{ + u16 global_status_register; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(0, smbus_io_base + SMBHSTCMD); + /* set up for a send byte */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x1), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* set the data word...*/ + outw(value, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return 0; +} + + +int do_smbus_read_byte(u16 smbus_io_base, u16 device, u8 address) +{ + u16 global_status_register; + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(address & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a byte data read */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* clear the data word...*/ + outw(0, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + /* read results of transaction */ + byte = inw(smbus_io_base + SMBHSTDAT) & 0xff; + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return byte; +} + +int do_smbus_write_byte(u16 smbus_io_base, u16 device, u8 address, u8 val) +{ + u16 global_status_register; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + outb(address & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a byte data write */ /* FIXME */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x2), smbus_io_base + SMBGCTL); + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* write the data word...*/ + outw(val, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return 0; +} + + + +int smbus_recv_byte(u16 device) +{ + return do_smbus_recv_byte(SMBUS_IO_BASE, device); +} + +int smbus_send_byte(u16 device, u8 val) +{ + return do_smbus_send_byte(SMBUS_IO_BASE, device, val); +} + +int smbus_read_byte(u16 device, u16 address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} + +int smbus_write_byte(u16 device, u16 address, u8 val) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); +} + Added: coreboot-v3/southbridge/amd/amd8111/usb.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,60 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2004 Linux Networx + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/smbus.h> +#include <arch/io.h> +#include "amd8111.h" + + +static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device) +{ + pci_write_config32(dev, 0x70, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = lpci_set_subsystem, +}; + +struct device_operations amd8111_usb = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_USB}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = NULL, + .ops_pci = &lops_pci +}; Added: coreboot-v3/southbridge/amd/amd8111/usb.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/usb.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_usb"; +}; Added: coreboot-v3/southbridge/amd/amd8111/usb2.c =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb2.c (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,58 @@ +/* + * + * This file is part of the coreboot project. + * Copyright (C) 2003 Tyan + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/smbus.h> +#include <arch/io.h> +#include "amd8111.h" + +static void amd8111_usb2_enable(struct device *dev) +{ + // Due to buggy USB2 we force it to disable. + dev->enabled = 0; + amd8111_enable(dev); + printk(BIOS_DEBUG, "USB2 disabled.\n"); +} + +struct device_operations amd8111_usb2 = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_8111_USB}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_enable_disable = amd8111_usb2_enable, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = NULL, +}; Added: coreboot-v3/southbridge/amd/amd8111/usb2.dts =================================================================== --- coreboot-v3/southbridge/amd/amd8111/usb2.dts (rev 0) +++ coreboot-v3/southbridge/amd/amd8111/usb2.dts 2008-08-15 19:08:44 UTC (rev 767) @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "amd8111_usb"; +};

1 0

[PATCH] v3: Fix up i440BX emulation RAM init
by Carl-Daniel Hailfinger 15 Aug '08

15 Aug '08

CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill it. Since it was the only content of the i440bxemulation northbridge Kconfig, kill that file as well. The i440BX RAM size is determined from the dts and the chipset specified size is ignored. Print a warning for that, especially because v2 uses the chipset specified RAM size. Build and boot tested on qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-i440bx_ramsize/Kconfig =================================================================== --- corebootv3-i440bx_ramsize/Kconfig (Revision 765) +++ corebootv3-i440bx_ramsize/Kconfig (Arbeitskopie) @@ -94,7 +94,6 @@ boolean # Source all northbridge/southbridge/superio Kconfig files: -source northbridge/intel/i440bxemulation/Kconfig menu "Payload" Index: corebootv3-i440bx_ramsize/mainboard/pcengines/alix1c/defconfig =================================================================== --- corebootv3-i440bx_ramsize/mainboard/pcengines/alix1c/defconfig (Revision 765) +++ corebootv3-i440bx_ramsize/mainboard/pcengines/alix1c/defconfig (Arbeitskopie) @@ -91,7 +91,6 @@ CONFIG_NORTHBRIDGE_AMD_GEODELX=y CONFIG_SOUTHBRIDGE_AMD_CS5536=y CONFIG_SUPERIO_WINBOND_W83627HF=y -CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 # # Payload Index: corebootv3-i440bx_ramsize/mainboard/pcengines/alix2c3/defconfig =================================================================== --- corebootv3-i440bx_ramsize/mainboard/pcengines/alix2c3/defconfig (Revision 765) +++ corebootv3-i440bx_ramsize/mainboard/pcengines/alix2c3/defconfig (Arbeitskopie) @@ -84,7 +84,6 @@ # CONFIG_NORTHBRIDGE_AMD_GEODELX=y CONFIG_SOUTHBRIDGE_AMD_CS5536=y -CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 # # Payload Index: corebootv3-i440bx_ramsize/mainboard/emulation/qemu-x86/defconfig =================================================================== --- corebootv3-i440bx_ramsize/mainboard/emulation/qemu-x86/defconfig (Revision 765) +++ corebootv3-i440bx_ramsize/mainboard/emulation/qemu-x86/defconfig (Arbeitskopie) @@ -83,7 +83,6 @@ CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION=y CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y CONFIG_SUPERIO_WINBOND_W83627HF=y -CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 # # Payload Index: corebootv3-i440bx_ramsize/northbridge/intel/i440bxemulation/Kconfig =================================================================== --- corebootv3-i440bx_ramsize/northbridge/intel/i440bxemulation/Kconfig (Revision 765) +++ corebootv3-i440bx_ramsize/northbridge/intel/i440bxemulation/Kconfig (Arbeitskopie) @@ -1,27 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> -## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE - int - default 32 # Mbytes - help - This is the default RAM size of emulation. - Index: corebootv3-i440bx_ramsize/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- corebootv3-i440bx_ramsize/northbridge/intel/i440bxemulation/i440bx.c (Revision 765) +++ corebootv3-i440bx_ramsize/northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) @@ -56,9 +56,12 @@ struct northbridge_intel_i440bxemulation_domain_config *device_configuration = dev->device_configuration; tolmk = device_configuration->ramsize * 1024; + printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts " + "settings of %d kB instead.\n", tolmk); mc_dev = dev->link[0].children; if (mc_dev) { idx = 10; +#warning FIXME: We have no memory hole between 640 and 768 kB ram_resource(dev, idx++, 0, tolmk); } phase4_assign_resources(&dev->link[0]); -- http://www.hailfinger.org/

2 2

r766 - in coreboot-v3: . mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c mainboard/pcengines/alix2c3 northbridge/intel/i440bxemulation
by svn＠coreboot.org 15 Aug '08

15 Aug '08

Author: hailfinger Date: 2008-08-15 18:41:37 +0200 (Fri, 15 Aug 2008) New Revision: 766 Removed: coreboot-v3/northbridge/intel/i440bxemulation/Kconfig Modified: coreboot-v3/Kconfig coreboot-v3/mainboard/emulation/qemu-x86/defconfig coreboot-v3/mainboard/pcengines/alix1c/defconfig coreboot-v3/mainboard/pcengines/alix2c3/defconfig coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c Log: CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill it. Since it was the only content of the i440bxemulation northbridge Kconfig, kill that file as well. The i440BX RAM size is determined from the dts and the chipset specified size is ignored. Print a warning for that, especially because v2 uses the chipset specified RAM size. Build and boot tested on qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-08-14 17:00:11 UTC (rev 765) +++ coreboot-v3/Kconfig 2008-08-15 16:41:37 UTC (rev 766) @@ -94,7 +94,6 @@ boolean # Source all northbridge/southbridge/superio Kconfig files: -source northbridge/intel/i440bxemulation/Kconfig menu "Payload" Modified: coreboot-v3/mainboard/emulation/qemu-x86/defconfig =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-08-14 17:00:11 UTC (rev 765) +++ coreboot-v3/mainboard/emulation/qemu-x86/defconfig 2008-08-15 16:41:37 UTC (rev 766) @@ -83,7 +83,6 @@ CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION=y CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y CONFIG_SUPERIO_WINBOND_W83627HF=y -CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 # # Payload Modified: coreboot-v3/mainboard/pcengines/alix1c/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/defconfig 2008-08-14 17:00:11 UTC (rev 765) +++ coreboot-v3/mainboard/pcengines/alix1c/defconfig 2008-08-15 16:41:37 UTC (rev 766) @@ -91,7 +91,6 @@ CONFIG_NORTHBRIDGE_AMD_GEODELX=y CONFIG_SOUTHBRIDGE_AMD_CS5536=y CONFIG_SUPERIO_WINBOND_W83627HF=y -CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 # # Payload Modified: coreboot-v3/mainboard/pcengines/alix2c3/defconfig =================================================================== --- coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-08-14 17:00:11 UTC (rev 765) +++ coreboot-v3/mainboard/pcengines/alix2c3/defconfig 2008-08-15 16:41:37 UTC (rev 766) @@ -84,7 +84,6 @@ # CONFIG_NORTHBRIDGE_AMD_GEODELX=y CONFIG_SOUTHBRIDGE_AMD_CS5536=y -CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 # # Payload Deleted: coreboot-v3/northbridge/intel/i440bxemulation/Kconfig =================================================================== --- coreboot-v3/northbridge/intel/i440bxemulation/Kconfig 2008-08-14 17:00:11 UTC (rev 765) +++ coreboot-v3/northbridge/intel/i440bxemulation/Kconfig 2008-08-15 16:41:37 UTC (rev 766) @@ -1,27 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> -## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -config NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE - int - default 32 # Mbytes - help - This is the default RAM size of emulation. - Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-14 17:00:11 UTC (rev 765) +++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-15 16:41:37 UTC (rev 766) @@ -56,9 +56,12 @@ struct northbridge_intel_i440bxemulation_domain_config *device_configuration = dev->device_configuration; tolmk = device_configuration->ramsize * 1024; + printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts " + "settings of %d kB instead.\n", tolmk); mc_dev = dev->link[0].children; if (mc_dev) { idx = 10; +#warning FIXME: We have no memory hole between 640 and 768 kB ram_resource(dev, idx++, 0, tolmk); } phase4_assign_resources(&dev->link[0]);

1 0

[PATCH] [buildrom] get mkelfimage from our svn tree
by Ward Vandewege 15 Aug '08

15 Aug '08

See attached. The bulk of it is just the svn remove of the two patches that have already been applied to mkelfimage in our svn repo. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

4 5

r3511 - trunk/util/superiotool
by svn＠coreboot.org 15 Aug '08

15 Aug '08

Author: stepan Date: 2008-08-15 11:46:55 +0200 (Fri, 15 Aug 2008) New Revision: 3511 Modified: trunk/util/superiotool/smsc.c Log: fix typo in superiotool (trivial) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/superiotool/smsc.c =================================================================== --- trunk/util/superiotool/smsc.c 2008-08-14 14:40:10 UTC (rev 3510) +++ trunk/util/superiotool/smsc.c 2008-08-15 09:46:55 UTC (rev 3511) @@ -562,7 +562,7 @@ {0x5b, "SIO10N268", { /* Init: 0x55. Exit: 0xaa. Ports: 0x2e/0x4e. */ {NOLDN, NULL, - {0x00,0x01,0x03,0x04,0x04,0x05,0x06,0x07,0x08,0x09, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, 0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,

1 0

underclocking CPU
by CuiBo 15 Aug '08

15 Aug '08

Hey Coreboot guys, I am looking forward to turn an old S939 AMD processor and an Asus A8VE-SE into a high performance router. To make the power profile fit, I had already underclocked and undervolted the CPU to 800Mhz with vendor BIOS, with 4x multiplier and 200Mhz FSB. Any way I change lower the FSB or multiplier to even lower the clock with coreboot? Thanks, fixture _________________________________________________________________ 用手机MSN聊天写邮件看空间，无限沟通，分享精彩！ http://mobile.msn.com.cn/

1 0

supermicro motherboard support
by Ben McClelland 14 Aug '08

14 Aug '08

Hi, I am interested in putting linuxbios on a supermicro H8DCE board (http://www.supermicro.com/Aplus/motherboard/Opteron/nForce/ H8DCE.cfm). Anyone know if this will or will not work for sure? I have been able to successfully flash the bios with flashrom, but haven't tried coreboot yet. Any help is much appreciated! thanks, -Ben here is output for lspci -vvv: 00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00:01.0 ISA bridge: nVidia Corporation CK804 ISA Bridge (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Kernel modules: ck804xrom 00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 0 Region 0: I/O ports at 9000 [size=32] Region 4: I/O ports at 4c00 [size=64] Region 5: I/O ports at 4c40 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus Kernel modules: i2c-nforce2 00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) (prog-if 10 [OHCI]) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 9 Region 0: Memory at fb5fc000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd Kernel modules: ohci-hcd 00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a3) (prog-if 20 [EHCI]) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 9 Region 0: Memory at fb5e0000 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev f2) (prog-if 8a [Master SecP PriP]) Subsystem: Unknown device f5d9:1011 Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non- prefetchable) [disabled] [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non- prefetchable) [disabled] [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non- prefetchable) [disabled] [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non- prefetchable) [disabled] [size=1] Region 4: I/O ports at 3000 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pata_amd Kernel modules: ata_generic, pata_amd, pata_acpi 00:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev f3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 9 Region 0: I/O ports at c800 [size=8] Region 1: I/O ports at c400 [size=4] Region 2: I/O ports at c000 [size=8] Region 3: I/O ports at bc00 [size=4] Region 4: I/O ports at b800 [size=16] Region 5: Memory at fb5fe000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv Kernel modules: ata_generic, pata_acpi, sata_nv 00:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev f3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 9 Region 0: I/O ports at b400 [size=8] Region 1: I/O ports at b000 [size=4] Region 2: I/O ports at ac00 [size=8] Region 3: I/O ports at a800 [size=4] Region 4: I/O ports at a400 [size=16] Region 5: Memory at fb5fd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv Kernel modules: ata_generic, pata_acpi, sata_nv 00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev a2) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=128 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 10 Region 0: Memory at fb5ff000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at cc00 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable+ DSel=0 DScale=0 PME- Kernel driver in use: forcedeth Kernel modules: forcedeth 00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit + Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal + Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport-driver Kernel modules: shpchp 00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fb300000-fb4fffff Prefetchable memory behind bridge: 00000000fb600000-00000000fc5fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit + Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal + Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport-driver Kernel modules: shpchp 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [a0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [c0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: k8temp Kernel modules: k8temp 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO + <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=N/C LWO=N/C Revision ID: 1.02 Capabilities: [a0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Revision ID: 1.02 Capabilities: [c0] HyperTransport: Host or Secondary Interface !!! Possibly incomplete decoding Command: WarmRst+ DblEnd- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO + <CRCErr=0 Link Config: MLWI=16bit MLWO=16bit LWI=N/C LWO=N/C Revision ID: 1.02 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/ Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: k8temp Kernel modules: k8temp 01:00.0 InfiniBand: Mellanox Technologies MT25204 [InfiniHost III Lx HCA] (rev 20) Subsystem: Mellanox Technologies MT25204 [InfiniHost III Lx HCA] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at fb400000 (64-bit, non-prefetchable) [size=1M] Region 2: Memory at fb800000 (64-bit, prefetchable) [size=8M] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Vital Product Data <?> Capabilities: [90] Message Signalled Interrupts: Mask- 64bit + Queue=0/5 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [84] MSI-X: Enable- Mask- TabSize=32 Vector table: BAR=0 offset=00082000 PBA: BAR=0 offset=00082200 Capabilities: [60] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #8, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Kernel driver in use: ib_mthca Kernel modules: ib_mthca 80:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=15 MastHost- DefDir- DUL- Link Control 0: CFlE+ CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=1 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 1.0GHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [e0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 80:01.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 1: Memory at fcafc000 (32-bit, non-prefetchable) [size=4K] 80:07.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev f3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 9 Region 0: I/O ports at f800 [size=8] Region 1: I/O ports at f400 [size=4] Region 2: I/O ports at f000 [size=8] Region 3: I/O ports at ec00 [size=4] Region 4: I/O ports at e800 [size=16] Region 5: Memory at fcafe000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv Kernel modules: ata_generic, pata_acpi, sata_nv 80:08.0 IDE interface: nVidia Corporation CK804 Serial ATA Controller (rev f3) (prog-if 85 [Master SecO PriO]) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 9 Region 0: I/O ports at e400 [size=8] Region 1: I/O ports at e000 [size=4] Region 2: I/O ports at dc00 [size=8] Region 3: I/O ports at d800 [size=4] Region 4: I/O ports at d400 [size=16] Region 5: Memory at fcafd000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: sata_nv Kernel modules: ata_generic, pata_acpi, sata_nv 80:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev a3) Subsystem: Super Micro Computer Inc Unknown device 1011 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx+ Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 9 Region 0: Memory at fcaff000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at fc00 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: forcedeth Kernel modules: forcedeth 80:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=80, secondary=82, subordinate=82, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit + Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal + Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 2, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport-driver Kernel modules: shpchp 80:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=80, secondary=81, subordinate=81, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fc700000-fc9fffff Prefetchable memory behind bridge: 00000000fcb00000-00000000feafffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1 +,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [48] Message Signalled Interrupts: Mask- 64bit + Queue=0/1 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [58] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <4us ExtTag- RBE- FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal + Unsupported+ RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s, Latency L0 <512ns, L1 <4us ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 1, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport-driver Kernel modules: shpchp 81:00.0 Ethernet controller: MYRICOM Inc. Myri-10G Dual-Protocol NIC (10G-PCIE-8A) Subsystem: MYRICOM Inc. Myri-10G Dual-Protocol NIC (10G- PCIE-8A) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 9 Region 0: Memory at fd000000 (64-bit, prefetchable) [size=16M] Region 2: Memory at fc900000 (64-bit, non-prefetchable) [size=1M] Expansion ROM at fc880000 [disabled] [size=512K] Capabilities: [44] Message Signalled Interrupts: Mask- 64bit + Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [54] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME (D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [5c] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 4096 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Suprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [88] Vendor Specific Information <?>

2 1

r765 - coreboot-v3/northbridge/amd/k8
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: rminnich Date: 2008-08-14 19:00:11 +0200 (Thu, 14 Aug 2008) New Revision: 765 Modified: coreboot-v3/northbridge/amd/k8/raminit.c Log: Continue cleaning up pci calls in stage1. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/k8/raminit.c =================================================================== --- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-14 16:31:24 UTC (rev 764) +++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-14 17:00:11 UTC (rev 765) @@ -39,9 +39,9 @@ #include <amd/k8/k8.h> #include <amd/k8/sysconf.h> #include <device/pci.h> +#include <pci_ops.h> #include <mc146818rtc.h> #include <lib.h> -#include "stage1.h" #ifndef QRANK_DIMM_SUPPORT #define QRANK_DIMM_SUPPORT 0 @@ -56,7 +56,7 @@ static int controller_present(const struct mem_controller *ctrl) { - return pci_read_config32(ctrl->f0, 0) == 0x11001022; + return pci_conf1_read_config32(ctrl->f0, 0) == 0x11001022; } void sdram_set_registers(const struct mem_controller *ctrl) @@ -545,8 +545,8 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) { u32 dcl, nbcap, opt = 1; - nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + nbcap = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; @@ -554,14 +554,14 @@ if (get_option(&opt, "ECC_memory") || opt) { dcl &= ~DCL_DimmEccEn; } - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); } static int is_dual_channel(const struct mem_controller *ctrl) { u32 dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_128BitEn; } @@ -573,7 +573,7 @@ */ #warning "FIXME: Implement a better test for Opterons" u32 nbcap; - nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + nbcap = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); } @@ -584,7 +584,7 @@ * This function must be called after spd_handle_unbuffered_dimms. */ u32 dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBufDimm); } @@ -716,25 +716,25 @@ base1 &= ~0x001ffffe; /* Set the appropriate DIMM base address register */ - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1); #if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1); } #endif /* Enable the memory clocks for this DIMM */ if (base0) { - dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch |= DCH_MEMCLK_EN0 << index; #if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { dch |= DCH_MEMCLK_EN0 << (index + 2); } #endif - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } } @@ -750,7 +750,7 @@ u32 map; u32 dch; - map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); + map = pci_conf1_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); map &= ~(0xf << (index * 4)); #if QRANK_DIMM_SUPPORT == 1 if(sz.rank == 4) { @@ -779,7 +779,7 @@ } } - pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map); + pci_conf1_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map); } @@ -826,8 +826,8 @@ limit_reg = 0x44 + index; base_reg = 0x40 + index; for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) { - pci_write_config32(device, limit_reg, limit); - pci_write_config32(device, base_reg, base); + pci_conf1_write_config32(device, limit_reg, limit); + pci_conf1_write_config32(device, base_reg, base); } } @@ -912,7 +912,7 @@ unsigned cs_mode; u32 value; - value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ if (!(value & 1)) { @@ -928,7 +928,7 @@ return 0; } - value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); + value = pci_conf1_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); cs_mode =( value >> ((index>>1)*4)) & 0xf; if(cs_mode == 0 ) continue; if(common_cs_mode == 0) { @@ -981,13 +981,13 @@ for(index = 0; index < 8; index++) { u32 value; - value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ if (!(value & 1)) { continue; } - pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase); - pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase); + pci_conf1_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask); csbase += csbase_inc; } @@ -1012,7 +1012,7 @@ candidate = 0; for(index = 0; index < 8; index++) { u32 value; - value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2)); /* Is it enabled? */ if (!(value & 1)) { @@ -1054,9 +1054,9 @@ csmask |= 0xfe00; /* For now don't optimize */ /* Write the new base register */ - pci_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase); /* Write the new mask register */ - pci_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask); + pci_conf1_write_config32(ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask); } /* Return the memory size in K */ @@ -1073,10 +1073,10 @@ u32 limit, base; unsigned index; index = node_id << 3; - base = pci_read_config32(ctrl->f1, 0x40 + index); + base = pci_conf1_read_config32(ctrl->f1, 0x40 + index); /* Only look at the limit if the base is enabled */ if ((base & 3) == 3) { - limit = pci_read_config32(ctrl->f1, 0x44 + index); + limit = pci_conf1_read_config32(ctrl->f1, 0x44 + index); end_k = ((limit + 0x00010000) & 0xffff0000) >> 2; } } @@ -1107,8 +1107,8 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask) { printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); - pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0); + pci_conf1_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0); dimm_mask &= ~(1 << index); return dimm_mask; } @@ -1144,7 +1144,7 @@ die("Mixed buffered and registered dimms not supported"); } - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_UnBufDimm; if (unbuffered) { if ((has_dualch) && (!is_cpu_pre_d0())) { @@ -1160,7 +1160,7 @@ dcl |= DCL_UnBufDimm; } } - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); if (is_registered(ctrl)) { printk(BIOS_DEBUG, "Registered\n"); } else { @@ -1228,7 +1228,7 @@ goto single_channel; } /* If the cpu is not capable of doing dual channels don't do dual channels */ - nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + nbcap = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; } @@ -1260,10 +1260,10 @@ } printk(BIOS_SPEW, "Enabling dual channel memory\n"); u32 dcl; - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_32ByteEn; dcl |= DCL_128BitEn; - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); return dimm_mask; single_channel: dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS)); @@ -1384,7 +1384,7 @@ [NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */ }; - value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); + value = pci_conf1_read_config32(ctrl->f3, NORTHBRIDGE_CAP); min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; @@ -1535,7 +1535,7 @@ result.param = get_mem_param(min_cycle_time); /* Update DRAM Config High with our selected memory speed */ - value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + value = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT); #if 0 /* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed @@ -1549,14 +1549,14 @@ #endif value |= result.param->dch_memclk; - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value); static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 }; /* Update DRAM Timing Low with our selected cas latency */ - value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + value = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); value |= latencies[min_latency - 2] << DTL_TCL_SHIFT; - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; return result; @@ -1585,14 +1585,14 @@ return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT); dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; } @@ -1613,14 +1613,14 @@ if (clocks > DTL_TRFC_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT); dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; } @@ -1639,14 +1639,14 @@ if (clocks > DTL_TRCD_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT); dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; } @@ -1664,14 +1664,14 @@ if (clocks > DTL_TRRD_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT); dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; } @@ -1689,14 +1689,14 @@ if (clocks > DTL_TRAS_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT); dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; } @@ -1714,34 +1714,34 @@ if (clocks > DTL_TRP_MAX) { return 0; } - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE; if (old_clocks > clocks) { clocks = old_clocks; } dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT); dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); return 1; } static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dtl; - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT); dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT; - pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl); } static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dth; - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (param->dch_tref4k << DTH_TREF_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); } static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i) @@ -1758,7 +1758,7 @@ tref = param->dch_tref4k; } - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK; if ((value == 12) && (old_tref == param->dch_tref4k)) { tref = param->dch_tref4k; @@ -1767,7 +1767,7 @@ } dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT); dth |= (tref << DTH_TREF_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); return 1; } @@ -1798,12 +1798,12 @@ dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2); } #endif - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~dimm; if (value == 4) { dcl |= dimm; } - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); return 1; } @@ -1816,9 +1816,9 @@ return -1; } if (value != 2) { - dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_DimmEccEn; - pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); } return 1; } @@ -1830,7 +1830,7 @@ dimms = 0; for(index = 0; index < 8; index += 2) { u32 csbase; - csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2))); + csbase = pci_conf1_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2))); if (csbase & 1) { dimms += 1; } @@ -1842,10 +1842,10 @@ { u32 dth; - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT); dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); } static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param) @@ -1856,7 +1856,7 @@ int lat = 0, mtype; clocks = 0; - dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); + dtl = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_LOW); latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK; if (is_opteron(ctrl)) { @@ -1886,10 +1886,10 @@ die("Unknown Trwt\n"); } - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT); dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); return; } @@ -1903,10 +1903,10 @@ } else { clocks = 1; } - dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH); + dth = pci_conf1_read_config32(ctrl->f2, DRAM_TIMING_HIGH); dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT); dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT); - pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); + pci_conf1_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth); } @@ -1937,7 +1937,7 @@ die("Unknown rdpreamble for this nr of slots"); } - dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT); rdpreamble = param->rdpreamble[i]; @@ -1946,7 +1946,7 @@ } dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT; - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param) @@ -1957,7 +1957,7 @@ dimms = count_dimms(ctrl); - dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT); async_lat = 0; if (is_registered(ctrl)) { @@ -1984,18 +1984,18 @@ } } dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT); - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { u32 dch; /* AMD says to Hardcode this */ - dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT); dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT; dch |= DCH_DYN_IDLE_CTR_EN; - pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask) @@ -2103,22 +2103,22 @@ carry_over = (4*1024*1024) - hole_startk; for(ii=controllers - 1;ii>i;ii--) { - base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); + base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (ii << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); + limit = pci_conf1_read_config32(ctrl[0].f1, 0x44 + (ii << 3)); for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); - pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); + pci_conf1_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2)); + pci_conf1_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2)); } } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + limit = pci_conf1_read_config32(ctrl[0].f1, 0x44 + (i << 3)); for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); + pci_conf1_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2)); } dev = ctrl[i].f1; - base = pci_read_config32(dev, 0x40 + (i << 3)); + base = pci_conf1_read_config32(dev, 0x40 + (i << 3)); basek = (base & 0xffff0000) >> 2; if(basek == hole_startk) { //don't need set memhole here, because hole off set will be 0, overflow @@ -2126,7 +2126,7 @@ base &= 0x0000ffff; base |= (4*1024*1024)<<2; for(j = 0; j < controllers; j++) { - pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); + pci_conf1_write_config32(ctrl[j].f1, 0x40 + (i<<3), base); } } else { @@ -2136,7 +2136,7 @@ (((basek + carry_over) >> 6) & 0x0000ff00) + /* enable */ 1; - pci_write_config32(dev, 0xf0, hoist); + pci_conf1_write_config32(dev, 0xf0, hoist); } return carry_over; @@ -2160,7 +2160,7 @@ for(i=0; i<controllers; i++) { u32 base; unsigned base_k; - base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); + base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } @@ -2180,11 +2180,11 @@ for(i=0; i<controllers; i++) { u32 base, limit; unsigned base_k, limit_k; - base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3)); + base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i << 3)); if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { continue; } - limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3)); + limit = pci_conf1_read_config32(ctrl[0].f1, 0x44 + (i << 3)); base_k = (base & 0xffff0000) >> 2; limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; if ((base_k <= hole_startk) && (limit_k > hole_startk)) { @@ -2215,17 +2215,17 @@ u32 dch; if (!controller_present(ctrl + i)) continue; - dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) { dch |= DCH_MEMCLK_VALID; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch); } else { /* Disable dram receivers */ u32 dcl; - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); dcl |= DCL_DisInRcvrs; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); } } @@ -2239,31 +2239,31 @@ if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */ - dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); if (!(dch & DCH_MEMCLK_VALID)) { continue; } /* Toggle DisDqsHys to get it working */ - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); if (dcl & DCL_DimmEccEn) { u32 mnc; printk(BIOS_SPEW, "ECC enabled\n"); - mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG); + mnc = pci_conf1_read_config32(ctrl[i].f3, MCA_NB_CONFIG); mnc |= MNC_ECC_EN; if (dcl & DCL_128BitEn) { mnc |= MNC_CHIPKILL_EN; } - pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); + pci_conf1_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc); } dcl |= DCL_DisDqsHys; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); dcl &= ~DCL_DisDqsHys; dcl &= ~DCL_DLL_Disable; dcl &= ~DCL_D_DRV; dcl &= ~DCL_QFC_EN; dcl |= DCL_DramInit; - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); } for(i = 0; i < controllers; i++) { @@ -2271,7 +2271,7 @@ if (!controller_present(ctrl + i)) continue; /* Skip everything if I don't have any memory on this controller */ - dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); + dch = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH); if (!(dch & DCH_MEMCLK_VALID)) { continue; } @@ -2280,7 +2280,7 @@ int loops = 0; do { - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); loops += 1; if ((loops & 1023) == 0) { printk(BIOS_DEBUG, "."); @@ -2294,9 +2294,9 @@ if (!is_cpu_pre_c0()) { /* Wait until it is safe to touch memory */ dcl &= ~(DCL_MemClrStatus | DCL_DramEnable); - pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); + pci_conf1_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl); do { - dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); + dcl = pci_conf1_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW); } while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) ); }

1 0

r764 - in coreboot-v3: northbridge/amd/k8 southbridge/nvidia/mcp55
by svn＠coreboot.org 14 Aug '08

14 Aug '08

Author: rminnich Date: 2008-08-14 18:31:24 +0200 (Thu, 14 Aug 2008) New Revision: 764 Added: coreboot-v3/northbridge/amd/k8/common.c coreboot-v3/northbridge/amd/k8/cpu.c coreboot-v3/northbridge/amd/k8/domain.c coreboot-v3/northbridge/amd/k8/pci.c Removed: coreboot-v3/northbridge/amd/k8/northbridge.c Modified: coreboot-v3/northbridge/amd/k8/Makefile coreboot-v3/northbridge/amd/k8/coherent_ht.c coreboot-v3/northbridge/amd/k8/incoherent_ht.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.h Log: First cut at sanity in the northbridge. Break out functions so that there is some meaning to what is in what. northbridge.c is marked for deletion, so don't sit up waiting for it to come home. pci functions are in pci.c domain functions are in domain.c cpu functions are in cpu.c; cpu.c may move in the future to, say, someplace like cpu/amd/k8. common functions are in common.c These are still not set up quite right. I used svn copy to create the new files. Geode builds fine. Anybody want to guess why this happens on k8? It's not clear to me. /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c: At top level: /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:60: error: ?\226?\128?\152pci_conf1_read_config8?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:33: error: previous definition of ?\226?\128?\152pci_conf1_read_config8?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:66: error: ?\226?\128?\152pci_conf1_read_config16?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:34: error: previous definition of ?\226?\128?\152pci_conf1_read_config16?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:72: error: ?\226?\128?\152pci_conf1_read_config32?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:35: error: previous definition of ?\226?\128?\152pci_conf1_read_config32?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:78: error: ?\226?\128?\152pci_conf1_write_config8?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:36: error: previous definition of ?\226?\128?\152pci_conf1_write_config8?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:84: error: ?\226?\128?\152pci_conf1_write_config16?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:37: error: previous definition of ?\226?\128?\152pci_conf1_write_config16?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:90: error: ?\226?\128?\152pci_conf1_write_config32?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:38: error: previous definition of ?\226?\128?\152pci_conf1_write_config32?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:116: error: ?\226?\128?\152pci_conf1_find_on_bus?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:39: error: previous definition of ?\226?\128?\152pci_conf1_find_on_bus?\226?\128?\153 was here /home/rminnich/src/bios/coreboot-v3/arch/x86/pci_ops_conf1.c:151: error: ?\226?\128?\152pci_conf1_find_device?\226?\128?\153 redeclared as different kind of symbol include/device/pci_ops.h:40: error: previous definition of ?\226?\128?\152pci_conf1_find_device?\226?\128?\153 was here Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/northbridge/amd/k8/Makefile =================================================================== --- coreboot-v3/northbridge/amd/k8/Makefile 2008-08-14 16:16:07 UTC (rev 763) +++ coreboot-v3/northbridge/amd/k8/Makefile 2008-08-14 16:31:24 UTC (rev 764) @@ -23,6 +23,9 @@ # no stage2 sources yet. STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/k8/get_sblk_pci1234.c \ - $(src)/northbridge/amd/k8/northbridge.c \ + $(src)/northbridge/amd/k8/common.c \ + $(src)/northbridge/amd/k8/cpu.c \ + $(src)/northbridge/amd/k8/domain.c \ + $(src)/northbridge/amd/k8/pci.c endif Modified: coreboot-v3/northbridge/amd/k8/coherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-14 16:16:07 UTC (rev 763) +++ coreboot-v3/northbridge/amd/k8/coherent_ht.c 2008-08-14 16:31:24 UTC (rev 764) @@ -88,7 +88,6 @@ #include <device/hypertransport_def.h> #include <mc146818rtc.h> #include <lib.h> -#include "stage1.h" #define enable_bsp_routing() enable_routing(0) @@ -154,11 +153,11 @@ printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... "); - val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); + val=pci_conf1_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL); val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C | HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P | HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P; - pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); + pci_conf1_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val); printk(BIOS_SPEW, "done.\n"); @@ -171,9 +170,9 @@ u32 val; - val = pci_read_config32(NODE_HT(node), 0x68); + val = pci_conf1_read_config32(NODE_HT(node), 0x68); val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST); - pci_write_config32(NODE_HT(node), 0x68, val); + pci_conf1_write_config32(NODE_HT(node), 0x68, val); #endif } @@ -206,16 +205,16 @@ /* Enable routing table */ printk(BIOS_SPEW, "Enabling routing table for node %x", node); - val=pci_read_config32(NODE_HT(node), 0x6c); + val=pci_conf1_read_config32(NODE_HT(node), 0x6c); val &= ~((1<<1)|(1<<0)); - pci_write_config32(NODE_HT(node), 0x6c, val); + pci_conf1_write_config32(NODE_HT(node), 0x6c, val); printk(BIOS_SPEW, " done.\r\n"); } void fill_row(u8 node, u8 row, u32 value) { - pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); + pci_conf1_write_config32(NODE_HT(node), 0x40+(row<<2), value); } #if CONFIG_MAX_PHYSICAL_CPUS > 1 @@ -240,7 +239,7 @@ u32 get_row(u8 node, u8 row) { - return pci_read_config32(NODE_HT(node), 0x40+(row<<2)); + return pci_conf1_read_config32(NODE_HT(node), 0x40+(row<<2)); } int link_connection(u8 src, u8 dest) @@ -254,10 +253,10 @@ printk(BIOS_SPEW, "Renaming current temporary node to %x", node); - val=pci_read_config32(NODE_HT(7), 0x60); + val=pci_conf1_read_config32(NODE_HT(7), 0x60); val &= (~7); /* clear low bits. */ val |= node; /* new node */ - pci_write_config32(NODE_HT(7), 0x60, val); + pci_conf1_write_config32(NODE_HT(7), 0x60, val); printk(BIOS_SPEW, " done.\n"); } @@ -271,7 +270,7 @@ * established and actually working by reading the * remode node's vendor/device id */ - val = pci_read_config32(NODE_HT(dest),0); + val = pci_conf1_read_config32(NODE_HT(dest),0); if(val != 0x11001022) return 0; @@ -284,7 +283,7 @@ u16 freq_cap; u32 id; - freq_cap = pci_read_config16(dev, pos); + freq_cap = pci_conf1_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 @@ -296,7 +295,7 @@ } #endif - id = pci_read_config32(dev, 0); + id = pci_conf1_read_config32(dev, 0); /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { @@ -328,20 +327,20 @@ freq = log2(freq_cap1 & freq_cap2); /* See if I am changing the link freqency */ - old_freq = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ); + old_freq = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ); old_freq &= 0x0f; needs_reset |= old_freq != freq; - old_freq = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ); + old_freq = pci_conf1_read_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ); old_freq &= 0x0f; needs_reset |= old_freq != freq; /* Set the Calulcated link frequency */ - pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq); - pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq); + pci_conf1_write_config8(node1, link1 + PCI_HT_CAP_HOST_FREQ, freq); + pci_conf1_write_config8(node2, link2 + PCI_HT_CAP_HOST_FREQ, freq); /* Get the width capabilities */ - width_cap1 = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH); - width_cap2 = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH); + width_cap1 = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH); + width_cap2 = pci_conf1_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH); /* Calculate node1's input width */ ln_width1 = link_width_to_pow2[width_cap1 & 7]; @@ -359,23 +358,23 @@ width |= pow2_to_link_width[ln_width1] << 4; /* See if I am changing node1's width */ - old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1); + old_width = pci_conf1_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1); old_width &= 0x77; needs_reset |= old_width != width; /* Set node1's widths */ - pci_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width); + pci_conf1_write_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1, width); // * Calculate node2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); /* See if I am changing node2's width */ - old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1); + old_width = pci_conf1_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1); old_width &= 0x77; needs_reset |= old_width != width; /* Set node2's widths */ - pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width); + pci_conf1_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width); return needs_reset; } @@ -414,7 +413,7 @@ u8 regpos; u32 reg; regpos = 0x98 + 0x20 * linkn; - reg = pci_read_config32(NODE_HT(source), regpos); + reg = pci_conf1_read_config32(NODE_HT(source), regpos); if ((reg & 0x17) != 3) continue; /* it is not conherent or not connected*/ val |= 1<<(linkn+1); } @@ -519,8 +518,8 @@ u32 value; u8 reg; reg = pci_reg[i]; - value = pci_read_config32(NODE_MP(0), reg); - pci_write_config32(NODE_MP(7), reg, value); + value = pci_conf1_read_config32(NODE_MP(0), reg); + pci_conf1_write_config32(NODE_MP(7), reg, value); } printk(BIOS_SPEW, "done\r\n"); @@ -664,7 +663,7 @@ { printk(BIOS_SPEW, "Enabling UP settings\r\n"); #if CONFIG_LOGICAL_CPUS==1 - unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; + unsigned tmp = (pci_conf1_read_config32(NODE_MC(0), 0xe8) >> 12) & 3; if (tmp>0) return; #endif disable_probes(); @@ -713,7 +712,7 @@ verify_connection(7); /* We found 2 nodes so far */ - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /*get default link on node7 to node0*/ print_linkn("(1,0) link=", byte); setup_row_local(7,1); @@ -738,7 +737,7 @@ verify_connection(7); /* We found 2 nodes so far */ - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on node7 to node0*/ print_linkn("\t-->(1,0) link=", byte); setup_row_local(7,1); @@ -811,7 +810,7 @@ setup_temp_row(0,2); verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 0*/ print_linkn("(2,0) link=", byte); @@ -826,7 +825,7 @@ setup_temp_row(1,3); verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 1*/ print_linkn("(3,1) link=", byte); @@ -861,7 +860,7 @@ } #endif - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 2*/ print_linkn("(3,2) link=", byte); setup_remote_row_direct(3,2, byte); @@ -985,7 +984,7 @@ setup_temp_row(byte,byte+2); } verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /*get default link on 7 to 2*/ print_linkn("(4,2) link=", byte); @@ -1014,7 +1013,7 @@ } verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 3*/ print_linkn("(5,3) link=", byte); setup_row_local(7,5); @@ -1051,7 +1050,7 @@ } #endif - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ print_linkn("(5,4) link=", byte); setup_remote_row_direct(5,4, byte); @@ -1213,7 +1212,7 @@ setup_temp_row(byte,byte+2); } verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ print_linkn("(6,4) link=", byte); @@ -1276,7 +1275,7 @@ verify_connection(7); } - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ print_linkn("(6,5) link=", byte); setup_remote_row_direct(6, 5, byte); @@ -1294,7 +1293,7 @@ verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ print_linkn("(7,5) link=", byte); setup_row_local(7,7); @@ -1314,7 +1313,7 @@ verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 4*/ print_linkn("(7,4) link=", byte); setup_row_local(7,7); @@ -1339,7 +1338,7 @@ verify_connection(7); - val = pci_read_config32(NODE_HT(7), 0x6c); + val = pci_conf1_read_config32(NODE_HT(7), 0x6c); byte = (val>>2) & 0x3; /* get default link on 7 to 5*/ print_linkn("(7,5) link=", byte); setup_remote_row_direct(7, 5, byte); @@ -1523,7 +1522,7 @@ mask = 0x06; /* BigMPCap */ for (node=0; node<nodes; node++) { - mask &= pci_read_config32(NODE_MC(node), 0xe8); + mask &= pci_conf1_read_config32(NODE_MC(node), 0xe8); } switch(mask) { @@ -1583,7 +1582,7 @@ totalcpus = 0; for (node=0; node<nodes; node++) { - tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; + tmp = (pci_conf1_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ; totalcpus += (tmp + 1); } @@ -1627,19 +1626,19 @@ dev = NODE_HT(node); /* Set the Total CPU and Node count in the system */ - val = pci_read_config32(dev, 0x60); + val = pci_conf1_read_config32(dev, 0x60); val &= (~0x000F0070); #if CONFIG_LOGICAL_CPUS==1 val |= ((total_cpus-1)<<16)|((nodes-1)<<4); #else val |= ((nodes-1)<<16)|((nodes-1)<<4); #endif - pci_write_config32(dev, 0x60, val); + pci_conf1_write_config32(dev, 0x60, val); /* Only respond to real cpu pci configuration cycles * and optimize the HT settings */ - val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); + val=pci_conf1_read_config32(dev, HT_TRANSACTION_CONTROL); val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) | (HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) | (HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT)); @@ -1647,13 +1646,13 @@ (HTTC_BUF_REL_PRI_8 << HTTC_BUF_REL_PRI_SHIFT) | (3 << HTTC_MED_PRI_BYP_CNT_SHIFT) | (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); - pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); + pci_conf1_write_config32(dev, HT_TRANSACTION_CONTROL, val); #if CONFIG_K8_REV_F_SUPPORT == 0 if (rev_a0) { - pci_write_config32(dev, 0x94, 0); - pci_write_config32(dev, 0xb4, 0); - pci_write_config32(dev, 0xd4, 0); + pci_conf1_write_config32(dev, 0x94, 0); + pci_conf1_write_config32(dev, 0xb4, 0); + pci_conf1_write_config32(dev, 0xd4, 0); } #endif } @@ -1675,25 +1674,25 @@ /* Errata 66 * Limit the number of downstream posted requests to 1 */ - cmd = pci_read_config32(dev, 0x70); + cmd = pci_conf1_read_config32(dev, 0x70); if ((cmd & (3 << 0)) != 2) { cmd &= ~(3<<0); cmd |= (2<<0); - pci_write_config32(dev, 0x70, cmd ); + pci_conf1_write_config32(dev, 0x70, cmd ); needs_reset = 1; } - cmd = pci_read_config32(dev, 0x7c); + cmd = pci_conf1_read_config32(dev, 0x7c); if ((cmd & (3 << 4)) != 0) { cmd &= ~(3<<4); cmd |= (0<<4); - pci_write_config32(dev, 0x7c, cmd ); + pci_conf1_write_config32(dev, 0x7c, cmd ); needs_reset = 1; } /* Clock Power/Timing Low */ - cmd = pci_read_config32(dev, 0xd4); + cmd = pci_conf1_read_config32(dev, 0xd4); if (cmd != 0x000D0001) { cmd = 0x000D0001; - pci_write_config32(dev, 0xd4, cmd); + pci_conf1_write_config32(dev, 0xd4, cmd); needs_reset = 1; /* Needed? */ } @@ -1705,9 +1704,9 @@ * Clock Power/Timing Low */ cmd_ref = 0x04e20707; /* Registered */ - cmd = pci_read_config32(dev, 0xd4); + cmd = pci_conf1_read_config32(dev, 0xd4); if(cmd != cmd_ref) { - pci_write_config32(dev, 0xd4, cmd_ref ); + pci_conf1_write_config32(dev, 0xd4, cmd_ref ); needs_reset = 1; /* Needed? */ } } @@ -1726,13 +1725,13 @@ int link; f0_dev = NODE_HT(node); f3_dev = NODE_MC(node); - cmd_ref = cmd = pci_read_config32(f3_dev, 0xdc); + cmd_ref = cmd = pci_conf1_read_config32(f3_dev, 0xdc); for(link = 0; link < 3; link++) { u32 link_type; unsigned reg; /* This works on an Athlon64 because unimplemented links return 0 */ reg = 0x98 + (link * 0x20); - link_type = pci_read_config32(f0_dev, reg); + link_type = pci_conf1_read_config32(f0_dev, reg); /* Only handle coherent links */ if ((link_type & (LinkConnected | InitComplete|NonCoherent)) == (LinkConnected|InitComplete)) @@ -1742,7 +1741,7 @@ } } if (cmd != cmd_ref) { - pci_write_config32(f3_dev, 0xdc, cmd); + pci_conf1_write_config32(f3_dev, 0xdc, cmd); needs_reset = 1; } } @@ -1751,7 +1750,7 @@ inline unsigned get_nodes(void) { - return ((pci_read_config32(PCI_BDF(0, 0x18, 0), 0x60)>>4) & 7) + 1; + return ((pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), 0x60)>>4) & 7) + 1; } int optimize_link_coherent_ht(void) Copied: coreboot-v3/northbridge/amd/k8/common.c (from rev 757, coreboot-v3/northbridge/amd/k8/northbridge.c) =================================================================== --- coreboot-v3/northbridge/amd/k8/common.c (rev 0) +++ coreboot-v3/northbridge/amd/k8/common.c 2008-08-14 16:31:24 UTC (rev 764) @@ -0,0 +1,1360 @@ +/* + * K8 northbridge + * This file is part of the coreboot project. + * Copyright (C) 2004-2005 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Ollie Lo + * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +/* This should be done by Eric + 2004.12 yhlu add dual core support + 2005.01 yhlu add support move apic before pci_domain in MB Config.lb + 2005.02 yhlu add e0 memory hole support + 2005.11 yhlu add put sb ht chain on bus 0 +*/ + +#include <console.h> +#include <lib.h> +#include <string.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <device/hypertransport_def.h> +#include <device/hypertransport.h> +#include <mc146818rtc.h> +#include <lib.h> +#include <lapic.h> + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +#include <cpu/amd/model_fxx_rev.h> +#endif + +struct amdk8_sysconf sysconf; + +#define FX_DEVS 8 +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; + +#if 0 +static void debug_fx_devs(void) +{ + int i; + for(i = 0; i < FX_DEVS; i++) { + struct device * dev; + dev = __f0_dev[i]; + if (dev) { + printk(BIOS_DEBUG, "__f0_dev[%d]: %s bus: %p\n", + i, dev_path(dev), dev->bus); + } + dev = __f1_dev[i]; + if (dev) { + printk(BIOS_DEBUG, "__f1_dev[%d]: %s bus: %p\n", + i, dev_path(dev), dev->bus); + } + } +} +#endif + +static void get_fx_devs(void) +{ + int i; + if (__f1_dev[0]) { + return; + } + for(i = 0; i < FX_DEVS; i++) { + __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0)); + __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1)); + } + if (!__f1_dev[0]) { + die("Cannot find 0:0x18.1\n"); + } +} + +static u32 f1_read_config32(unsigned reg) +{ + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + get_fx_devs(); + for(i = 0; i < FX_DEVS; i++) { + struct device * dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static unsigned int amdk8_nodeid(struct device * dev) +{ + return (dev->path.pci.devfn >> 3) - 0x18; +} + +static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) +{ + + u32 link_type; + int i; + u32 busses, config_busses; + unsigned free_reg, config_reg; + unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain + unsigned max_bus; + unsigned min_bus; + unsigned max_devfn; + + dev->link[link].cap = 0x80 + (link *0x20); + do { + link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + } while(link_type & ConnectionPending); + if (!(link_type & LinkConnected)) { + return max; + } + do { + link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + } while(!(link_type & InitComplete)); + if (!(link_type & NonCoherent)) { + return max; + } + /* See if there is an available configuration space mapping + * register in function 1. + */ + free_reg = 0; + for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { + u32 config; + config = f1_read_config32(config_reg); + if (!free_reg && ((config & 3) == 0)) { + free_reg = config_reg; + continue; + } + if (((config & 3) == 3) && + (((config >> 4) & 7) == nodeid) && + (((config >> 8) & 3) == link)) { + break; + } + } + if (free_reg && (config_reg > 0xec)) { + config_reg = free_reg; + } + /* If we can't find an available configuration space mapping + * register skip this bus + */ + if (config_reg > 0xec) { + return max; + } + + /* Set up the primary, secondary and subordinate bus numbers. + * We have no idea how many busses are behind this bridge yet, + * so we set the subordinate bus number to 0xff for the moment. + */ +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + // first chain will on bus 0 + if((nodeid == 0) && (sblink==link)) { // actually max is 0 here + min_bus = max; + } + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 + // second chain will be on 0x40, third 0x80, forth 0xc0 + else { + min_bus = ((max>>6) + 1) * 0x40; + } + max = min_bus; + #else + //other ... + else { + min_bus = ++max; + } + #endif +#else + min_bus = ++max; +#endif + max_bus = 0xff; + + dev->link[link].secondary = min_bus; + dev->link[link].subordinate = max_bus; + + /* Read the existing primary/secondary/subordinate bus + * number configuration. + */ + busses = pci_read_config32(dev, dev->link[link].cap + 0x14); + config_busses = f1_read_config32(config_reg); + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagates by the bridge if it is + * not correctly configured + */ + busses &= 0xff000000; + busses |= (((unsigned int)(dev->bus->secondary) << 0) | + ((unsigned int)(dev->link[link].secondary) << 8) | + ((unsigned int)(dev->link[link].subordinate) << 16)); + pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + + config_busses &= 0x000fc88; + config_busses |= + (3 << 0) | /* rw enable, no device compare */ + (( nodeid & 7) << 4) | + (( link & 3 ) << 8) | + ((dev->link[link].secondary) << 16) | + ((dev->link[link].subordinate) << 24); + f1_write_config32(config_reg, config_busses); + + /* Now we can scan all of the subordinate busses i.e. the + * chain on the hypertranport link + */ + for(i=0;i<4;i++) { + ht_unitid_base[i] = 0x20; + } + + if (min_bus == 0) + max_devfn = (0x17<<3) | 7; + else + max_devfn = (0x1f<<3) | 7; + + max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + + /* We know the number of busses behind this bridge. Set the + * subordinate bus number to it's real value + */ + dev->link[link].subordinate = max; + busses = (busses & 0xff00ffff) | + ((unsigned int) (dev->link[link].subordinate) << 16); + pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + + config_busses = (config_busses & 0x00ffffff) | + (dev->link[link].subordinate << 24); + f1_write_config32(config_reg, config_busses); + + { + // config config_reg, and ht_unitid_base to update hcdn_reg; + int index; + unsigned temp = 0; + index = (config_reg-0xe0) >> 2; + for(i=0;i<4;i++) { + temp |= (ht_unitid_base[i] & 0xff) << (i*8); + } + + sysconf.hcdn_reg[index] = temp; + + } + + return max; +} + +static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max) +{ + unsigned nodeid; + unsigned link; + unsigned sblink = 0; + unsigned offset_unitid = 0; + nodeid = amdk8_nodeid(dev); + + if(nodeid==0) { + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + offset_unitid = 1; + #endif + // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2, + // but put 8151 on link0 + max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); +#endif + } + + for(link = 0; link < dev->links; link++) { +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + if( (nodeid == 0) && (sblink == link) ) continue; //already done +#endif + offset_unitid = 0; + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if((nodeid == 0) && (sblink == link)) + #endif + offset_unitid = 1; + #endif + + max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + } + + return max; +} + + +static int reg_useable(unsigned reg, + struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link; + int result; + res = 0; + for(nodeid = 0; !res && (nodeid < 8); nodeid++) { + struct device * dev; + dev = __f0_dev[nodeid]; + for(link = 0; !res && (link < 3); link++) { + res = probe_resource(dev, 0x100 + (reg | link)); + } + } + result = 2; + if (res) { + result = 0; + if ( (goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + + return result; +} + +static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + unsigned free_reg, reg; + resource = 0; + free_reg = 0; + for(reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; + } + if (reg > 0) { + resource = new_resource(dev, 0x100 + (reg | link)); + } + return resource; +} + +static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + unsigned free_reg, reg; + resource = 0; + free_reg = 0; + for(reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + if (reg > 0) { + resource = new_resource(dev, 0x100 + (reg | link)); + } + return resource; +} + +static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdk8_find_iopair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_IO_HOST_ALIGN); + resource->gran = log2(HT_IO_HOST_ALIGN); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_IO, IORESOURCE_IO); + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdk8_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); + } + + /* Initialize the memory constraints on the current bus */ + resource = amdk8_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); + } +} + +static void amdk8_read_resources(struct device * dev) +{ + unsigned nodeid, link; + nodeid = amdk8_nodeid(dev); + for(link = 0; link < dev->links; link++) { + if (dev->link[link].children) { + amdk8_link_read_bases(dev, nodeid, link); + } + } +} + +static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) +{ + resource_t rbase, rend; + unsigned reg, link; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if (resource->index < 0x100) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfc; + link = resource->index & 3; + + if (resource->flags & IORESOURCE_IO) { + u32 base, limit; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_IO, IORESOURCE_IO); + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x4); + base &= 0xfe000fcc; + base |= rbase & 0x01fff000; + base |= 3; + limit &= 0xfe000fc8; + limit |= rend & 0x01fff000; + limit |= (link & 3) << 4; + limit |= (nodeid & 7); + + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n", + __func__, dev_path(dev), link); + base |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + base |= PCI_IO_BASE_NO_ISA; + } + + f1_write_config32(reg + 0x4, limit); + f1_write_config32(reg, base); + } + else if (resource->flags & IORESOURCE_MEM) { + u32 base, limit; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)); + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x4); + base &= 0x000000f0; + base |= (rbase >> 8) & 0xffffff00; + base |= 3; + limit &= 0x00000048; + limit |= (rend >> 8) & 0xffffff00; + limit |= (link & 3) << 4; + limit |= (nodeid & 7); + f1_write_config32(reg + 0x4, limit); + f1_write_config32(reg, base); + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " <node %d link %d>", + nodeid, link); + report_resource_stored(dev, resource, buf); +} + +/** + * + * I tried to reuse the resource allocation code in amdk8_set_resource() + * but it is too diffcult to deal with the resource allocation magic. + */ +#if CONFIG_MULTIPLE_VGA_INIT == 1 +extern struct device * vga_pri; // the primary vga device, defined in device.c +#endif + +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) +{ + struct resource *resource; + unsigned link; + u32 base, limit; + unsigned reg; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = 0; link < dev->links; link++) { + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_INIT == 1 + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, + dev->link[link].secondary,dev->link[link].subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= dev->link[link].secondary ) && + (vga_pri->bus->secondary <= dev->link[link].subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == dev->links) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); + + /* allocate a temp resrouce for legacy VGA buffer */ + resource = amdk8_find_mempair(dev, nodeid, link); + if(!resource){ + printk(BIOS_DEBUG, "VGA: Can not find free mmio reg for legacy VGA buffer\n"); + return; + } + resource->base = 0xa0000; + resource->size = 0x20000; + + /* write the resource to the hardware */ + reg = resource->index & 0xfc; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x4); + base &= 0x000000f0; + base |= (resource->base >> 8) & 0xffffff00; + base |= 3; + limit &= 0x00000048; + limit |= (resource_end(resource) >> 8) & 0xffffff00; + limit |= (resource->index & 3) << 4; + limit |= (nodeid & 7); + f1_write_config32(reg + 0x4, limit); + f1_write_config32(reg, base); + + /* release the temp resource */ + resource->flags = 0; +} + +static void amdk8_set_resources(struct device * dev) +{ + unsigned nodeid, link; + int i; + + /* Find the nodeid */ + nodeid = amdk8_nodeid(dev); + + amdk8_create_vga_resource(dev, nodeid); + + /* Set each resource we have found */ + for(i = 0; i < dev->resources; i++) { + amdk8_set_resource(dev, &dev->resource[i], nodeid); + } + + for(link = 0; link < dev->links; link++) { + struct bus *bus; + bus = &dev->link[link]; + if (bus->children) { + assign_resources(bus); + } + } +} + +static void amdk8_enable_resources(struct device * dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static void mcf0_control_init(struct device *dev) +{ + printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. Nothing to do ..."); + + printk(BIOS_DEBUG, "done.\n"); +} + + +static void k8_pci_domain_read_resources(struct device * dev) +{ + struct resource *resource; + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, link; + struct device * dev; + nodeid = limit & 7; + link = (limit >> 4) & 3; + dev = __f0_dev[nodeid]; + if (dev) { + /* Reserve the resource */ + struct resource *resource; + resource = new_resource(dev, 0x100 + (reg | link)); + if (resource) { + resource->flags = 1; + } + } + } + } +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +#else + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_IO, IORESOURCE_IO); + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); +#endif +} + +static void k8_ram_resource(struct device * dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static u32 find_pci_tolm(struct bus *bus) +{ + struct resource *min; + u32 tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +#ifdef CONFIG_PCI_64BIT_PREF_MEM +#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) +#endif + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; + +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + + for (i = 0; i < 8; i++) { + u32 base; + u32 hole; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + + hole = pci_read_config32(__f1_dev[i], 0xf0); + if(hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if(mem_hole.node_id==-1) { + u32 limitk_pri = 0; + for(i=0; i<8; i++) { + u32 base, limit; + unsigned base_k, limit_k; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + + base_k = (base & 0xffff0000) >> 2; + if(limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = limitk_pri; + mem_hole.node_id = i; + break; //only one hole + } + + limit = f1_read_config32(0x44 + (i << 3)); + limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + limitk_pri = limit_k; + } + } + + return mem_hole; + +} +static void disable_hoist_memory(unsigned long hole_startk, int i) +{ + int ii; + struct device * dev; + u32 base, limit; + u32 hoist; + u32 hole_sizek; + + + //1. find which node has hole + //2. change limit in that node. + //3. change base and limit in later node + //4. clear that node f0 + + //if there is not mem hole enabled, we need to change it's base instead + + hole_sizek = (4*1024*1024) - hole_startk; + + for(ii=7;ii>i;ii--) { + + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + limit = f1_read_config32(0x44 + (ii << 3)); + f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); + f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); + dev = __f1_dev[i]; + hoist = pci_read_config32(dev, 0xf0); + if(hoist & 1) { + pci_write_config32(dev, 0xf0, 0); + } + else { + base = pci_read_config32(dev, 0x40 + (i << 3)); + f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2)); + } + +} + +static u32 hoist_memory(unsigned long hole_startk, int i) +{ + int ii; + u32 carry_over; + struct device * dev; + u32 base, limit; + u32 basek; + u32 hoist; + + carry_over = (4*1024*1024) - hole_startk; + + for(ii=7;ii>i;ii--) { + + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + limit = f1_read_config32(0x44 + (ii << 3)); + f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); + f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); + dev = __f1_dev[i]; + base = pci_read_config32(dev, 0x40 + (i << 3)); + basek = (base & 0xffff0000) >> 2; + if(basek == hole_startk) { + //don't need set memhole here, because hole off set will be 0, overflow + //so need to change base reg instead, new basek will be 4*1024*1024 + base &= 0x0000ffff; + base |= (4*1024*1024)<<2; + f1_write_config32(0x40 + (i<<3), base); + } + else + { + hoist = /* hole start address */ + ((hole_startk << 10) & 0xff000000) + + /* hole address to memory controller address */ + (((basek + carry_over) >> 6) & 0x0000ff00) + + /* enable */ + 1; + + pci_write_config32(dev, 0xf0, hoist); + } + + return carry_over; +} +#endif + +static void k8_pci_domain_set_resources(struct device * dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *resource, *last; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + unsigned reset_memhole = 1; +#endif + +#if 0 + /* Place the IO devices somewhere safe */ + io = find_resource(dev, 0); + io->base = DEVICE_IO_START; +#endif +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1); + mem2 = find_resource(dev, 2); + +#if 1 + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); +#endif + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + +#if 1 + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); +#endif + + last = &dev->resource[dev->resources]; + for(resource = &dev->resource[0]; resource < last; resource++) + { +#if 1 + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; +#endif + compute_allocate_resource(&dev->link[0], resource, + BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); + + resource->flags |= IORESOURCE_STORED; + report_resource_stored(dev, resource, ""); + + } +#endif + + + pci_tolm = find_pci_tolm(&dev->link[0]); + +#warning "FIXME handle interleaved nodes" + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + +#if 1 +#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole" + /* Round the mmio hold to 64M */ + mmio_basek &= ~((64*1024) - 1); +#endif + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek + * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + #ifndef CONFIG_K8_REV_F_SUPPORT + if (!is_cpu_pre_e0()) { + #endif + + mem_hole = get_hw_mem_hole_info(); + + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } + + //mmio_basek = 3*1024*1024; // for debug to meet boundary + + if(reset_memhole) { + if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + // We need to reset our Mem Hole, because We want more big HOLE than we already set + //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead + disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); + } + + #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some + u32 basek_pri; + for (i = 0; i < 8; i++) { + u32 base; + u32 basek; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + + basek = (base & 0xffff0000) >> 2; + if(mmio_basek == basek) { + mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node + break; + } + basek_pri = basek; + } + #endif + } + +#ifndef CONFIG_K8_REV_F_SUPPORT + } // is_cpu_pre_e0 +#endif + +#endif + + idx = 0x10; + for(i = 0; i < 8; i++) { + u32 base, limit; + unsigned basek, limitk, sizek; + base = f1_read_config32(0x40 + (i << 3)); + limit = f1_read_config32(0x44 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + basek = (base & 0xffff0000) >> 2; + limitk = ((limit + 0x00010000) & 0xffff0000) >> 2; + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + k8_ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + + printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + + /* See if I need to split the region to accomodate pci memory space */ + if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if(pre_sizek>0) { + k8_ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + } + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 + if(reset_memhole) + #ifndef CONFIG_K8_REV_F_SUPPORT + if(!is_cpu_pre_e0() ) + #endif + sizek += hoist_memory(mmio_basek,i); + #endif + + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + k8_ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; + } + assign_resources(&dev->link[0]); +} + +static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max) +{ + unsigned reg; + int i; + /* Unmap all of the HT chains */ + for(reg = 0xe0; reg <= 0xec; reg += 4) { + f1_write_config32(reg, 0); + } + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); + + /* Tune the hypertransport transaction for best performance. + * Including enabling relaxed ordering if it is safe. + */ + get_fx_devs(); + for(i = 0; i < FX_DEVS; i++) { + struct device * f0_dev; + f0_dev = __f0_dev[i]; + if (f0_dev && f0_dev->enabled) { + u32 httc; + httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); + httc &= ~HTTC_RSP_PASS_PW; + if (!dev->link[0].disable_relaxed_ordering) { + httc |= HTTC_RSP_PASS_PW; + } + printk(BIOS_SPEW, "%s passpw: %s\n", + dev_path(dev), + (!dev->link[0].disable_relaxed_ordering)? + "enabled":"disabled"); + pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); + } + } + return max; +} + + +static unsigned int cpu_bus_scan(struct device * dev, unsigned int max) +{ + struct bus *cpu_bus; + struct device * dev_mc; + int bsp_apicid; + int i,j; + unsigned nb_cfg_54; + unsigned siblings; + int e0_later_single_core; + int disable_siblings; + + nb_cfg_54 = 0; + sysconf.enabled_apic_ext_id = 0; + sysconf.lift_bsp_apicid = 0; + siblings = 0; + + /* Find the bootstrap processors apicid */ + bsp_apicid = lapicid(); + sysconf.apicid_offset = bsp_apicid; + + disable_siblings = !CONFIG_LOGICAL_CPUS; +#if CONFIG_LOGICAL_CPUS == 1 + get_option(&disable_siblings, "dual_core"); +#endif + + // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0) + // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core + + nb_cfg_54 = read_nb_cfg_54(); + + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!dev_mc) { + die("0:18.0 not found?"); + } + + sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1; + + + if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) + { + sysconf.enabled_apic_ext_id = 1; + if(bsp_apicid == 0) { + /* bsp apic id is not changed */ + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; + } else + { + sysconf.lift_bsp_apicid = 1; + } + + } + + /* Find which cpus are present */ + cpu_bus = &dev->link[0]; + for(i = 0; i < sysconf.nodes; i++) { + struct device * dev, *cpu; + struct device_path cpu_path; + + /* Find the cpu's pci device */ + dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + if (!dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int j; + struct device * dev_f0; + for(j = 0; j <= 3; j++) { + dev = pci_probe_dev(NULL, dev_mc->bus, + PCI_DEVFN(0x18 + i, j)); + } + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); + if(dev_f0) { + dev_f0->links = 3; + for(j=0;j<3;j++) { + dev_f0->link[j].link = j; + dev_f0->link[j].dev = dev_f0; + } + } + + } + + e0_later_single_core = 0; + if (dev && dev->enabled) { + j = pci_read_config32(dev, 0xe8); + j = (j >> 12) & 3; // dev is func 3 + printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(dev), j); + + if(nb_cfg_54) { + // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... + // ----> you can mixed single core e0 and dual core e0 at any sequence + // That is the typical case + + if(j == 0 ){ + #ifndef CONFIG_K8_REV_F_SUPPORT + e0_later_single_core = is_e0_later_in_bsp(i); // single core + #else + e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 + #endif + } else { + e0_later_single_core = 0; + } + if(e0_later_single_core) { + printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); + + j=1; + } + + if(siblings > j ) { + } + else { + siblings = j; + } + } else { + siblings = j; + } + } + + unsigned jj; + if(e0_later_single_core || disable_siblings) { + jj = 0; + } else + { + jj = siblings; + } +#if 0 + jj = 0; // if create cpu core1 path in amd_siblings by core0 +#endif + + for (j = 0; j <=jj; j++ ) { + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + + /* Enable the cpu if I have the processor */ + if (dev && dev->enabled) { + /* this is a CPU */ + struct device_id did; + did.type = DEVICE_ID_CPU; +#warning fill cpuid; right now it is zero + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path, &did); + } + if (cpu) { + cpu->enabled = 1; + } + } + + /* Disable the cpu if I don't have the processor */ + if (cpu && (!dev || !dev->enabled)) { + cpu->enabled = 0; + } + + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if(sysconf.enabled_apic_ext_id) { + if(sysconf.lift_bsp_apicid) { + cpu->path.apic.apic_id += sysconf.apicid_offset; + } else + { + if (cpu->path.apic.apic_id != 0) + cpu->path.apic.apic_id += sysconf.apicid_offset; + } + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + + } //j + } + return max; +} + +static void cpu_bus_init(struct device * dev) +{ + /* unclear if we need this any more. CPUs are in the device tree. */ + // initialize_cpus(&dev->link[0]); + //so what do we do? This is a first for v3. +} + +static void cpu_bus_noop(struct device * dev) +{ +} + +struct device_operations k8_ops = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x1100}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = amdk8_scan_chains, + .phase4_read_resources = amdk8_read_resources, + .phase4_set_resources = amdk8_set_resources, + .phase5_enable_resources = amdk8_enable_resources, + .phase6_init = mcf0_control_init, + .ops_pci = &pci_dev_ops_pci, +}; + + + +/* arguably, this should no longer be here. It was part of a nasty kludge because the CPUs + * were never really part of the device tree. The solution crafted in v2 was expedient but + * hardly comprehensible. It may be removed soon. + */ +/* the interesting question, of course: should we really be going for an *exact* match? Or a range? */ +struct device_operations k8cpu_ops = { + .id = {.type = DEVICE_ID_CPU, + {.cpu = {"Genuine AMD"}}}, + .constructor = default_device_constructor, + .phase3_scan = cpu_bus_scan, + .phase4_read_resources = cpu_bus_noop, + .phase4_set_resources = cpu_bus_noop, + .phase5_enable_resources = cpu_bus_noop, + .phase6_init = cpu_bus_init, + .ops_pci = &pci_dev_ops_pci, +}; + +struct device_operations k8apic_ops = { + .id = {.type = DEVICE_ID_APIC_CLUSTER, + {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x1100}}}, + .constructor = default_device_constructor, + .phase3_scan = k8_domain_scan_bus, + .phase4_read_resources = k8_pci_domain_read_resources, + .phase4_set_resources = k8_pci_domain_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .ops_pci = &pci_dev_ops_pci, + .ops_pci_bus = &pci_cf8_conf1, +}; Copied: coreboot-v3/northbridge/amd/k8/cpu.c (from rev 757, coreboot-v3/northbridge/amd/k8/northbridge.c) =================================================================== --- coreboot-v3/northbridge/amd/k8/cpu.c (rev 0) +++ coreboot-v3/northbridge/amd/k8/cpu.c 2008-08-14 16:31:24 UTC (rev 764) @@ -0,0 +1,237 @@ +/* + * K8 northbridge + * This file is part of the coreboot project. + * Copyright (C) 2004-2005 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Ollie Lo + * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +/* This should be done by Eric + 2004.12 yhlu add dual core support + 2005.01 yhlu add support move apic before pci_domain in MB Config.lb + 2005.02 yhlu add e0 memory hole support + 2005.11 yhlu add put sb ht chain on bus 0 +*/ + +#include <console.h> +#include <lib.h> +#include <string.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <device/hypertransport_def.h> +#include <device/hypertransport.h> +#include <mc146818rtc.h> +#include <lib.h> +#include <lapic.h> + +static unsigned int cpu_bus_scan(struct device * dev, unsigned int max) +{ + struct bus *cpu_bus; + struct device * dev_mc; + int bsp_apicid; + int i,j; + unsigned nb_cfg_54; + unsigned siblings; + int e0_later_single_core; + int disable_siblings; + + nb_cfg_54 = 0; + sysconf.enabled_apic_ext_id = 0; + sysconf.lift_bsp_apicid = 0; + siblings = 0; + + /* Find the bootstrap processors apicid */ + bsp_apicid = lapicid(); + sysconf.apicid_offset = bsp_apicid; + + disable_siblings = !CONFIG_LOGICAL_CPUS; +#if CONFIG_LOGICAL_CPUS == 1 + get_option(&disable_siblings, "dual_core"); +#endif + + // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0) + // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core + + nb_cfg_54 = read_nb_cfg_54(); + + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (!dev_mc) { + die("0:18.0 not found?"); + } + + sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1; + + + if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) + { + sysconf.enabled_apic_ext_id = 1; + if(bsp_apicid == 0) { + /* bsp apic id is not changed */ + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; + } else + { + sysconf.lift_bsp_apicid = 1; + } + + } + + /* Find which cpus are present */ + cpu_bus = &dev->link[0]; + for(i = 0; i < sysconf.nodes; i++) { + struct device * dev, *cpu; + struct device_path cpu_path; + + /* Find the cpu's pci device */ + dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + if (!dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int j; + struct device * dev_f0; + for(j = 0; j <= 3; j++) { + dev = pci_probe_dev(NULL, dev_mc->bus, + PCI_DEVFN(0x18 + i, j)); + } + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); + if(dev_f0) { + dev_f0->links = 3; + for(j=0;j<3;j++) { + dev_f0->link[j].link = j; + dev_f0->link[j].dev = dev_f0; + } + } + + } + + e0_later_single_core = 0; + if (dev && dev->enabled) { + j = pci_read_config32(dev, 0xe8); + j = (j >> 12) & 3; // dev is func 3 + printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(dev), j); + + if(nb_cfg_54) { + // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... + // ----> you can mixed single core e0 and dual core e0 at any sequence + // That is the typical case + + if(j == 0 ){ + #ifndef CONFIG_K8_REV_F_SUPPORT + e0_later_single_core = is_e0_later_in_bsp(i); // single core + #else + e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 + #endif + } else { + e0_later_single_core = 0; + } + if(e0_later_single_core) { + printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); + + j=1; + } + + if(siblings > j ) { + } + else { + siblings = j; + } + } else { + siblings = j; + } + } + + unsigned jj; + if(e0_later_single_core || disable_siblings) { + jj = 0; + } else + { + jj = siblings; + } +#if 0 + jj = 0; // if create cpu core1 path in amd_siblings by core0 +#endif + + for (j = 0; j <=jj; j++ ) { + + /* Build the cpu device path */ + cpu_path.type = DEVICE_PATH_APIC; + cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); + + /* See if I can find the cpu */ + cpu = find_dev_path(cpu_bus, &cpu_path); + + /* Enable the cpu if I have the processor */ + if (dev && dev->enabled) { + /* this is a CPU */ + struct device_id did; + did.type = DEVICE_ID_CPU; +#warning fill cpuid; right now it is zero + if (!cpu) { + cpu = alloc_dev(cpu_bus, &cpu_path, &did); + } + if (cpu) { + cpu->enabled = 1; + } + } + + /* Disable the cpu if I don't have the processor */ + if (cpu && (!dev || !dev->enabled)) { + cpu->enabled = 0; + } + + /* Report what I have done */ + if (cpu) { + cpu->path.apic.node_id = i; + cpu->path.apic.core_id = j; + if(sysconf.enabled_apic_ext_id) { + if(sysconf.lift_bsp_apicid) { + cpu->path.apic.apic_id += sysconf.apicid_offset; + } else + { + if (cpu->path.apic.apic_id != 0) + cpu->path.apic.apic_id += sysconf.apicid_offset; + } + } + printk(BIOS_DEBUG, "CPU: %s %s\n", + dev_path(cpu), cpu->enabled?"enabled":"disabled"); + } + + } //j + } + return max; +} + +static void cpu_bus_init(struct device * dev) +{ + /* unclear if we need this any more. CPUs are in the device tree. */ + // initialize_cpus(&dev->link[0]); + //so what do we do? This is a first for v3. +} + +static void cpu_bus_noop(struct device * dev) +{ +} Copied: coreboot-v3/northbridge/amd/k8/domain.c (from rev 757, coreboot-v3/northbridge/amd/k8/northbridge.c) =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c (rev 0) +++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-14 16:31:24 UTC (rev 764) @@ -0,0 +1,363 @@ +/* + * K8 northbridge + * This file is part of the coreboot project. + * Copyright (C) 2004-2005 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Ollie Lo + * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +/* This should be done by Eric + 2004.12 yhlu add dual core support + 2005.01 yhlu add support move apic before pci_domain in MB Config.lb + 2005.02 yhlu add e0 memory hole support + 2005.11 yhlu add put sb ht chain on bus 0 +*/ + +#include <console.h> +#include <lib.h> +#include <string.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <device/hypertransport_def.h> +#include <device/hypertransport.h> +#include <mc146818rtc.h> +#include <lib.h> +#include <lapic.h> + +static void k8_pci_domain_read_resources(struct device * dev) +{ + struct resource *resource; + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, link; + struct device * dev; + nodeid = limit & 7; + link = (limit >> 4) & 3; + dev = __f0_dev[nodeid]; + if (dev) { + /* Reserve the resource */ + struct resource *resource; + resource = new_resource(dev, 0x100 + (reg | link)); + if (resource) { + resource->flags = 1; + } + } + } + } +#if CONFIG_PCI_64BIT_PREF_MEM == 0 + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +#else + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_IO, IORESOURCE_IO); + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + compute_allocate_resource(&dev->link[0], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); +#endif +} + +static void k8_pci_domain_set_resources(struct device * dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + struct resource *io, *mem1, *mem2; + struct resource *resource, *last; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + int i, idx; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + unsigned reset_memhole = 1; +#endif + +#if 0 + /* Place the IO devices somewhere safe */ + io = find_resource(dev, 0); + io->base = DEVICE_IO_START; +#endif +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1); + mem2 = find_resource(dev, 2); + +#if 1 + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); +#endif + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first + */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + +#if 1 + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); +#endif + + last = &dev->resource[dev->resources]; + for(resource = &dev->resource[0]; resource < last; resource++) + { +#if 1 + resource->flags |= IORESOURCE_ASSIGNED; + resource->flags &= ~IORESOURCE_STORED; +#endif + compute_allocate_resource(&dev->link[0], resource, + BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); + + resource->flags |= IORESOURCE_STORED; + report_resource_stored(dev, resource, ""); + + } +#endif + + + pci_tolm = find_pci_tolm(&dev->link[0]); + +#warning "FIXME handle interleaved nodes" + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + +#if 1 +#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole" + /* Round the mmio hold to 64M */ + mmio_basek &= ~((64*1024) - 1); +#endif + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek + * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + #ifndef CONFIG_K8_REV_F_SUPPORT + if (!is_cpu_pre_e0()) { + #endif + + mem_hole = get_hw_mem_hole_info(); + + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } + + //mmio_basek = 3*1024*1024; // for debug to meet boundary + + if(reset_memhole) { + if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + // We need to reset our Mem Hole, because We want more big HOLE than we already set + //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead + disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); + } + + #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some + u32 basek_pri; + for (i = 0; i < 8; i++) { + u32 base; + u32 basek; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + + basek = (base & 0xffff0000) >> 2; + if(mmio_basek == basek) { + mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node + break; + } + basek_pri = basek; + } + #endif + } + +#ifndef CONFIG_K8_REV_F_SUPPORT + } // is_cpu_pre_e0 +#endif + +#endif + + idx = 0x10; + for(i = 0; i < 8; i++) { + u32 base, limit; + unsigned basek, limitk, sizek; + base = f1_read_config32(0x40 + (i << 3)); + limit = f1_read_config32(0x44 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + basek = (base & 0xffff0000) >> 2; + limitk = ((limit + 0x00010000) & 0xffff0000) >> 2; + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + k8_ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + + printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu + + /* See if I need to split the region to accomodate pci memory space */ + if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if(pre_sizek>0) { + k8_ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + } + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 + if(reset_memhole) + #ifndef CONFIG_K8_REV_F_SUPPORT + if(!is_cpu_pre_e0() ) + #endif + sizek += hoist_memory(mmio_basek,i); + #endif + + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + basek = 4*1024*1024; + sizek -= (4*1024*1024 - mmio_basek); + } + } + k8_ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; + } + assign_resources(&dev->link[0]); +} + +static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max) +{ + unsigned reg; + int i; + /* Unmap all of the HT chains */ + for(reg = 0xe0; reg <= 0xec; reg += 4) { + f1_write_config32(reg, 0); + } + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); + + /* Tune the hypertransport transaction for best performance. + * Including enabling relaxed ordering if it is safe. + */ + get_fx_devs(); + for(i = 0; i < FX_DEVS; i++) { + struct device * f0_dev; + f0_dev = __f0_dev[i]; + if (f0_dev && f0_dev->enabled) { + u32 httc; + httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); + httc &= ~HTTC_RSP_PASS_PW; + if (!dev->link[0].disable_relaxed_ordering) { + httc |= HTTC_RSP_PASS_PW; + } + printk(BIOS_SPEW, "%s passpw: %s\n", + dev_path(dev), + (!dev->link[0].disable_relaxed_ordering)? + "enabled":"disabled"); + pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); + } + } + return max; +} + +struct device_operations k8apic_ops = { + .id = {.type = DEVICE_ID_APIC_CLUSTER, + {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x1100}}}, + .constructor = default_device_constructor, + .phase3_scan = k8_domain_scan_bus, + .phase4_read_resources = k8_pci_domain_read_resources, + .phase4_set_resources = k8_pci_domain_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .ops_pci = &pci_dev_ops_pci, + .ops_pci_bus = &pci_cf8_conf1, +}; Modified: coreboot-v3/northbridge/amd/k8/incoherent_ht.c =================================================================== --- coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-14 16:16:07 UTC (rev 763) +++ coreboot-v3/northbridge/amd/k8/incoherent_ht.c 2008-08-14 16:31:24 UTC (rev 764) @@ -48,7 +48,7 @@ u8 pos; u8 hdr_type; - hdr_type = pci_read_config8(bdf, PCI_HEADER_TYPE); + hdr_type = pci_conf1_read_config8(bdf, PCI_HEADER_TYPE); pos = 0; hdr_type &= 0x7f; @@ -57,21 +57,21 @@ pos = PCI_CAPABILITY_LIST; } if (pos > PCI_CAP_LIST_NEXT) { - pos = pci_read_config8(bdf, pos); + pos = pci_conf1_read_config8(bdf, pos); } while(pos != 0) { /* loop through the linked list */ u8 cap; - cap = pci_read_config8(bdf, pos + PCI_CAP_LIST_ID); + cap = pci_conf1_read_config8(bdf, pos + PCI_CAP_LIST_ID); if (cap == PCI_CAP_ID_HT) { u16 flags; - flags = pci_read_config16(bdf, pos + PCI_CAP_FLAGS); + flags = pci_conf1_read_config16(bdf, pos + PCI_CAP_FLAGS); if ((flags >> 13) == val) { /* Entry is a slave or host , success... */ break; } } - pos = pci_read_config8(bdf, pos + PCI_CAP_LIST_NEXT); + pos = pci_conf1_read_config8(bdf, pos + PCI_CAP_LIST_NEXT); } return pos; } @@ -101,7 +101,7 @@ /* Check if is already collapsed */ if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { bdf = PCI_BDF(bus, 0, 0); - id = pci_read_config32(bdf, PCI_VENDOR_ID); + id = pci_conf1_read_config32(bdf, PCI_VENDOR_ID); if ( ! ( (id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000) ) ) { return; @@ -116,7 +116,7 @@ u8 pos; u16 flags; - id = pci_read_config32(bdf, PCI_VENDOR_ID); + id = pci_conf1_read_config32(bdf, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { continue; @@ -128,9 +128,9 @@ } /* Clear the unitid */ - flags = pci_read_config16(bdf, pos + PCI_CAP_FLAGS); + flags = pci_conf1_read_config16(bdf, pos + PCI_CAP_FLAGS); flags &= ~0x1f; - pci_write_config16(bdf, pos + PCI_CAP_FLAGS, flags); + pci_conf1_write_config16(bdf, pos + PCI_CAP_FLAGS, flags); } } @@ -140,10 +140,10 @@ u16 freq_cap; u32 id; - freq_cap = pci_read_config16(bdf, pos); + freq_cap = pci_conf1_read_config16(bdf, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ - id = pci_read_config32(bdf, 0); + id = pci_conf1_read_config32(bdf, 0); /* AMD 8131 Errata 48 */ if (id == (PCI_VENDOR_ID_AMD | (PCI_DEVICE_ID_AMD_8131_PCIX << 16))) { @@ -174,11 +174,11 @@ } static u8 ht_read_width_cap(u32 bdf, u8 pos) { - u8 width_cap = pci_read_config8(bdf, pos); + u8 width_cap = pci_conf1_read_config8(bdf, pos); u32 id; - id = pci_read_config32(bdf, 0); + id = pci_conf1_read_config32(bdf, 0); /* netlogic micro cap doesn't support 16 bit yet */ if (id == (0x184e | (0x0001 << 16))) { @@ -239,16 +239,16 @@ freq = log2(freq_cap1 & freq_cap2); /* See if I am changing the link freqency */ - old_freq = pci_read_config8(bdf1, pos1 + LINK_FREQ(offs1)); + old_freq = pci_conf1_read_config8(bdf1, pos1 + LINK_FREQ(offs1)); old_freq &= 0x0f; needs_reset |= old_freq != freq; - old_freq = pci_read_config8(bdf2, pos2 + LINK_FREQ(offs2)); + old_freq = pci_conf1_read_config8(bdf2, pos2 + LINK_FREQ(offs2)); old_freq &= 0x0f; needs_reset |= old_freq != freq; /* Set the Calulcated link frequency */ - pci_write_config8(bdf1, pos1 + LINK_FREQ(offs1), freq); - pci_write_config8(bdf2, pos2 + LINK_FREQ(offs2), freq); + pci_conf1_write_config8(bdf1, pos1 + LINK_FREQ(offs1), freq); + pci_conf1_write_config8(bdf2, pos2 + LINK_FREQ(offs2), freq); /* Get the width capabilities */ width_cap1 = ht_read_width_cap(bdf1, pos1 + LINK_WIDTH(offs1)); @@ -270,23 +270,23 @@ width |= pow2_to_link_width[ln_width1] << 4; /* See if I am changing dev1's width */ - old_width = pci_read_config8(bdf1, pos1 + LINK_WIDTH(offs1) + 1); + old_width = pci_conf1_read_config8(bdf1, pos1 + LINK_WIDTH(offs1) + 1); old_width &= 0x77; needs_reset |= old_width != width; /* Set dev1's widths */ - pci_write_config8(bdf1, pos1 + LINK_WIDTH(offs1) + 1, width); + pci_conf1_write_config8(bdf1, pos1 + LINK_WIDTH(offs1) + 1, width); /* Calculate dev2's width */ width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); /* See if I am changing dev2's width */ - old_width = pci_read_config8(bdf2, pos2 + LINK_WIDTH(offs2) + 1); + old_width = pci_conf1_read_config8(bdf2, pos2 + LINK_WIDTH(offs2) + 1); old_width &= 0x77; needs_reset |= old_width != width; /* Set dev2's widths */ - pci_write_config8(bdf2, pos2 + LINK_WIDTH(offs2) + 1, width); + pci_conf1_write_config8(bdf2, pos2 + LINK_WIDTH(offs2) + 1, width); return needs_reset; } @@ -327,8 +327,8 @@ u32 bdf; u16 cr; bdf = PCI_BDF((bus & 0xff), ((devfn>>3) & 0x1f), (devfn & 0x7)); - hdr_type = pci_read_config8(bdf, PCI_HEADER_TYPE); - class = pci_read_config16(bdf, PCI_CLASS_DEVICE); + hdr_type = pci_conf1_read_config8(bdf, PCI_HEADER_TYPE); + class = pci_conf1_read_config16(bdf, PCI_CLASS_DEVICE); switch(hdr_type & 0x7f) { /* header type */ case PCI_HEADER_TYPE_BRIDGE: @@ -336,18 +336,18 @@ /* set the bus range dev */ /* Clear all status bits and turn off memory, I/O and master enables. */ - cr = pci_read_config16(bdf, PCI_COMMAND); - pci_write_config16(bdf, PCI_COMMAND, 0x0000); - pci_write_config16(bdf, PCI_STATUS, 0xffff); + cr = pci_conf1_read_config16(bdf, PCI_COMMAND); + pci_conf1_write_config16(bdf, PCI_COMMAND, 0x0000); + pci_conf1_write_config16(bdf, PCI_STATUS, 0xffff); - buses = pci_read_config32(bdf, PCI_PRIMARY_BUS); + buses = pci_conf1_read_config32(bdf, PCI_PRIMARY_BUS); buses &= 0xff000000; new_bus++; buses |= (((unsigned int) (bus & 0xff) << 0) | ((unsigned int) (new_bus & 0xff) << 8) | ((unsigned int) max_bus << 16)); - pci_write_config32(bdf, PCI_PRIMARY_BUS, buses); + pci_conf1_write_config32(bdf, PCI_PRIMARY_BUS, buses); /* here we need to figure out if dev is a ht bridge if it is ht bridge, we need to call ht_setup_chainx at first @@ -369,9 +369,9 @@ buses = (buses & 0xff00ffff) | ((unsigned int) (new_bus & 0xff) << 16); - pci_write_config32(bdf, PCI_PRIMARY_BUS, buses); + pci_conf1_write_config32(bdf, PCI_PRIMARY_BUS, buses); - pci_write_config16(bdf, PCI_COMMAND, cr); + pci_conf1_write_config16(bdf, PCI_COMMAND, cr); break; default: @@ -425,7 +425,7 @@ /* Wait until the link initialization is complete */ do { - ctrl = pci_read_config16(bdf, upos + LINK_CTRL(uoffs)); + ctrl = pci_conf1_read_config16(bdf, upos + LINK_CTRL(uoffs)); /* Is this the end of the hypertransport chain? */ if (ctrl & (1 << 6)) { goto end_of_chain; @@ -440,8 +440,8 @@ * if its transient */ ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc - pci_write_config16(bdf, upos + LINK_CTRL(uoffs), ctrl); - ctrl = pci_read_config16(bdf, upos + LINK_CTRL(uoffs)); + pci_conf1_write_config16(bdf, upos + LINK_CTRL(uoffs), ctrl); + ctrl = pci_conf1_read_config16(bdf, upos + LINK_CTRL(uoffs)); if (ctrl & ((1 << 4) | (1 << 8))) { printk(BIOS_ERR, "Detected error on Hypertransport Link\n"); break; @@ -452,7 +452,7 @@ u32 abdf = PCI_BDF(bus, 0, 0); last_unitid = next_unitid; - id = pci_read_config32(abdf, PCI_VENDOR_ID); + id = pci_conf1_read_config32(abdf, PCI_VENDOR_ID); /* If the chain is enumerated quit */ if ( (id == 0xffffffff) || (id == 0x00000000) || @@ -487,10 +487,10 @@ } #endif /* Update the Unitid of the current device */ - flags = pci_read_config16(abdf, pos + PCI_CAP_FLAGS); + flags = pci_conf1_read_config16(abdf, pos + PCI_CAP_FLAGS); flags &= ~0x1f; /* mask out the base Unit ID */ flags |= next_unitid & 0x1f; - pci_write_config16(abdf, pos + PCI_CAP_FLAGS, flags); + pci_conf1_write_config16(abdf, pos + PCI_CAP_FLAGS, flags); /* Compute the number of unitids consumed */ count = (flags >> 5) & 0x1f; @@ -504,7 +504,7 @@ * by reading which direction our last write to PCI_CAP_FLAGS * came from. */ - flags = pci_read_config16(abdf, pos + PCI_CAP_FLAGS); + flags = pci_conf1_read_config16(abdf, pos + PCI_CAP_FLAGS); offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS; /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */ @@ -533,10 +533,10 @@ if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { u16 flags; int i; - flags = pci_read_config16(PCI_BDF(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); + flags = pci_conf1_read_config16(PCI_BDF(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; - pci_write_config16(PCI_BDF(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); + pci_conf1_write_config16(PCI_BDF(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); // Here need to change the dev in the array for(i=0;i<sysinfo->link_pair_num;i++) @@ -585,17 +585,17 @@ u8 link_type; /* This works on an Athlon64 because unimplemented links return 0 */ - dword = pci_read_config32(PCI_BDF(0,0x18+node,0), 0x98 + (linkn * 0x20)); + dword = pci_conf1_read_config32(PCI_BDF(0,0x18+node,0), 0x98 + (linkn * 0x20)); link_type = dword & 0xff; if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ - dword_old = dword = pci_read_config32(PCI_BDF(0,0x18+node,3), 0xdc); + dword_old = dword = pci_conf1_read_config32(PCI_BDF(0,0x18+node,3), 0xdc); dword &= ~( 0xff<<(linkn *8) ); dword |= val << (linkn *8); if (dword != dword_old) { - pci_write_config32(PCI_BDF(0,0x18+node,3), 0xdc, dword); + pci_conf1_write_config32(PCI_BDF(0,0x18+node,3), 0xdc, dword); return 1; } } @@ -624,13 +624,13 @@ devn = CONFIG_HT_CHAIN_UNITID_BASE; #endif - reg = pci_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); + reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); nodeid = ((reg & 0xf0)>>4); // nodeid linkn = ((reg & 0xf00)>>8); // link n busn = (reg & 0xff0000)>>16; //busn - reg = pci_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted + reg = pci_conf1_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) { val = 0x25; } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) { @@ -656,15 +656,15 @@ /* This works on an Athlon64 because unimplemented links return 0 */ regpos = 0x98 + (linkn * 0x20); bdf = PCI_BDF(0,0x18+node,0); - dword = pci_read_config32(bdf, regpos); + dword = pci_conf1_read_config32(bdf, regpos); link_type = dword & 0xff; if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/ regpos = 0x90 + (linkn * 0x20); - dword = pci_read_config32(bdf, regpos ); + dword = pci_conf1_read_config32(bdf, regpos ); if (dword != val) { - pci_write_config32(bdf, regpos, val); + pci_conf1_write_config32(bdf, regpos, val); return 1; } } @@ -685,7 +685,7 @@ u8 busn; unsigned devn; - reg = pci_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); + reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); if((reg & 3) != 3) continue; // not enabled nodeid = ((reg & 0xf0)>>4); // nodeid @@ -693,7 +693,7 @@ busn = (reg & 0xff0000)>>16; //busn for(devn = 0; devn < 0x20; devn++) { - reg = pci_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); //1? + reg = pci_conf1_read_config32( PCI_BDF(busn, devn, 0), PCI_VENDOR_ID); //1? if ( (reg & 0xffff) == vendorid ) { reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val); break; @@ -728,17 +728,17 @@ unsigned bus; unsigned offset_unitid = 0; - reg = pci_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); + reg = pci_conf1_read_config32(PCI_BDF(0,0x18,1), 0xe0 + i * 4); //We need setup 0x94, 0xb4, and 0xd4 according to the reg devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19 regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4; busn = (reg & 0xff0000)>>16; - dword = pci_read_config32( PCI_BDF(0, devpos, 0), regpos) ; + dword = pci_conf1_read_config32( PCI_BDF(0, devpos, 0), regpos) ; dword &= ~(0xffff<<8); dword |= (reg & 0xffff0000)>>8; - pci_write_config32( PCI_BDF(0, devpos,0), regpos , dword); + pci_conf1_write_config32( PCI_BDF(0, devpos,0), regpos , dword); #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) @@ -782,34 +782,34 @@ nodes = get_nodes(); /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_BDF(0, 0x18, 0), 0x64); + reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 0), 0x64); /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */ print_linkn_in("SBLink=", ((reg>>8) & 3) ); sysinfo->sblk = (reg>>8) & 3; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24); - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xe0, tempreg); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xe0, tempreg); next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ #if CONFIG_K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC4, tempreg); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xC4, tempreg); tempreg = 3 | ( 3<<4) | (0<<12); //base - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC0, tempreg); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xC0, tempreg); next_io_base = 0x3+0x1; #endif /* clean others */ for(ht_c_num=1;ht_c_num<4; ht_c_num++) { - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); #if CONFIG_K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0); - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0); #endif } @@ -820,13 +820,13 @@ for(linkn = 0; linkn<3; linkn++) { unsigned regpos; regpos = 0x98 + 0x20 * linkn; - reg = pci_read_config32(bdf, regpos); + reg = pci_conf1_read_config32(bdf, regpos); if ((reg & 0x17) != 7) continue; /* it is not non conherent or not connected*/ print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf)); tempreg = 3 | (nodeid <<4) | (linkn<<8); /*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */ for(ht_c_num=0;ht_c_num<4; ht_c_num++) { - reg = pci_read_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4); + reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4); if(((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/ break; } @@ -836,15 +836,15 @@ if((reg & 0xf) == 3) continue; /*SbLink so don't touch it */ print_linkn_in("\tbusn=", next_busn); tempreg |= (next_busn<<16)|((next_busn+0x3f)<<24); - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); next_busn+=0x3f+1; #if CONFIG_K8_ALLOCATE_IO_RANGE == 1 /* io range allocation */ tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ? - pci_write_config32(PCI_BDF(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); + pci_conf1_write_config32(PCI_BDF(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg); next_io_base += 0x3+0x1; #endif @@ -859,8 +859,8 @@ for(i = 0; i< 4; i++) { unsigned regpos; regpos = 0xe0 + i * 4; - reg = pci_read_config32(PCI_BDF(0, 0x18, 1), regpos); - pci_write_config32(dev, regpos, reg); + reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 1), regpos); + pci_conf1_write_config32(dev, regpos, reg); } #if CONFIG_K8_ALLOCATE_IO_RANGE == 1 @@ -868,14 +868,14 @@ for(i = 0; i< 4; i++) { unsigned regpos; regpos = 0xc4 + i * 8; - reg = pci_read_config32(PCI_BDF(0, 0x18, 1), regpos); - pci_write_config32(dev, regpos, reg); + reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 1), regpos); + pci_conf1_write_config32(dev, regpos, reg); } for(i = 0; i< 4; i++) { unsigned regpos; regpos = 0xc0 + i * 8; - reg = pci_read_config32(PCI_BDF(0, 0x18, 1), regpos); - pci_write_config32(dev, regpos, reg); + reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 1), regpos); + pci_conf1_write_config32(dev, regpos, reg); } #endif } @@ -883,7 +883,7 @@ /* recount ht_c_num*/ u8 i=0; for(ht_c_num=0;ht_c_num<4; ht_c_num++) { - reg = pci_read_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4); + reg = pci_conf1_read_config32(PCI_BDF(0, 0x18, 1), 0xe0 + ht_c_num * 4); if(((reg & 0xf) != 0x0)) { i++; } Deleted: coreboot-v3/northbridge/amd/k8/northbridge.c =================================================================== --- coreboot-v3/northbridge/amd/k8/northbridge.c 2008-08-14 16:16:07 UTC (rev 763) +++ coreboot-v3/northbridge/amd/k8/northbridge.c 2008-08-14 16:31:24 UTC (rev 764) @@ -1,1360 +0,0 @@ -/* - * K8 northbridge - * This file is part of the coreboot project. - * Copyright (C) 2004-2005 Linux Networx - * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) - * Copyright (C) 2005-7 YingHai Lu - * Copyright (C) 2005 Ollie Lo - * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> - * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ -/* This should be done by Eric - 2004.12 yhlu add dual core support - 2005.01 yhlu add support move apic before pci_domain in MB Config.lb - 2005.02 yhlu add e0 memory hole support - 2005.11 yhlu add put sb ht chain on bus 0 -*/ - -#include <console.h> -#include <lib.h> -#include <string.h> -#include <mtrr.h> -#include <macros.h> -#include <spd.h> -#include <cpu.h> -#include <msr.h> -#include <amd/k8/k8.h> -#include <amd/k8/sysconf.h> -#include <device/pci.h> -#include <device/hypertransport_def.h> -#include <device/hypertransport.h> -#include <mc146818rtc.h> -#include <lib.h> -#include <lapic.h> - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -#include <cpu/amd/model_fxx_rev.h> -#endif - -struct amdk8_sysconf sysconf; - -#define FX_DEVS 8 -static struct device * __f0_dev[FX_DEVS]; -static struct device * __f1_dev[FX_DEVS]; - -#if 0 -static void debug_fx_devs(void) -{ - int i; - for(i = 0; i < FX_DEVS; i++) { - struct device * dev; - dev = __f0_dev[i]; - if (dev) { - printk(BIOS_DEBUG, "__f0_dev[%d]: %s bus: %p\n", - i, dev_path(dev), dev->bus); - } - dev = __f1_dev[i]; - if (dev) { - printk(BIOS_DEBUG, "__f1_dev[%d]: %s bus: %p\n", - i, dev_path(dev), dev->bus); - } - } -} -#endif - -static void get_fx_devs(void) -{ - int i; - if (__f1_dev[0]) { - return; - } - for(i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0)); - __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1)); - } - if (!__f1_dev[0]) { - die("Cannot find 0:0x18.1\n"); - } -} - -static u32 f1_read_config32(unsigned reg) -{ - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned reg, u32 value) -{ - int i; - get_fx_devs(); - for(i = 0; i < FX_DEVS; i++) { - struct device * dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -static unsigned int amdk8_nodeid(struct device * dev) -{ - return (dev->path.pci.devfn >> 3) - 0x18; -} - -static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) -{ - - u32 link_type; - int i; - u32 busses, config_busses; - unsigned free_reg, config_reg; - unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain - unsigned max_bus; - unsigned min_bus; - unsigned max_devfn; - - dev->link[link].cap = 0x80 + (link *0x20); - do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); - } while(link_type & ConnectionPending); - if (!(link_type & LinkConnected)) { - return max; - } - do { - link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); - } while(!(link_type & InitComplete)); - if (!(link_type & NonCoherent)) { - return max; - } - /* See if there is an available configuration space mapping - * register in function 1. - */ - free_reg = 0; - for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { - u32 config; - config = f1_read_config32(config_reg); - if (!free_reg && ((config & 3) == 0)) { - free_reg = config_reg; - continue; - } - if (((config & 3) == 3) && - (((config >> 4) & 7) == nodeid) && - (((config >> 8) & 3) == link)) { - break; - } - } - if (free_reg && (config_reg > 0xec)) { - config_reg = free_reg; - } - /* If we can't find an available configuration space mapping - * register skip this bus - */ - if (config_reg > 0xec) { - return max; - } - - /* Set up the primary, secondary and subordinate bus numbers. - * We have no idea how many busses are behind this bridge yet, - * so we set the subordinate bus number to 0xff for the moment. - */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if((nodeid == 0) && (sblink==link)) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif -#else - min_bus = ++max; -#endif - max_bus = 0xff; - - dev->link[link].secondary = min_bus; - dev->link[link].subordinate = max_bus; - - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, dev->link[link].cap + 0x14); - config_busses = f1_read_config32(config_reg); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xff000000; - busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(dev->link[link].secondary) << 8) | - ((unsigned int)(dev->link[link].subordinate) << 16)); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); - - config_busses &= 0x000fc88; - config_busses |= - (3 << 0) | /* rw enable, no device compare */ - (( nodeid & 7) << 4) | - (( link & 3 ) << 8) | - ((dev->link[link].secondary) << 16) | - ((dev->link[link].subordinate) << 24); - f1_write_config32(config_reg, config_busses); - - /* Now we can scan all of the subordinate busses i.e. the - * chain on the hypertranport link - */ - for(i=0;i<4;i++) { - ht_unitid_base[i] = 0x20; - } - - if (min_bus == 0) - max_devfn = (0x17<<3) | 7; - else - max_devfn = (0x1f<<3) | 7; - - max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); - - /* We know the number of busses behind this bridge. Set the - * subordinate bus number to it's real value - */ - dev->link[link].subordinate = max; - busses = (busses & 0xff00ffff) | - ((unsigned int) (dev->link[link].subordinate) << 16); - pci_write_config32(dev, dev->link[link].cap + 0x14, busses); - - config_busses = (config_busses & 0x00ffffff) | - (dev->link[link].subordinate << 24); - f1_write_config32(config_reg, config_busses); - - { - // config config_reg, and ht_unitid_base to update hcdn_reg; - int index; - unsigned temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } - - sysconf.hcdn_reg[index] = temp; - - } - - return max; -} - -static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max) -{ - unsigned nodeid; - unsigned link; - unsigned sblink = 0; - unsigned offset_unitid = 0; - nodeid = amdk8_nodeid(dev); - - if(nodeid==0) { - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - offset_unitid = 1; - #endif - // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2, - // but put 8151 on link0 - max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); -#endif - } - - for(link = 0; link < dev->links; link++) { -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - if( (nodeid == 0) && (sblink == link) ) continue; //already done -#endif - offset_unitid = 0; - #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) - #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 - if((nodeid == 0) && (sblink == link)) - #endif - offset_unitid = 1; - #endif - - max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); - } - - return max; -} - - -static int reg_useable(unsigned reg, - struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) -{ - struct resource *res; - unsigned nodeid, link; - int result; - res = 0; - for(nodeid = 0; !res && (nodeid < 8); nodeid++) { - struct device * dev; - dev = __f0_dev[nodeid]; - for(link = 0; !res && (link < 3); link++) { - res = probe_resource(dev, 0x100 + (reg | link)); - } - } - result = 2; - if (res) { - result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - - return result; -} - -static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) -{ - struct resource *resource; - unsigned free_reg, reg; - resource = 0; - free_reg = 0; - for(reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xd8) { - reg = free_reg; - } - if (reg > 0) { - resource = new_resource(dev, 0x100 + (reg | link)); - } - return resource; -} - -static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) -{ - struct resource *resource; - unsigned free_reg, reg; - resource = 0; - free_reg = 0; - for(reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } - if (reg > 0) { - resource = new_resource(dev, 0x100 + (reg | link)); - } - return resource; -} - -static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdk8_find_iopair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_IO_HOST_ALIGN); - resource->gran = log2(HT_IO_HOST_ALIGN); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdk8_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); - } - - /* Initialize the memory constraints on the current bus */ - resource = amdk8_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); - } -} - -static void amdk8_read_resources(struct device * dev) -{ - unsigned nodeid, link; - nodeid = amdk8_nodeid(dev); - for(link = 0; link < dev->links; link++) { - if (dev->link[link].children) { - amdk8_link_read_bases(dev, nodeid, link); - } - } -} - -static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) -{ - resource_t rbase, rend; - unsigned reg, link; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if (resource->index < 0x100) { - return; - } - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfc; - link = resource->index & 3; - - if (resource->flags & IORESOURCE_IO) { - u32 base, limit; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_IO, IORESOURCE_IO); - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x4); - base &= 0xfe000fcc; - base |= rbase & 0x01fff000; - base |= 3; - limit &= 0xfe000fc8; - limit |= rend & 0x01fff000; - limit |= (link & 3) << 4; - limit |= (nodeid & 7); - - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n", - __func__, dev_path(dev), link); - base |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - base |= PCI_IO_BASE_NO_ISA; - } - - f1_write_config32(reg + 0x4, limit); - f1_write_config32(reg, base); - } - else if (resource->flags & IORESOURCE_MEM) { - u32 base, limit; - compute_allocate_resource(&dev->link[link], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)); - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x4); - base &= 0x000000f0; - base |= (rbase >> 8) & 0xffffff00; - base |= 3; - limit &= 0x00000048; - limit |= (rend >> 8) & 0xffffff00; - limit |= (link & 3) << 4; - limit |= (nodeid & 7); - f1_write_config32(reg + 0x4, limit); - f1_write_config32(reg, base); - } - resource->flags |= IORESOURCE_STORED; - sprintf(buf, " <node %d link %d>", - nodeid, link); - report_resource_stored(dev, resource, buf); -} - -/** - * - * I tried to reuse the resource allocation code in amdk8_set_resource() - * but it is too diffcult to deal with the resource allocation magic. - */ -#if CONFIG_MULTIPLE_VGA_INIT == 1 -extern struct device * vga_pri; // the primary vga device, defined in device.c -#endif - -static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) -{ - struct resource *resource; - unsigned link; - u32 base, limit; - unsigned reg; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = 0; link < dev->links; link++) { - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_MULTIPLE_VGA_INIT == 1 - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, - dev->link[link].secondary,dev->link[link].subordinate); - /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= dev->link[link].secondary ) && - (vga_pri->bus->secondary <= dev->link[link].subordinate ) - ) -#endif - break; - } - } - - /* no VGA card installed */ - if (link == dev->links) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); - - /* allocate a temp resrouce for legacy VGA buffer */ - resource = amdk8_find_mempair(dev, nodeid, link); - if(!resource){ - printk(BIOS_DEBUG, "VGA: Can not find free mmio reg for legacy VGA buffer\n"); - return; - } - resource->base = 0xa0000; - resource->size = 0x20000; - - /* write the resource to the hardware */ - reg = resource->index & 0xfc; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x4); - base &= 0x000000f0; - base |= (resource->base >> 8) & 0xffffff00; - base |= 3; - limit &= 0x00000048; - limit |= (resource_end(resource) >> 8) & 0xffffff00; - limit |= (resource->index & 3) << 4; - limit |= (nodeid & 7); - f1_write_config32(reg + 0x4, limit); - f1_write_config32(reg, base); - - /* release the temp resource */ - resource->flags = 0; -} - -static void amdk8_set_resources(struct device * dev) -{ - unsigned nodeid, link; - int i; - - /* Find the nodeid */ - nodeid = amdk8_nodeid(dev); - - amdk8_create_vga_resource(dev, nodeid); - - /* Set each resource we have found */ - for(i = 0; i < dev->resources; i++) { - amdk8_set_resource(dev, &dev->resource[i], nodeid); - } - - for(link = 0; link < dev->links; link++) { - struct bus *bus; - bus = &dev->link[link]; - if (bus->children) { - assign_resources(bus); - } - } -} - -static void amdk8_enable_resources(struct device * dev) -{ - pci_dev_enable_resources(dev); - enable_childrens_resources(dev); -} - -static void mcf0_control_init(struct device *dev) -{ - printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. Nothing to do ..."); - - printk(BIOS_DEBUG, "done.\n"); -} - - -static void k8_pci_domain_read_resources(struct device * dev) -{ - struct resource *resource; - unsigned reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for(reg = 0x80; reg <= 0xd8; reg+= 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned nodeid, link; - struct device * dev; - nodeid = limit & 7; - link = (limit >> 4) & 3; - dev = __f0_dev[nodeid]; - if (dev) { - /* Reserve the resource */ - struct resource *resource; - resource = new_resource(dev, 0x100 + (reg | link)); - if (resource) { - resource->flags = 1; - } - } - } - } -#if CONFIG_PCI_64BIT_PREF_MEM == 0 - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -#else - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, 0); - resource->base = 0x400; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_IO, IORESOURCE_IO); - - /* Initialize the system wide prefetchable memory resources constraints */ - resource = new_resource(dev, 1); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM | IORESOURCE_PREFETCH); - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, 2); - resource->limit = 0xfcffffffffULL; - resource->flags = IORESOURCE_MEM; - compute_allocate_resource(&dev->link[0], resource, - IORESOURCE_MEM | IORESOURCE_PREFETCH, - IORESOURCE_MEM); -#endif -} - -static void k8_ram_resource(struct device * dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static u32 find_pci_tolm(struct bus *bus) -{ - struct resource *min; - u32 tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - -#ifdef CONFIG_PCI_64BIT_PREF_MEM -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) -#endif - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - -struct hw_mem_hole_info { - unsigned hole_startk; - int node_id; -}; - -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - int i; - - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - - for (i = 0; i < 8; i++) { - u32 base; - u32 hole; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - - hole = pci_read_config32(__f1_dev[i], 0xf0); - if(hole & 1) { // we find the hole - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole - } - } - - //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk - if(mem_hole.node_id==-1) { - u32 limitk_pri = 0; - for(i=0; i<8; i++) { - u32 base, limit; - unsigned base_k, limit_k; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - - base_k = (base & 0xffff0000) >> 2; - if(limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = limitk_pri; - mem_hole.node_id = i; - break; //only one hole - } - - limit = f1_read_config32(0x44 + (i << 3)); - limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; - limitk_pri = limit_k; - } - } - - return mem_hole; - -} -static void disable_hoist_memory(unsigned long hole_startk, int i) -{ - int ii; - struct device * dev; - u32 base, limit; - u32 hoist; - u32 hole_sizek; - - - //1. find which node has hole - //2. change limit in that node. - //3. change base and limit in later node - //4. clear that node f0 - - //if there is not mem hole enabled, we need to change it's base instead - - hole_sizek = (4*1024*1024) - hole_startk; - - for(ii=7;ii>i;ii--) { - - base = f1_read_config32(0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - limit = f1_read_config32(0x44 + (ii << 3)); - f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); - f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); - } - limit = f1_read_config32(0x44 + (i << 3)); - f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); - dev = __f1_dev[i]; - hoist = pci_read_config32(dev, 0xf0); - if(hoist & 1) { - pci_write_config32(dev, 0xf0, 0); - } - else { - base = pci_read_config32(dev, 0x40 + (i << 3)); - f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2)); - } - -} - -static u32 hoist_memory(unsigned long hole_startk, int i) -{ - int ii; - u32 carry_over; - struct device * dev; - u32 base, limit; - u32 basek; - u32 hoist; - - carry_over = (4*1024*1024) - hole_startk; - - for(ii=7;ii>i;ii--) { - - base = f1_read_config32(0x40 + (ii << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - limit = f1_read_config32(0x44 + (ii << 3)); - f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); - f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); - } - limit = f1_read_config32(0x44 + (i << 3)); - f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); - dev = __f1_dev[i]; - base = pci_read_config32(dev, 0x40 + (i << 3)); - basek = (base & 0xffff0000) >> 2; - if(basek == hole_startk) { - //don't need set memhole here, because hole off set will be 0, overflow - //so need to change base reg instead, new basek will be 4*1024*1024 - base &= 0x0000ffff; - base |= (4*1024*1024)<<2; - f1_write_config32(0x40 + (i<<3), base); - } - else - { - hoist = /* hole start address */ - ((hole_startk << 10) & 0xff000000) + - /* hole address to memory controller address */ - (((basek + carry_over) >> 6) & 0x0000ff00) + - /* enable */ - 1; - - pci_write_config32(dev, 0xf0, hoist); - } - - return carry_over; -} -#endif - -static void k8_pci_domain_set_resources(struct device * dev) -{ -#if CONFIG_PCI_64BIT_PREF_MEM == 1 - struct resource *io, *mem1, *mem2; - struct resource *resource, *last; -#endif - unsigned long mmio_basek; - u32 pci_tolm; - int i, idx; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; - unsigned reset_memhole = 1; -#endif - -#if 0 - /* Place the IO devices somewhere safe */ - io = find_resource(dev, 0); - io->base = DEVICE_IO_START; -#endif -#if CONFIG_PCI_64BIT_PREF_MEM == 1 - /* Now reallocate the pci resources memory with the - * highest addresses I can manage. - */ - mem1 = find_resource(dev, 1); - mem2 = find_resource(dev, 2); - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - /* See if both resources have roughly the same limits */ - if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || - ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) - { - /* If so place the one with the most stringent alignment first - */ - if (mem2->align > mem1->align) { - struct resource *tmp; - tmp = mem1; - mem1 = mem2; - mem2 = tmp; - } - /* Now place the memory as high up as it will go */ - mem2->base = resource_max(mem2); - mem1->limit = mem2->base - 1; - mem1->base = resource_max(mem1); - } - else { - /* Place the resources as high up as they will go */ - mem2->base = resource_max(mem2); - mem1->base = resource_max(mem1); - } - -#if 1 - printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", - mem1->base, mem1->limit, mem1->size, mem1->align); - printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", - mem2->base, mem2->limit, mem2->size, mem2->align); -#endif - - last = &dev->resource[dev->resources]; - for(resource = &dev->resource[0]; resource < last; resource++) - { -#if 1 - resource->flags |= IORESOURCE_ASSIGNED; - resource->flags &= ~IORESOURCE_STORED; -#endif - compute_allocate_resource(&dev->link[0], resource, - BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK); - - resource->flags |= IORESOURCE_STORED; - report_resource_stored(dev, resource, ""); - - } -#endif - - - pci_tolm = find_pci_tolm(&dev->link[0]); - -#warning "FIXME handle interleaved nodes" - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - -#if 1 -#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole" - /* Round the mmio hold to 64M */ - mmio_basek &= ~((64*1024) - 1); -#endif - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek - * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - #ifndef CONFIG_K8_REV_F_SUPPORT - if (!is_cpu_pre_e0()) { - #endif - - mem_hole = get_hw_mem_hole_info(); - - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { //We will use hole_basek as mmio_basek, and we don't need to reset hole anymore - mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } - - //mmio_basek = 3*1024*1024; // for debug to meet boundary - - if(reset_memhole) { - if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! - // We need to reset our Mem Hole, because We want more big HOLE than we already set - //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead - disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); - } - - #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 - //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some - u32 basek_pri; - for (i = 0; i < 8; i++) { - u32 base; - u32 basek; - base = f1_read_config32(0x40 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - - basek = (base & 0xffff0000) >> 2; - if(mmio_basek == basek) { - mmio_basek -= (basek - basek_pri)>>1; // increase mem hole size to make sure it is on middle of pri node - break; - } - basek_pri = basek; - } - #endif - } - -#ifndef CONFIG_K8_REV_F_SUPPORT - } // is_cpu_pre_e0 -#endif - -#endif - - idx = 0x10; - for(i = 0; i < 8; i++) { - u32 base, limit; - unsigned basek, limitk, sizek; - base = f1_read_config32(0x40 + (i << 3)); - limit = f1_read_config32(0x44 + (i << 3)); - if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { - continue; - } - basek = (base & 0xffff0000) >> 2; - limitk = ((limit + 0x00010000) & 0xffff0000) >> 2; - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - k8_ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - - } - - - printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu - - /* See if I need to split the region to accomodate pci memory space */ - if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) { - if (basek <= mmio_basek) { - unsigned pre_sizek; - pre_sizek = mmio_basek - basek; - if(pre_sizek>0) { - k8_ram_resource(dev, (idx | i), basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - if(reset_memhole) - #ifndef CONFIG_K8_REV_F_SUPPORT - if(!is_cpu_pre_e0() ) - #endif - sizek += hoist_memory(mmio_basek,i); - #endif - - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } - else { - basek = 4*1024*1024; - sizek -= (4*1024*1024 - mmio_basek); - } - } - k8_ram_resource(dev, (idx | i), basek, sizek); - idx += 0x10; - } - assign_resources(&dev->link[0]); -} - -static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max) -{ - unsigned reg; - int i; - /* Unmap all of the HT chains */ - for(reg = 0xe0; reg <= 0xec; reg += 4) { - f1_write_config32(reg, 0); - } - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max); - - /* Tune the hypertransport transaction for best performance. - * Including enabling relaxed ordering if it is safe. - */ - get_fx_devs(); - for(i = 0; i < FX_DEVS; i++) { - struct device * f0_dev; - f0_dev = __f0_dev[i]; - if (f0_dev && f0_dev->enabled) { - u32 httc; - httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL); - httc &= ~HTTC_RSP_PASS_PW; - if (!dev->link[0].disable_relaxed_ordering) { - httc |= HTTC_RSP_PASS_PW; - } - printk(BIOS_SPEW, "%s passpw: %s\n", - dev_path(dev), - (!dev->link[0].disable_relaxed_ordering)? - "enabled":"disabled"); - pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); - } - } - return max; -} - - -static unsigned int cpu_bus_scan(struct device * dev, unsigned int max) -{ - struct bus *cpu_bus; - struct device * dev_mc; - int bsp_apicid; - int i,j; - unsigned nb_cfg_54; - unsigned siblings; - int e0_later_single_core; - int disable_siblings; - - nb_cfg_54 = 0; - sysconf.enabled_apic_ext_id = 0; - sysconf.lift_bsp_apicid = 0; - siblings = 0; - - /* Find the bootstrap processors apicid */ - bsp_apicid = lapicid(); - sysconf.apicid_offset = bsp_apicid; - - disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 - get_option(&disable_siblings, "dual_core"); -#endif - - // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0) - // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core - - nb_cfg_54 = read_nb_cfg_54(); - - dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); - if (!dev_mc) { - die("0:18.0 not found?"); - } - - sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1; - - - if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) - { - sysconf.enabled_apic_ext_id = 1; - if(bsp_apicid == 0) { - /* bsp apic id is not changed */ - sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; - } else - { - sysconf.lift_bsp_apicid = 1; - } - - } - - /* Find which cpus are present */ - cpu_bus = &dev->link[0]; - for(i = 0; i < sysconf.nodes; i++) { - struct device * dev, *cpu; - struct device_path cpu_path; - - /* Find the cpu's pci device */ - dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); - if (!dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int j; - struct device * dev_f0; - for(j = 0; j <= 3; j++) { - dev = pci_probe_dev(NULL, dev_mc->bus, - PCI_DEVFN(0x18 + i, j)); - } - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0)); - if(dev_f0) { - dev_f0->links = 3; - for(j=0;j<3;j++) { - dev_f0->link[j].link = j; - dev_f0->link[j].dev = dev_f0; - } - } - - } - - e0_later_single_core = 0; - if (dev && dev->enabled) { - j = pci_read_config32(dev, 0xe8); - j = (j >> 12) & 3; // dev is func 3 - printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(dev), j); - - if(nb_cfg_54) { - // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... - // ----> you can mixed single core e0 and dual core e0 at any sequence - // That is the typical case - - if(j == 0 ){ - #ifndef CONFIG_K8_REV_F_SUPPORT - e0_later_single_core = is_e0_later_in_bsp(i); // single core - #else - e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 - #endif - } else { - e0_later_single_core = 0; - } - if(e0_later_single_core) { - printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n"); - - j=1; - } - - if(siblings > j ) { - } - else { - siblings = j; - } - } else { - siblings = j; - } - } - - unsigned jj; - if(e0_later_single_core || disable_siblings) { - jj = 0; - } else - { - jj = siblings; - } -#if 0 - jj = 0; // if create cpu core1 path in amd_siblings by core0 -#endif - - for (j = 0; j <=jj; j++ ) { - - /* Build the cpu device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - - /* See if I can find the cpu */ - cpu = find_dev_path(cpu_bus, &cpu_path); - - /* Enable the cpu if I have the processor */ - if (dev && dev->enabled) { - /* this is a CPU */ - struct device_id did; - did.type = DEVICE_ID_CPU; -#warning fill cpuid; right now it is zero - if (!cpu) { - cpu = alloc_dev(cpu_bus, &cpu_path, &did); - } - if (cpu) { - cpu->enabled = 1; - } - } - - /* Disable the cpu if I don't have the processor */ - if (cpu && (!dev || !dev->enabled)) { - cpu->enabled = 0; - } - - /* Report what I have done */ - if (cpu) { - cpu->path.apic.node_id = i; - cpu->path.apic.core_id = j; - if(sysconf.enabled_apic_ext_id) { - if(sysconf.lift_bsp_apicid) { - cpu->path.apic.apic_id += sysconf.apicid_offset; - } else - { - if (cpu->path.apic.apic_id != 0) - cpu->path.apic.apic_id += sysconf.apicid_offset; - } - } - printk(BIOS_DEBUG, "CPU: %s %s\n", - dev_path(cpu), cpu->enabled?"enabled":"disabled"); - } - - } //j - } - return max; -} - -static void cpu_bus_init(struct device * dev) -{ - /* unclear if we need this any more. CPUs are in the device tree. */ - // initialize_cpus(&dev->link[0]); - //so what do we do? This is a first for v3. -} - -static void cpu_bus_noop(struct device * dev) -{ -} - -struct device_operations k8_ops = { - .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x1100}}}, - .constructor = default_device_constructor, - .reset_bus = pci_bus_reset, - .phase3_scan = amdk8_scan_chains, - .phase4_read_resources = amdk8_read_resources, - .phase4_set_resources = amdk8_set_resources, - .phase5_enable_resources = amdk8_enable_resources, - .phase6_init = mcf0_control_init, - .ops_pci = &pci_dev_ops_pci, -}; - - - -/* arguably, this should no longer be here. It was part of a nasty kludge because the CPUs - * were never really part of the device tree. The solution crafted in v2 was expedient but - * hardly comprehensible. It may be removed soon. - */ -/* the interesting question, of course: should we really be going for an *exact* match? Or a range? */ -struct device_operations k8cpu_ops = { - .id = {.type = DEVICE_ID_CPU, - {.cpu = {"Genuine AMD"}}}, - .constructor = default_device_constructor, - .phase3_scan = cpu_bus_scan, - .phase4_read_resources = cpu_bus_noop, - .phase4_set_resources = cpu_bus_noop, - .phase5_enable_resources = cpu_bus_noop, - .phase6_init = cpu_bus_init, - .ops_pci = &pci_dev_ops_pci, -}; - -struct device_operations k8apic_ops = { - .id = {.type = DEVICE_ID_APIC_CLUSTER, - {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, - .device = 0x1100}}}, - .constructor = default_device_constructor, - .phase3_scan = k8_domain_scan_bus, - .phase4_read_resources = k8_pci_domain_read_resources, - .phase4_set_resources = k8_pci_domain_set_resources, - .phase5_enable_resources = enable_childrens_resources, - .ops_pci = &pci_dev_ops_pci, - .ops_pci_bus = &pci_cf8_conf1, -}; Copied: coreboot-v3/northbridge/amd/k8/pci.c (from rev 757, coreboot-v3/northbridge/amd/k8/northbridge.c) =================================================================== --- coreboot-v3/northbridge/amd/k8/pci.c (rev 0) +++ coreboot-v3/northbridge/amd/k8/pci.c 2008-08-14 16:31:24 UTC (rev 764) @@ -0,0 +1,831 @@ +/* + * K8 northbridge + * This file is part of the coreboot project. + * Copyright (C) 2004-2005 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> and Jason Schildt for Linux Networx) + * Copyright (C) 2005-7 YingHai Lu + * Copyright (C) 2005 Ollie Lo + * Copyright (C) 2005-2007 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ +/* This should be done by Eric + 2004.12 yhlu add dual core support + 2005.01 yhlu add support move apic before pci_domain in MB Config.lb + 2005.02 yhlu add e0 memory hole support + 2005.11 yhlu add put sb ht chain on bus 0 +*/ + +#include <console.h> +#include <lib.h> +#include <string.h> +#include <mtrr.h> +#include <macros.h> +#include <spd.h> +#include <cpu.h> +#include <msr.h> +#include <amd/k8/k8.h> +#include <amd/k8/sysconf.h> +#include <device/pci.h> +#include <device/hypertransport_def.h> +#include <device/hypertransport.h> +#include <mc146818rtc.h> +#include <lib.h> +#include <lapic.h> + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +#include <cpu/amd/model_fxx_rev.h> +#endif + +struct amdk8_sysconf sysconf; + +#define FX_DEVS 8 +static struct device * __f0_dev[FX_DEVS]; +static struct device * __f1_dev[FX_DEVS]; + +#if 0 +static void debug_fx_devs(void) +{ + int i; + for(i = 0; i < FX_DEVS; i++) { + struct device * dev; + dev = __f0_dev[i]; + if (dev) { + printk(BIOS_DEBUG, "__f0_dev[%d]: %s bus: %p\n", + i, dev_path(dev), dev->bus); + } + dev = __f1_dev[i]; + if (dev) { + printk(BIOS_DEBUG, "__f1_dev[%d]: %s bus: %p\n", + i, dev_path(dev), dev->bus); + } + } +} +#endif + +static void get_fx_devs(void) +{ + int i; + if (__f1_dev[0]) { + return; + } + for(i = 0; i < FX_DEVS; i++) { + __f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0)); + __f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1)); + } + if (!__f1_dev[0]) { + die("Cannot find 0:0x18.1\n"); + } +} + +static u32 f1_read_config32(unsigned reg) +{ + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + get_fx_devs(); + for(i = 0; i < FX_DEVS; i++) { + struct device * dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static unsigned int amdk8_nodeid(struct device * dev) +{ + return (dev->path.pci.devfn >> 3) - 0x18; +} + +static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid) +{ + + u32 link_type; + int i; + u32 busses, config_busses; + unsigned free_reg, config_reg; + unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain + unsigned max_bus; + unsigned min_bus; + unsigned max_devfn; + + dev->link[link].cap = 0x80 + (link *0x20); + do { + link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + } while(link_type & ConnectionPending); + if (!(link_type & LinkConnected)) { + return max; + } + do { + link_type = pci_read_config32(dev, dev->link[link].cap + 0x18); + } while(!(link_type & InitComplete)); + if (!(link_type & NonCoherent)) { + return max; + } + /* See if there is an available configuration space mapping + * register in function 1. + */ + free_reg = 0; + for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) { + u32 config; + config = f1_read_config32(config_reg); + if (!free_reg && ((config & 3) == 0)) { + free_reg = config_reg; + continue; + } + if (((config & 3) == 3) && + (((config >> 4) & 7) == nodeid) && + (((config >> 8) & 3) == link)) { + break; + } + } + if (free_reg && (config_reg > 0xec)) { + config_reg = free_reg; + } + /* If we can't find an available configuration space mapping + * register skip this bus + */ + if (config_reg > 0xec) { + return max; + } + + /* Set up the primary, secondary and subordinate bus numbers. + * We have no idea how many busses are behind this bridge yet, + * so we set the subordinate bus number to 0xff for the moment. + */ +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + // first chain will on bus 0 + if((nodeid == 0) && (sblink==link)) { // actually max is 0 here + min_bus = max; + } + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 + // second chain will be on 0x40, third 0x80, forth 0xc0 + else { + min_bus = ((max>>6) + 1) * 0x40; + } + max = min_bus; + #else + //other ... + else { + min_bus = ++max; + } + #endif +#else + min_bus = ++max; +#endif + max_bus = 0xff; + + dev->link[link].secondary = min_bus; + dev->link[link].subordinate = max_bus; + + /* Read the existing primary/secondary/subordinate bus + * number configuration. + */ + busses = pci_read_config32(dev, dev->link[link].cap + 0x14); + config_busses = f1_read_config32(config_reg); + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagates by the bridge if it is + * not correctly configured + */ + busses &= 0xff000000; + busses |= (((unsigned int)(dev->bus->secondary) << 0) | + ((unsigned int)(dev->link[link].secondary) << 8) | + ((unsigned int)(dev->link[link].subordinate) << 16)); + pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + + config_busses &= 0x000fc88; + config_busses |= + (3 << 0) | /* rw enable, no device compare */ + (( nodeid & 7) << 4) | + (( link & 3 ) << 8) | + ((dev->link[link].secondary) << 16) | + ((dev->link[link].subordinate) << 24); + f1_write_config32(config_reg, config_busses); + + /* Now we can scan all of the subordinate busses i.e. the + * chain on the hypertranport link + */ + for(i=0;i<4;i++) { + ht_unitid_base[i] = 0x20; + } + + if (min_bus == 0) + max_devfn = (0x17<<3) | 7; + else + max_devfn = (0x1f<<3) | 7; + + max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid); + + /* We know the number of busses behind this bridge. Set the + * subordinate bus number to it's real value + */ + dev->link[link].subordinate = max; + busses = (busses & 0xff00ffff) | + ((unsigned int) (dev->link[link].subordinate) << 16); + pci_write_config32(dev, dev->link[link].cap + 0x14, busses); + + config_busses = (config_busses & 0x00ffffff) | + (dev->link[link].subordinate << 24); + f1_write_config32(config_reg, config_busses); + + { + // config config_reg, and ht_unitid_base to update hcdn_reg; + int index; + unsigned temp = 0; + index = (config_reg-0xe0) >> 2; + for(i=0;i<4;i++) { + temp |= (ht_unitid_base[i] & 0xff) << (i*8); + } + + sysconf.hcdn_reg[index] = temp; + + } + + return max; +} + +static unsigned int amdk8_scan_chains(struct device * dev, unsigned int max) +{ + unsigned nodeid; + unsigned link; + unsigned sblink = 0; + unsigned offset_unitid = 0; + nodeid = amdk8_nodeid(dev); + + if(nodeid==0) { + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + offset_unitid = 1; + #endif + // do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2, + // but put 8151 on link0 + max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); +#endif + } + + for(link = 0; link < dev->links; link++) { +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + if( (nodeid == 0) && (sblink == link) ) continue; //already done +#endif + offset_unitid = 0; + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + if((nodeid == 0) && (sblink == link)) + #endif + offset_unitid = 1; + #endif + + max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid); + } + + return max; +} + + +static int reg_useable(unsigned reg, + struct device * goal_dev, unsigned goal_nodeid, unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link; + int result; + res = 0; + for(nodeid = 0; !res && (nodeid < 8); nodeid++) { + struct device * dev; + dev = __f0_dev[nodeid]; + for(link = 0; !res && (link < 3); link++) { + res = probe_resource(dev, 0x100 + (reg | link)); + } + } + result = 2; + if (res) { + result = 0; + if ( (goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + + return result; +} + +static struct resource *amdk8_find_iopair(struct device * dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + unsigned free_reg, reg; + resource = 0; + free_reg = 0; + for(reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; + } + if (reg > 0) { + resource = new_resource(dev, 0x100 + (reg | link)); + } + return resource; +} + +static struct resource *amdk8_find_mempair(struct device * dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + unsigned free_reg, reg; + resource = 0; + free_reg = 0; + for(reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + if (reg > 0) { + resource = new_resource(dev, 0x100 + (reg | link)); + } + return resource; +} + +static void amdk8_link_read_bases(struct device * dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdk8_find_iopair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_IO_HOST_ALIGN); + resource->gran = log2(HT_IO_HOST_ALIGN); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_IO, IORESOURCE_IO); + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdk8_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM | IORESOURCE_PREFETCH); + } + + /* Initialize the memory constraints on the current bus */ + resource = amdk8_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + IORESOURCE_MEM); + } +} + +static void amdk8_read_resources(struct device * dev) +{ + unsigned nodeid, link; + nodeid = amdk8_nodeid(dev); + for(link = 0; link < dev->links; link++) { + if (dev->link[link].children) { + amdk8_link_read_bases(dev, nodeid, link); + } + } +} + +static void amdk8_set_resource(struct device * dev, struct resource *resource, unsigned nodeid) +{ + resource_t rbase, rend; + unsigned reg, link; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if (resource->index < 0x100) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfc; + link = resource->index & 3; + + if (resource->flags & IORESOURCE_IO) { + u32 base, limit; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_IO, IORESOURCE_IO); + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x4); + base &= 0xfe000fcc; + base |= rbase & 0x01fff000; + base |= 3; + limit &= 0xfe000fc8; + limit |= rend & 0x01fff000; + limit |= (link & 3) << 4; + limit |= (nodeid & 7); + + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %x\n", + __func__, dev_path(dev), link); + base |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + base |= PCI_IO_BASE_NO_ISA; + } + + f1_write_config32(reg + 0x4, limit); + f1_write_config32(reg, base); + } + else if (resource->flags & IORESOURCE_MEM) { + u32 base, limit; + compute_allocate_resource(&dev->link[link], resource, + IORESOURCE_MEM | IORESOURCE_PREFETCH, + resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH)); + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x4); + base &= 0x000000f0; + base |= (rbase >> 8) & 0xffffff00; + base |= 3; + limit &= 0x00000048; + limit |= (rend >> 8) & 0xffffff00; + limit |= (link & 3) << 4; + limit |= (nodeid & 7); + f1_write_config32(reg + 0x4, limit); + f1_write_config32(reg, base); + } + resource->flags |= IORESOURCE_STORED; + sprintf(buf, " <node %d link %d>", + nodeid, link); + report_resource_stored(dev, resource, buf); +} + +/** + * + * I tried to reuse the resource allocation code in amdk8_set_resource() + * but it is too diffcult to deal with the resource allocation magic. + */ +#if CONFIG_MULTIPLE_VGA_INIT == 1 +extern struct device * vga_pri; // the primary vga device, defined in device.c +#endif + +static void amdk8_create_vga_resource(struct device * dev, unsigned nodeid) +{ + struct resource *resource; + unsigned link; + u32 base, limit; + unsigned reg; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = 0; link < dev->links; link++) { + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_INIT == 1 + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary, + dev->link[link].secondary,dev->link[link].subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= dev->link[link].secondary ) && + (vga_pri->bus->secondary <= dev->link[link].subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == dev->links) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link); + + /* allocate a temp resrouce for legacy VGA buffer */ + resource = amdk8_find_mempair(dev, nodeid, link); + if(!resource){ + printk(BIOS_DEBUG, "VGA: Can not find free mmio reg for legacy VGA buffer\n"); + return; + } + resource->base = 0xa0000; + resource->size = 0x20000; + + /* write the resource to the hardware */ + reg = resource->index & 0xfc; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x4); + base &= 0x000000f0; + base |= (resource->base >> 8) & 0xffffff00; + base |= 3; + limit &= 0x00000048; + limit |= (resource_end(resource) >> 8) & 0xffffff00; + limit |= (resource->index & 3) << 4; + limit |= (nodeid & 7); + f1_write_config32(reg + 0x4, limit); + f1_write_config32(reg, base); + + /* release the temp resource */ + resource->flags = 0; +} + +static void amdk8_set_resources(struct device * dev) +{ + unsigned nodeid, link; + int i; + + /* Find the nodeid */ + nodeid = amdk8_nodeid(dev); + + amdk8_create_vga_resource(dev, nodeid); + + /* Set each resource we have found */ + for(i = 0; i < dev->resources; i++) { + amdk8_set_resource(dev, &dev->resource[i], nodeid); + } + + for(link = 0; link < dev->links; link++) { + struct bus *bus; + bus = &dev->link[link]; + if (bus->children) { + assign_resources(bus); + } + } +} + +static void amdk8_enable_resources(struct device * dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static void mcf0_control_init(struct device *dev) +{ + printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. Nothing to do ..."); + + printk(BIOS_DEBUG, "done.\n"); +} + +static void k8_ram_resource(struct device * dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static u32 find_pci_tolm(struct bus *bus) +{ + struct resource *min; + u32 tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +#ifdef CONFIG_PCI_64BIT_PREF_MEM +#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) +#endif + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; + +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + + for (i = 0; i < 8; i++) { + u32 base; + u32 hole; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + + hole = pci_read_config32(__f1_dev[i], 0xf0); + if(hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + //We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk + if(mem_hole.node_id==-1) { + u32 limitk_pri = 0; + for(i=0; i<8; i++) { + u32 base, limit; + unsigned base_k, limit_k; + base = f1_read_config32(0x40 + (i << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + + base_k = (base & 0xffff0000) >> 2; + if(limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = limitk_pri; + mem_hole.node_id = i; + break; //only one hole + } + + limit = f1_read_config32(0x44 + (i << 3)); + limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2; + limitk_pri = limit_k; + } + } + + return mem_hole; + +} +static void disable_hoist_memory(unsigned long hole_startk, int i) +{ + int ii; + struct device * dev; + u32 base, limit; + u32 hoist; + u32 hole_sizek; + + + //1. find which node has hole + //2. change limit in that node. + //3. change base and limit in later node + //4. clear that node f0 + + //if there is not mem hole enabled, we need to change it's base instead + + hole_sizek = (4*1024*1024) - hole_startk; + + for(ii=7;ii>i;ii--) { + + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + limit = f1_read_config32(0x44 + (ii << 3)); + f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2)); + f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2)); + dev = __f1_dev[i]; + hoist = pci_read_config32(dev, 0xf0); + if(hoist & 1) { + pci_write_config32(dev, 0xf0, 0); + } + else { + base = pci_read_config32(dev, 0x40 + (i << 3)); + f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2)); + } + +} + +static u32 hoist_memory(unsigned long hole_startk, int i) +{ + int ii; + u32 carry_over; + struct device * dev; + u32 base, limit; + u32 basek; + u32 hoist; + + carry_over = (4*1024*1024) - hole_startk; + + for(ii=7;ii>i;ii--) { + + base = f1_read_config32(0x40 + (ii << 3)); + if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) { + continue; + } + limit = f1_read_config32(0x44 + (ii << 3)); + f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2)); + f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2)); + } + limit = f1_read_config32(0x44 + (i << 3)); + f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2)); + dev = __f1_dev[i]; + base = pci_read_config32(dev, 0x40 + (i << 3)); + basek = (base & 0xffff0000) >> 2; + if(basek == hole_startk) { + //don't need set memhole here, because hole off set will be 0, overflow + //so need to change base reg instead, new basek will be 4*1024*1024 + base &= 0x0000ffff; + base |= (4*1024*1024)<<2; + f1_write_config32(0x40 + (i<<3), base); + } + else + { + hoist = /* hole start address */ + ((hole_startk << 10) & 0xff000000) + + /* hole address to memory controller address */ + (((basek + carry_over) >> 6) & 0x0000ff00) + + /* enable */ + 1; + + pci_write_config32(dev, 0xf0, hoist); + } + + return carry_over; +} +#endif + +struct device_operations k8_ops = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = 0x1100}}}, + .constructor = default_device_constructor, + .reset_bus = pci_bus_reset, + .phase3_scan = amdk8_scan_chains, + .phase4_read_resources = amdk8_read_resources, + .phase4_set_resources = amdk8_set_resources, + .phase5_enable_resources = amdk8_enable_resources, + .phase6_init = mcf0_control_init, + .ops_pci = &pci_dev_ops_pci, +}; Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-08-14 16:16:07 UTC (rev 763) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-08-14 16:31:24 UTC (rev 764) @@ -26,6 +26,6 @@ void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device); -struct pci_operations mcp55_pci_dev_ops_pci; +extern struct pci_operations mcp55_pci_dev_ops_pci; #endif /* MCP55_H */

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coreboot August 2008