coreboot August 2008

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patch: allow dts names to end in .dts
by ron minnich 11 Aug '08

11 Aug '08

If a dts name ends in .dts, e.g. /config/("southbridge/nvidia/mcp55/ide.dts"); it will be used. The node label will have the .dts removed. Attached. Tested on builds and it looks fine. Now you can all stop telling me to do this :-) ron

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r740 - coreboot-v3/util/dtc
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-11 18:05:53 +0200 (Mon, 11 Aug 2008) New Revision: 740 Modified: coreboot-v3/util/dtc/dtc-parser.y Log: Add support for dtc files that end in .dtc, e.g. ide.dtc. This is managed by stripping the .dtc from the name when it is used to label the node in the tree. This one's for you Peter! Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/util/dtc/dtc-parser.y =================================================================== --- coreboot-v3/util/dtc/dtc-parser.y 2008-08-11 16:04:38 UTC (rev 739) +++ coreboot-v3/util/dtc/dtc-parser.y 2008-08-11 16:05:53 UTC (rev 740) @@ -139,9 +139,17 @@ switchback(); } - ')' ';' { + ')' ';' { + int namelen; + char *name = strdup((char *)$3.val); /* convention: first property is labeled with path */ - $6->label = strdup((char *)$3.val); + $6->label = name; + + /* convention: if it ends in .dts, strip that off */ + namelen = strlen($6->label); + if ((namelen > 4) && (! strncmp(&name[namelen-4], ".dts", 4))) + $6->label[namelen-4] = '\0'; + $$ = $6 } |

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r739 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-11 18:04:38 +0200 (Mon, 11 Aug 2008) New Revision: 739 Added: coreboot-v3/southbridge/nvidia/mcp55/ide.c coreboot-v3/southbridge/nvidia/mcp55/ide.dts Log: .c and .dts for mcp55 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: coreboot-v3/southbridge/nvidia/mcp55/ide.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/ide.c (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-11 16:04:38 UTC (rev 739) @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <lib.h> +#include <console.h> +#include <device/pci.h> +#include <msr.h> +#include <legacy.h> +#include <device/pci_ids.h> +#include <statictree.h> +#include <config.h> +#include "mcp55.h" + +static void ide_init(struct device *dev) +{ + struct southbridge_nvidia_mcp55_ide_config *conf = + (struct southbridge_nvidia_mcp55_ide_config *)dev->device_configuration; + /* Enable ide devices so the linux ide driver will work */ + u32 dword; + u16 word; + u8 byte; + + word = pci_read_config16(dev, 0x50); + /* Ensure prefetch is disabled */ + word &= ~((1 << 15) | (1 << 13)); + if (conf->ide1_enable) { + word |= (1<<0); + printk(BIOS_DEBUG, "Enable secondary ide interface\t"); + } + if (conf->ide0_enable) { + word |= (1<<1); + printk(BIOS_DEBUG, "Enable primary ide interfac\n"); + } + + word |= (1<<12); + word |= (1<<14); + + pci_write_config16(dev, 0x50, word); + + + byte = 0x20 ; // Latency: 64-->32 + pci_write_config8(dev, 0xd, byte); + + dword = pci_read_config32(dev, 0xf8); + dword |= 12; + pci_write_config32(dev, 0xf8, dword); +#ifdef CONFIG_PCI_ROM_RUN + pci_dev_init(dev); +#endif + +#warning set subsystem id on mcp55 ide +#if 0 + pci_write_config32(dev, 0x40, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +#endif +} + +struct device_operations mcp55_ide = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + .device = PCI_DEVICE_ID_NVIDIA_MCP55_IDE}}}, + .constructor = default_device_constructor, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_dev_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = ide_init, + .ops_pci = &pci_dev_ops_pci, +}; + Added: coreboot-v3/southbridge/nvidia/mcp55/ide.dts =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/ide.dts (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/ide.dts 2008-08-11 16:04:38 UTC (rev 739) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-8 Ronald G. Minnich <rminnich(a)gmail.com> * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + device_operations = "mcp55_ide"; + + /* IDE: enable MCP55 IDE. There may be a different IDE controller on board */ + ide0_enable = "0"; + ide1_enable = "0"; +};

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last for the day
by ron minnich 11 Aug '08

11 Aug '08

This brings us to compiling with warnings, no errors. (!) It does not link of course! The code needs lots of cleanup and formatting, which I think should wait for another commit. I would like to get this in as it is very close to the v2 code and hence further changes will be more clearly delineated. Stefan I think I got the mainboard makefile wrong; can you look? I am going to finish up bringing mcp55 files over but then move to a SimNOW supported mainboard. SimNOW is too useful not to use. Marc or Jordan, what is the *simplest* SimNOW mobo I can use to start testing if I get that far? thanks ron

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r738 - coreboot-v3/arch/x86
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: rminnich Date: 2008-08-11 17:55:05 +0200 (Mon, 11 Aug 2008) New Revision: 738 Modified: coreboot-v3/arch/x86/Kconfig Log: new defines for K8 and SMP Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/arch/x86/Kconfig =================================================================== --- coreboot-v3/arch/x86/Kconfig 2008-08-11 13:23:40 UTC (rev 737) +++ coreboot-v3/arch/x86/Kconfig 2008-08-11 15:55:05 UTC (rev 738) @@ -56,6 +56,58 @@ arch/x86/Makefile for more hints on possible values. It is usually set in mainboard/*/Kconfig. +config K8_REV_F_SUPPORT + hex + default 0 if CPU_AMD_K8 + help + Whether to include rev F support + +config K8_SCAN_PCI_BUS + hex + default 0 if CPU_AMD_K8 + help + Whether to scan the PCI bus in stage1 + +config K8_ALLOCATE_IO_RANGE + hex + default 0 if CPU_AMD_K8 + help + Whether to allocate IO space in stage1 + +config K8_ALLOCATE_MMIO_RANGE + hex + default 0 if CPU_AMD_K8 + help + Whether to allocate MMIO space in stage1. + Comment from code: + Do we need allocate MMIO? Currently we direct + last 64M to southbridge link (sblink) only, + We can not lose access to last 4M range to ROM. + +config LOGICAL_CPUS + hex + default 1 + help + How many logical CPUs there are. Fix me. + +config MAX_PHYSICAL_CPUS + hex + default 1 + help + Max number of physical CPUs (sockets) + +config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED + hex + default 0 if CPU_AMD_K8 + help + Config with 4 CPUs even if more are installed + +config CROSS_BAR_47_56 + hex + default 0 if CPU_AMD_K8 + help + Configure for the type of crossbar on the mainboard. + config OPTION_TABLE boolean help @@ -93,3 +145,50 @@ default 0x8000 if CPU_AMD_K8 help This option sets the size of the area used for CAR. + +# variables related to AMD Hypertransport. +config HT_CHAIN_UNITID_BASE + hex + default 0 if CPU_AMD_K8 + help + Hypertransport unit ID base value. + Mainboard-dependent. + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 if CPU_AMD_K8 + help + Unit id of the end of hypertransport chain + (usually the real SB); if it is + less than than HT_CHAIN_UNITID_BASE, + it can be 0 + +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + hex + default 1 if CPU_AMD_K8 + help + Determines (I don't understand; ask YHLU) + if only offset SB hypertransport chain + +config SB_HT_CHAIN_ON_BUS0 + hex + default 0 if CPU_AMD_K8 + help + Make SB hypertransport chain sit on bus 0, if it is 1, + will put sb ht chain on bus 0, if it is 2 will + put other chain on 0x40, 0x80, 0xc0 + + +config K8_HT_FREQ_1G_SUPPORT + hex + default 1 if CPU_AMD_K8 + help + 1 Ghz. support. Opteron E0 or later can support + 1G HT, but still depends on the mainboard + +config HT_FREQ_800MHZ + hex + default 1 if CPU_AMD_K8 + help + Can we run HT at 800 Mhz +

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Building a Linux kernel payload of qemu
by yajin 11 Aug '08

11 Aug '08

Hi everyone, I want to build coreboot and linux kernel as a payload. I just followed this wiki article: http://www.coreboot.org/QEMU_Build_Tutorial#Building_a_Linux_kernel_payload. My host system is ubuntu 8.04 on dell vostro 1400 notebook. 1. checkout the coreboot v2 r2405 2. download qemu 0.90 and apply the three patches 3. make linux kernel elf mkelfImage --append="console=ttyS0" --initrd=/boot/initrd.img /boot/vmlinuz linux.elf 4. building coreboot 4.1 Change payload in Confilg.lb to linux.elf 4.2 change option ROM_SIZE to 10*1024*1024 because linux.elf is about 9M. If ROM_SIZE is too small, coreboot will terminate with an error. So I change ROM_SIZE to 10M. 4.3 copy qemu-bios.rom to qemu directory and rename it to bios.bin. 5. build qemu 0.9.0 6. run qemu Because I just want to run coreboot and linux payload, So I do not create hda img for qemu. ./qemu -L . -hda /dev/null -nographic -no-kqemu Qemu exit with error message "qemu: could not load PC bios './bios.bin'" I changed the BIOS_SIZE in vl.h to 11M and qemu did not work too. #define BIOS_SIZE (10240+1024)*1024 But I download the coreboot and payload in http://www.coreboot.org/images/b/b9/Qemu_coreboot_filo.zip, it works. I compare the bios.bin in Qemu_coreboot_filo.zip and the one I created. The one I crated is ELF 32-bit LSB executable and the one in Qemu_coreboot_filo.zip is data. #file qemu-bios.rom qemu-bios.rom: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), statically linked, corrupted section header size #file qemu_coreboot_filo.bin qemu_coreboot_filo.bin: data I think the qemu-bios.rom has wrong format and that is why qemu can not load bios.bin I created. I use objcopy -O binary to get data file of qemu-bios.rom but it outputs an empty file. Any suggestions? How can I build coreboot and linux kernel as payload of qemu. Thanks. ------ yajin http://vm-kernel.org

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fun gotcha
by ron minnich 11 Aug '08

11 Aug '08

if you see this go by: gcc -nostdlib -static -T /home/rminnich/src/bios/coreboot-v3/arch/x86/ldscript.ld \ /home/rminnich/src/bios/coreboot-v3/build/lib/uart8250.o /home/rminnich/src/bios/coreboot-v3/build/lib/mem.o /home/rminnich/src/bios/coreboot-v3/build/lib/lar.o /home/rminnich/src/bios/coreboot-v3/build/lib/delay.o /home/rminnich/src/bios/coreboot-v3/build/lib/vtxprintf.o /home/rminnich/src/bios/coreboot-v3/build/lib/vsprintf.o /home/rminnich/src/bios/coreboot-v3/build/lib/console.o /home/rminnich/src/bios/coreboot-v3/build/lib/string.o /home/rminnich/src/bios/coreboot-v3/build/lib/lzma.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/stage1.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/serial.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/speaker.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/udelay_io.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/mc146818rtc.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/post_code.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/amd/k8/stage1.o /home/rminnich/src/bios/coreboot-v3/build/arch/x86/amd/stage0.o /home/rminnich/src/bios/coreboot-v3/build/mainboard/gigabyte/m57sli/stage1.o /home/rminnich/src/bios/coreboot-v3/build/mainboard/gigabyte/m57sli/option_table.c /home/rminnich/src/bios/coreboot-v3/build/southbridge/nvidia/mcp55/stage1_smbus.o /home/rminnich/src/bios/coreboot-v3/build/mainboard/gigabyte/m57sli/initram.o /home/rminnich/src/bios/coreboot-v3/build/northbridge/amd/k8/raminit.o /home/rminnich/src/bios/coreboot-v3/build/northbridge/amd/k8/coherent_ht.o /home/rminnich/src/bios/coreboot-v3/build/northbridge/amd/k8/incoherent_ht.o /home/rminnich/src/bios/coreboot-v3/build/southbridge/nvidia/mcp55/stage1.o /home/rminnich/src/bios/coreboot-v3/build/southbridge/nvidia/mcp55/stage1_smbus.o /home/rminnich/src/bios/coreboot-v3/build/southbridge/nvidia/mcp55/stage1.o /home/rminnich/src/bios/coreboot-v3/build/superio/ite/it8716f/stage1.o /home/rminnich/src/bios/coreboot-v3/build/device/pnp_raw.o -o /home/rminnich/src/bios/coreboot-v3/build/stage0.o You will get this error: as: unrecognized option `-T' Why that error? This is a link step, right? Not quite: There is a .c in that list: /home/rminnich/src/bios/coreboot-v3/build/mainboard/gigabyte/m57sli/option_table.c and that does it. Hardly intuitive, but worth knowing. Now what broke the coreboot build process, I am not yet sure. ron

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[PATCH] [buildrom] fix LAB and kernel payload build post v210
by Ward Vandewege 11 Aug '08

11 Aug '08

See attached. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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r219 - in buildrom-devel/packages: busybox kernel
by svn＠coreboot.org 11 Aug '08

11 Aug '08

Author: ward Date: 2008-08-11 17:01:35 +0200 (Mon, 11 Aug 2008) New Revision: 219 Modified: buildrom-devel/packages/busybox/busybox.mk buildrom-devel/packages/kernel/kernel.inc Log: Buildrom rev 210 (the upgrade to the latest kconfig) broke kernel and LAB payload build quite spectacularly. It did so by introducing extra environment variables needed for kconfig which do not agree with the kernel and LAB payload build process. The attached patch fixes that. Not tested on real hardware yet. But since this makes buildrom build again, this is certainly an improvement over the status quo, I would argue. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/packages/busybox/busybox.mk =================================================================== --- buildrom-devel/packages/busybox/busybox.mk 2008-08-09 23:10:31 UTC (rev 218) +++ buildrom-devel/packages/busybox/busybox.mk 2008-08-11 15:01:35 UTC (rev 219) @@ -46,7 +46,7 @@ ifneq ($(findstring defconfig,$(BUSYBOX_CONFIG)),defconfig) @ echo "Using custom config $(PACKAGE_DIR)/busybox/conf/$(BUSYBOX_CONFIG)" endif - @ ( unset CFLAGS; unset LDFLAGS; \ + @ ( unset MAKEFLAGS; unset CFLAGS; unset LDFLAGS; \ export EXTRA_CFLAGS="$(CFLAGS)";\ export LDFLAGS="$(LDFLAGS_orig)";\ $(MAKE) -C $(BUSYBOX_SRC_DIR) VERBOSE=y \ Modified: buildrom-devel/packages/kernel/kernel.inc =================================================================== --- buildrom-devel/packages/kernel/kernel.inc 2008-08-09 23:10:31 UTC (rev 218) +++ buildrom-devel/packages/kernel/kernel.inc 2008-08-11 15:01:35 UTC (rev 219) @@ -61,8 +61,9 @@ ifneq ($(findstring defconfig,$(KERNEL_CONFIG)),defconfig) @ echo "Using custom kernel config $(KERNEL_CONFIG)" endif - @ $(MAKE) $(PARALLEL_MAKE) -C $(KERNEL_SRC_DIR) ARCH=$(KERNEL_BUILD_ARCH) \ - KERNEL_CC="$(CC)" KERNEL_LD="$(LD)" > $(KERNEL_BUILD_LOG) 2>&1 + @ (unset KCONFIG_AUTOHEADER; unset KCONFIG_AUTOCONFIG; \ + $(MAKE) $(PARALLEL_MAKE) -C $(KERNEL_SRC_DIR) ARCH=$(KERNEL_BUILD_ARCH) \ + KERNEL_CC="$(CC)" KERNEL_LD="$(LD)" > $(KERNEL_BUILD_LOG) 2>&1) @ mkdir -p $(OUTPUT_DIR)/config/kernel @ cp $(KERNEL_SRC_DIR)/.config $(OUTPUT_DIR)/config/kernel/

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[PATCH] libpayload: fix VGA and serial IO breakage
by Ulf Jordan 11 Aug '08

11 Aug '08

Hello, Since r3482 I have not had any VGA or serial IO from libpayload. The reason seems to be that the CONFIG_ macros generated by kconfig are never made available to the C source files during compilation. Before r3482 the CONFIG_ macros were obtained by including autoconf.h in libpayload.h. In the attached patch, config.h from the new kconfig is included in libpayload.h, but I'm not quite sure if this is the appropriate place. Compile tested against libpayload+coreinfo svn HEAD. Runtime tested with libpayload+coreinfo+coreboot-v3 in QEMU. /ulf

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coreboot August 2008