coreboot August 2008

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r732 - in coreboot-v3/include: arch/x86/amd/k8 device
by svn＠coreboot.org 10 Aug '08

10 Aug '08

Author: rminnich Date: 2008-08-11 00:02:15 +0200 (Mon, 11 Aug 2008) New Revision: 732 Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h coreboot-v3/include/device/pci_ids.h Log: Add needed defines for k8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h =================================================================== --- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-10 21:20:46 UTC (rev 731) +++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-10 22:02:15 UTC (rev 732) @@ -298,6 +298,11 @@ #define RES_PORT_IO_32 0x20 #define RES_MEM_IO 0x40 +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) + #ifndef ASSEMBLY /* cpu version -- no support for f0 yet */ static inline int is_cpu_rev_a0(void) @@ -379,6 +384,7 @@ struct mem_controller { unsigned node_id; + /* NOTE: these are in "BDF" format -- i.e. bus in upper 16, devfn in upper 8 of lower 16 */ u32 f0, f1, f2, f3; u32 channel0[DIMM_SOCKETS]; u32 channel1[DIMM_SOCKETS]; Modified: coreboot-v3/include/device/pci_ids.h =================================================================== --- coreboot-v3/include/device/pci_ids.h 2008-08-10 21:20:46 UTC (rev 731) +++ coreboot-v3/include/device/pci_ids.h 2008-08-10 22:02:15 UTC (rev 732) @@ -141,7 +141,57 @@ /* Vendors and devices. Sort key: vendor first, device next. */ #define PCI_VENDOR_ID_AMD 0x1022 -#define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080 +#define PCI_VENDOR_ID_AMD 0x1022 +#define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_LANCE_HOME 0x2001 +#define PCI_DEVICE_ID_AMD_LX 0x1054 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 +#define PCI_DEVICE_ID_AMD_FE_GATE_7006 0x7006 +#define PCI_DEVICE_ID_AMD_FE_GATE_7007 0x7007 +#define PCI_DEVICE_ID_AMD_FE_GATE_700C 0x700C +#define PCI_DEVIDE_ID_AMD_FE_GATE_700D 0x700D +#define PCI_DEVICE_ID_AMD_FE_GATE_700E 0x700E +#define PCI_DEVICE_ID_AMD_FE_GATE_700F 0x700F +#define PCI_DEVICE_ID_AMD_COBRA_7400 0x7400 +#define PCI_DEVICE_ID_AMD_COBRA_7401 0x7401 +#define PCI_DEVICE_ID_AMD_COBRA_7403 0x7403 +#define PCI_DEVICE_ID_AMD_COBRA_7404 0x7404 +#define PCI_DEVICE_ID_AMD_VIPER_7408 0x7408 +#define PCI_DEVICE_ID_AMD_VIPER_7409 0x7409 +#define PCI_DEVICE_ID_AMD_VIPER_740B 0x740B +#define PCI_DEVICE_ID_AMD_VIPER_740C 0x740C +#define PCI_DEVICE_ID_AMD_VIPER_7410 0x7410 +#define PCI_DEVICE_ID_AMD_VIPER_7411 0x7411 +#define PCI_DEVICE_ID_AMD_SB768_7440 0x7440 +#define PCI_DEVICE_ID_AMD_SB768_7441 0x7441 +#define PCI_DEVICE_ID_AMD_SB768_7443 0x7443 +#define PCI_DEVICE_ID_AMD_SB768_7448 0x7448 +#define PCI_DEVICE_ID_AMD_SB768_7449 0x7449 +#define PCI_DEVICE_ID_AMD_VIPER_7413 0x7413 +#define PCI_DEVICE_ID_AMD_VIPER_7414 0x7414 +#define PCI_DEVICE_ID_AMD_VIPER_7440 0x7440 +#define PCI_DEVICE_ID_AMD_VIPER_7441 0x7441 +#define PCI_DEVICE_ID_AMD_VIPER_7443 0x7443 +#define PCI_DEVICE_ID_AMD_VIPER_7448 0x7448 +#define PCI_DEVICE_ID_AMD_VIPER_7449 0x7449 +#define PCI_DEVICE_ID_AMD_8151_SYSCTRL 0x7454 +#define PCI_DEVICE_ID_AMD_8151_AGP 0x7455 +#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460 +#define PCI_DEVICE_ID_AMD_8111_USB 0x7464 +#define PCI_DEVICE_ID_AMD_8111_ISA 0x7468 +#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 +#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a +#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b +#define PCI_DEVICE_ID_AMD_8111_NIC 0x7462 +#define PCI_DEVICE_ID_AMD_8111_USB2 0x7463 +#define PCI_DEVICE_ID_AMD_8131_PCIX 0x7450 +#define PCI_DEVICE_ID_AMD_8131_IOAPIC 0x7451 +#define PCI_DEVICE_ID_AMD_8132_PCIX 0x7458 +#define PCI_DEVICE_ID_AMD_8132_IOAPIC 0x7459 +#define PCI_DEVICE_ID_AMD_AES 0x2082 +#define PCI_DEVICE_ID_AMD_761_0 0x700E +#define PCI_DEVICE_ID_AMD_761_1 0x700F +#define PCI_DEVICE_ID_AMD_VIPER_7412 0x7412#define PCI_DEVICE_ID_AMD_LXBRIDGE 0x2080 #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 #define PCI_DEVICE_ID_AMD_CS5536_A0_IDE 0x2092

1 0

r731 - coreboot-v3/southbridge/nvidia/mcp55
by svn＠coreboot.org 10 Aug '08

10 Aug '08

Author: rminnich Date: 2008-08-10 23:20:46 +0200 (Sun, 10 Aug 2008) New Revision: 731 Added: coreboot-v3/southbridge/nvidia/mcp55/stage1.h coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c Log: Add stage1.h to the files for standard defines used by all stage1 functions. Modify all functions to use the new v3 pci operations calling conventions. use udelay for delays. Add the USB debug support function. This is compiling pretty well for me save for the missing hypertransport function. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-10 00:20:24 UTC (rev 730) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.c 2008-08-10 21:20:46 UTC (rev 731) @@ -26,20 +26,20 @@ #include <cpu.h> #include <amd/k8/k8.h> #include "mcp55.h" -#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where) -#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what) +#include "stage1.h" #warning fix disgusting define of MCP55_NUM it is mainboard dependent #define MCP55_NUM 1 -static int set_ht_link_mcp55(u8 ht_c_num) +int set_ht_link_mcp55(u8 ht_c_num) { + int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); unsigned vendorid = 0x10de; unsigned val = 0x01610109; /* Nvidia mcp55 hardcode, hw can not set it automatically */ return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); } -static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) +void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) { int i; @@ -139,14 +139,6 @@ } -static void delayx(u8 value) { -#if 1 - int i; - for(i=0;i<0x8000;i++) { - outb(value, 0x80); - } -#endif -} static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { @@ -154,11 +146,10 @@ u32 pll_ctrl; u32 dword; int i; - u32 dev; - // dev = PCI_BDF(busnx, devnx+1, 1); - dword = pci_read_config32(busnx, (devnx+1)<<3 | 1, 0xe4); + u32 bdf = PCI_BDF(busnx, devnx+1, 1); + dword = pci_read_config32(bdf, 0xe4); dword |= 0x3f0; // disable it at first - pci_write_config32(busnx, (devnx+1)<<3 | 1, 0xe4, dword); + pci_write_config32(bdf, 0xe4, dword); for(i=0; i<3; i++) { tgio_ctrl = inl(anactrl_io_base + 0xcc); @@ -178,14 +169,14 @@ outl(tgio_ctrl, anactrl_io_base + 0xcc); // wait 100us - delayx(1); + udelay(100); - dword = pci_read_config32(busnx, (devnx+1)<<3 | 1, 0xe4); + dword = pci_read_config32(bdf, 0xe4); dword &= ~(0x3f0); // enable - pci_write_config32(busnx, (devnx+1)<<3 | 1, 0xe4, dword); + pci_write_config32(bdf, 0xe4, dword); // need to wait 100ms - delayx(1000); + udelay(100000); } static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) @@ -380,7 +371,7 @@ #endif -static int mcp55_early_setup_x(void) +int mcp55_early_setup_x(void) { /*find out how many mcp55 we have */ unsigned busn[HT_CHAIN_NUM_MAX]; @@ -403,8 +394,9 @@ busnx = ht_c_index * HT_CHAIN_BUSN_D; for(devnx=0;devnx<0x20;devnx++) { u32 id; - // dev = PCI_BDF(busnx, devnx, 0); - id = pci_read_config32(busnx, devnx<<3, PCI_VENDOR_ID); + u32 bdf; + bdf = PCI_BDF(busnx, devnx, 0); + id = pci_read_config32(bdf, PCI_VENDOR_ID); if(id == 0x036910de) { busn[mcp55_num] = busnx; devn[mcp55_num] = devnx; @@ -431,4 +423,49 @@ } +/* this was in separate file but I am trying to gather the utility junk + * into one file. + */ +unsigned int get_sbdn(unsigned int bus) +{ +#warning bus ignore in get_sbdn; do we care + /* Find the device. + */ + u32 bdf; + if (!pci_locate_device(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_MCP55_HT, &bdf)) { + die("PCI_DEVICE_ID_NVIDIA_MCP55_HT not found\r\n"); + } + + return (bdf>>15) & 0x1f; + +} + +void hard_reset(void) +{ +#warning what is set_bios_reset +// set_bios_reset(); + + /* full reset */ + outb(0x0a, 0x0cf9); + outb(0x0e, 0x0cf9); +} + +void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) +{ +/* default value for mcp55 is good */ + /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + +} + +void soft_reset(void) +{ +#warning what is set_bios_reset +// set_bios_reset(); +#if 1 + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +#endif +} + Added: coreboot-v3/southbridge/nvidia/mcp55/stage1.h =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1.h (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1.h 2008-08-10 21:20:46 UTC (rev 731) @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#define pci_read_config32(bdf, where) pci_cf8_conf1.read32(bdf, where) +#define pci_write_config32(bdf, where, what) pci_cf8_conf1.write32(bdf, where, what) +#define pci_read_config16(bdf, where) pci_cf8_conf1.read32(bdf, where) +#define pci_write_config16(bdf, where, what) pci_cf8_conf1.write32(bdf, where, what) +#define pci_locate_device(vid, did, slot) pci_cf8_conf1.find(vid, did, slot) Modified: coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-08-10 00:20:24 UTC (rev 730) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_smbus.c 2008-08-10 21:20:46 UTC (rev 731) @@ -5,6 +5,7 @@ * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. * Copyright (C) 2006,2007 AMD * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2008 Ronald G. Minnich (for v3) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,73 +27,222 @@ #include <device/device.h> #include <device/pci.h> #include "mcp55.h" -#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where) -#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what) -#define pci_read_config16(bus, dev, where) pci_cf8_conf1.read32(NULL, bus, dev, where) -#define pci_write_config16(bus, dev, where, what) pci_cf8_conf1.write32(NULL, bus, dev, where, what) +#include "stage1.h" #include "mcp55_smbus.h" #define SMBUS0_IO_BASE 0x1000 #define SMBUS1_IO_BASE (0x1000+(1<<8)) /*SIZE 0x40 */ -static void enable_smbus(void) +int smbus_wait_until_ready(u16 smbus_io_base) { - u32 dev; - dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); -#if 0 - if (dev == PCI_DEV_INVALID) { + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { + return 0; + } + outb(val,smbus_io_base + SMBHSTSTAT); + } while(--loops); + return -2; +} + +int smbus_wait_until_done(u16 smbus_io_base) +{ + unsigned long loops; + loops = SMBUS_TIMEOUT; + do { + unsigned char val; + smbus_delay(); + + val = inb(smbus_io_base + SMBHSTSTAT); + if ( (val & 0xff) != 0) { + return 0; + } + } while(--loops); + return -3; +} + +int do_smbus_recv_byte(u16 smbus_io_base, u8 device) +{ + u8 global_status_register; + u8 byte; + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* byte data recv */ + outb(0x05, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + if (global_status_register != 0x80) { // loose check, otherwise it should be 0 + return -1; + } + return byte; +} + +int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val) +{ + u8 global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x04, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + +int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address) +{ + u8 global_status_register; + u8 byte; + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBXMITADD); + smbus_delay(); + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + /* byte data read */ + outb(0x07, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */ + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + if (global_status_register != 0x80) { // lose check, otherwise it should be 0 + return -1; + } + return byte; +} + +int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val) +{ + u8 global_status_register; + + outb(val, smbus_io_base + SMBHSTDAT0); + smbus_delay(); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBXMITADD); + smbus_delay(); + + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + smbus_delay(); + + /* set up for a byte data write */ + outb(0x06, smbus_io_base + SMBHSTPRTCL); + smbus_delay(); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; + } + global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; /* lose check */; + + if (global_status_register != 0x80) { + return -1; + } + return 0; +} + + +void enable_smbus(void) +{ + u32 bdf; + if (!pci_locate_device(0x10de, 0x0368, &bdf)) { die("SMBUS controller not found\r\n"); } - printk(BIOS_DEBUG, "SMBus controller enabled\r\n"); -#endif + printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ - pci_write_config32(0, dev, 0x20, SMBUS0_IO_BASE | 1); - pci_write_config32(0, dev, 0x24, SMBUS1_IO_BASE | 1); + pci_write_config32(bdf, 0x20, SMBUS0_IO_BASE | 1); + pci_write_config32(bdf, 0x24, SMBUS1_IO_BASE | 1); /* Set smbus iospace enable */ - pci_write_config16(0, dev, 0x4, 0x01); + pci_write_config16(bdf, 0x4, 0x01); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT); outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT); } -static u8 smbus_recv_byte(u8 device) +u8 smbus_recv_byte(u8 device) { return do_smbus_recv_byte(SMBUS0_IO_BASE, device); } -static u8 smbus_send_byte(u8 device,u8 val) +u8 smbus_send_byte(u8 device,u8 val) { return do_smbus_send_byte(SMBUS0_IO_BASE, device, val); } -static u8 smbus_read_byte(u8 device, u8 address) +u8 smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); } -static u8 smbus_write_byte(u8 device, u8 address, u8 val) +u8 smbus_write_byte(u8 device, u8 address, u8 val) { return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); } -static u8 smbusx_recv_byte(u8 smb_index, u8 device) +u8 smbusx_recv_byte(u8 smb_index, u8 device) { return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device); } -static u8 smbusx_send_byte(u8 smb_index, u8 device, u8 val) +u8 smbusx_send_byte(u8 smb_index, u8 device, u8 val) { return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val); } -static u8 smbusx_read_byte(u8 smb_index, u8 device, u8 address) +u8 smbusx_read_byte(u8 smb_index, u8 device, u8 address) { return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address); } -static u8 smbusx_write_byte(u8 smb_index, u8 device, u8 address, u8 val) +u8 smbusx_write_byte(u8 smb_index, u8 device, u8 address, u8 val) { return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val); } Added: coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c (rev 0) +++ coreboot-v3/southbridge/nvidia/mcp55/stage1_usbdebug.c 2008-08-10 21:20:46 UTC (rev 731) @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan Computer. + * Copyright (C) 2006,2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This should probably be a config variable. */ +#if HT_CHAIN_END_UNITID_BASE != 0x20 + #define MCP55_DEVN_BASE HT_CHAIN_END_UNITID_BASE +#else + #define MCP55_DEVN_BASE HT_CHAIN_UNITID_BASE +#endif + +#define EHCI_BAR_INDEX 0x10 +#define EHCI_BAR 0xFEF00000 +#define EHCI_DEBUG_OFFSET 0x98 + +#include "pci.h" +#include "stage1.h" +static void set_debug_port(unsigned port) +{ + u32 dword; + u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1); + dword = pci_read_config32(bdf, 0x74); + dword &= ~(0xf<<12); + dword |= (port<<12); + pci_write_config32(bdf, 0x74, dword); + +} + +static void mcp55_enable_usbdebug_direct(unsigned port) +{ + u32 bdf = PCI_BDF(0, MCP55_DEVN_BASE+2, 1); + set_debug_port(port); + pci_write_config32(bdf, EHCI_BAR_INDEX, EHCI_BAR); + pci_write_config8(bdf, 0x04, 0x2); // mem space enable +} +

1 0

patch: resource map proposal.
by ron minnich 10 Aug '08

10 Aug '08

This is a possible mod to change the way resource maps are done. Unify the big mess into a little mess. This code has all the functionality of the 4 or 5 rmap functions from v2 .. This includes my proposed pci config patch. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>

6 22

[PATCH] v3: move to anonymous unions
by Carl-Daniel Hailfinger 10 Aug '08

10 Aug '08

The named unions in the device tree code are obnoxious and degrade readability. Move to anonymous unions. Build tested on all targets. Boot tested on qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c =================================================================== --- corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c (Revision 716) +++ corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -696,7 +696,7 @@ struct device_operations cs5536_ops = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, @@ -708,7 +708,7 @@ struct device_operations cs5536_ide = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, .constructor = default_device_constructor, #warning FIXME: what has to go in phase3_scan? Index: corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c (Revision 716) +++ corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie) @@ -45,10 +45,11 @@ /* the range makes it hard to use the library function. Sorry. * I realize this is not pretty. It would be nice if we could * use anonymous unions. + * We now use anonymous unions. Fix up the code? */ - if ((lpc_dev->id.u.pci.vendor != PCI_VENDOR_ID_NVIDIA) || ( - (lpc_dev->id.u.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || - (lpc_dev->id.u.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) + if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA) || ( + (lpc_dev->id.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || + (lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) ) ) { u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); @@ -80,16 +81,16 @@ unsigned devfn; /* sorry. Again, anonymous unions etc. would make this easier. */ - if(dev->id.u.pci.device==0x0000) { + if(dev->id.pci.device==0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; // vendorid &= 0xffff; } else { // vendorid = dev->vendor; - deviceid = dev->id.u.pci.device; + deviceid = dev->id.pci.device; } - devfn = (dev->path.u.pci.devfn) & ~7; + devfn = (dev->path.pci.devfn) & ~7; switch(deviceid) { case PCI_DEVICE_ID_NVIDIA_MCP55_HT: return; @@ -129,7 +130,7 @@ case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three devfn -= (4<<3); index = 22; - i = (dev->path.u.pci.devfn) & 7; + i = (dev->path.pci.devfn) & 7; if(i>0) { index -= (i+3); } @@ -249,7 +250,7 @@ struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, Index: corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c (Revision 716) +++ corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c (Arbeitskopie) @@ -85,7 +85,7 @@ /* You can override or extend each operation as needed for the device. */ struct device_operations i82371eb_isa = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7000}}}, + {.pci = {.vendor = 0x8086,.device = 0x7000}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, @@ -98,7 +98,7 @@ struct device_operations i82371eb_ide = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7010}}}, + {.pci = {.vendor = 0x8086,.device = 0x7010}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, @@ -111,7 +111,7 @@ struct device_operations i82371eb_acpi = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7113}}}, + {.pci = {.vendor = 0x8086,.device = 0x7113}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, Index: corebootv3-anonymous_unions/include/device/path.h =================================================================== --- corebootv3-anonymous_unions/include/device/path.h (Revision 716) +++ corebootv3-anonymous_unions/include/device/path.h (Arbeitskopie) @@ -100,7 +100,7 @@ struct cpu_path cpu; struct cpu_bus_path cpu_bus; struct ioport_path ioport; - } u; + }; }; Index: corebootv3-anonymous_unions/include/device/device.h =================================================================== --- corebootv3-anonymous_unions/include/device/device.h (Revision 716) +++ corebootv3-anonymous_unions/include/device/device.h (Arbeitskopie) @@ -108,7 +108,7 @@ struct apic_cluster_id apic_cluster; struct cpu_id cpu; struct cpu_bus_id cpu_bus; - } u; + }; }; Index: corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c =================================================================== --- corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c (Revision 716) +++ corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c (Arbeitskopie) @@ -36,13 +36,13 @@ static void pnp_enter_ext_func_mode(struct device * dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } static void pnp_exit_ext_func_mode(struct device * dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void pnp_write_index(u16 port_base, u8 reg, u8 value) @@ -73,7 +73,7 @@ #warning Fix CMOS handling // get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); - pnp_write_index(dev->path.u.pnp.port,7,0x0a); + pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); value &= ~(3<<5); if(power_on) { @@ -128,7 +128,7 @@ } conf = dev->device_configuration; - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627HF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); #warning init_uart8250 @@ -167,7 +167,7 @@ { pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627HF_HWM: printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n"); enable_hwm_smbus(dev); Index: corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c =================================================================== --- corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c (Revision 716) +++ corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c (Arbeitskopie) @@ -41,12 +41,12 @@ static void pnp_enter_conf_state(struct device *dev) { - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); } static void pnp_exit_conf_state(struct device *dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } void f71805f_pnp_set_resources(struct device *dev) @@ -79,7 +79,7 @@ if (!dev->enabled) return; - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case F71805F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); //TODO: needed? fix or remove? Index: corebootv3-anonymous_unions/superio/ite/it8716f/superio.c =================================================================== --- corebootv3-anonymous_unions/superio/ite/it8716f/superio.c (Revision 716) +++ corebootv3-anonymous_unions/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -37,14 +37,14 @@ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(struct device *dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x01, dev->path.u.pnp.port); - outb(0x55, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x01, dev->path.pnp.port); + outb(0x55, dev->path.pnp.port); - if (dev->path.u.pnp.port == 0x4e) { - outb(0xaa, dev->path.u.pnp.port); + if (dev->path.pnp.port == 0x4e) { + outb(0xaa, dev->path.pnp.port); } else { - outb(0x55, dev->path.u.pnp.port); + outb(0x55, dev->path.pnp.port); } } @@ -142,7 +142,7 @@ conf = dev->device_configuration; /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case IT8716F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); // init_uart8250(res0->base, &conf->com1); Index: corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c =================================================================== --- corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c (Revision 716) +++ corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c (Arbeitskopie) @@ -44,7 +44,7 @@ struct device_operations qemuvga_pci_ops_dev = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS, + {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS, .device = PCI_DEVICE_ID_CIRRUS_5446}}}, .constructor = default_device_constructor, .phase3_scan = 0, Index: corebootv3-anonymous_unions/device/pcie_device.c =================================================================== --- corebootv3-anonymous_unions/device/pcie_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pcie_device.c (Arbeitskopie) @@ -42,8 +42,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pcie_tune_dev(child); Index: corebootv3-anonymous_unions/device/hypertransport.c =================================================================== --- corebootv3-anonymous_unions/device/hypertransport.c (Revision 716) +++ corebootv3-anonymous_unions/device/hypertransport.c (Arbeitskopie) @@ -50,7 +50,7 @@ */ while (last && last->sibling && (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) { + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } if (first) { @@ -344,7 +344,7 @@ u32 id; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = PCI_DEVFN(0, 0); + dummy.path.pci.devfn = PCI_DEVFN(0, 0); id = pci_read_config32(&dummy, PCI_VENDOR_ID); if (!((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000))) { @@ -361,7 +361,7 @@ unsigned int pos, flags; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = devfn; + dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { @@ -498,9 +498,9 @@ /* Update the unitid in the device structure. */ static_count = 1; for (func = dev; func; func = func->sibling) { - func->path.u.pci.devfn += (next_unitid << 3); - static_count = (func->path.u.pci.devfn >> 3) - - (dev->path.u.pci.devfn >> 3) + 1; + func->path.pci.devfn += (next_unitid << 3); + static_count = (func->path.pci.devfn >> 3) + - (dev->path.pci.devfn >> 3) + 1; last_func = func; } @@ -557,7 +557,7 @@ flags); for (func = real_last_dev; func; func = func->sibling) { - func->path.u.pci.devfn -= + func->path.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3); last_func = func; Index: corebootv3-anonymous_unions/device/pnp_device.c =================================================================== --- corebootv3-anonymous_unions/device/pnp_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pnp_device.c (Arbeitskopie) @@ -32,19 +32,19 @@ void pnp_write_config(struct device *dev, u8 reg, u8 value) { - outb(reg, dev->path.u.pnp.port); - outb(value, dev->path.u.pnp.port + 1); + outb(reg, dev->path.pnp.port); + outb(value, dev->path.pnp.port + 1); } u8 pnp_read_config(struct device *dev, u8 reg) { - outb(reg, dev->path.u.pnp.port); - return inb(dev->path.u.pnp.port + 1); + outb(reg, dev->path.pnp.port); + return inb(dev->path.pnp.port + 1); } void pnp_set_logical_device(struct device *dev) { - pnp_write_config(dev, 0x07, dev->path.u.pnp.device); + pnp_write_config(dev, 0x07, dev->path.pnp.device); } void pnp_set_enable(struct device *dev, int enable) @@ -238,11 +238,11 @@ int i; path.type = DEVICE_PATH_PNP; - path.u.pnp.port = base_dev->path.u.pnp.port; + path.pnp.port = base_dev->path.pnp.port; /* Setup the ops and resources on the newly allocated devices. */ for (i = 0; i < functions; i++) { - path.u.pnp.device = info[i].function; + path.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path, &id); /* Don't initialize a device multiple times. */ Index: corebootv3-anonymous_unions/device/pcix_device.c =================================================================== --- corebootv3-anonymous_unions/device/pcix_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pcix_device.c (Arbeitskopie) @@ -66,8 +66,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pcix_tune_dev(child); Index: corebootv3-anonymous_unions/device/agp_device.c =================================================================== --- corebootv3-anonymous_unions/device/agp_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/agp_device.c (Arbeitskopie) @@ -40,8 +40,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } agp_tune_dev(child); Index: corebootv3-anonymous_unions/device/pci_rom.c =================================================================== --- corebootv3-anonymous_unions/device/pci_rom.c (Revision 716) +++ corebootv3-anonymous_unions/device/pci_rom.c (Arbeitskopie) @@ -45,8 +45,8 @@ * or readonly. */ init_archive(&archive); - sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor, - dev->id.u.pci.device); + sprintf(pcifile, "pci%04x,%04x.rom", dev->id.pci.vendor, + dev->id.pci.device); ret = find_file(&archive, pcifile, &result); if (ret) { @@ -108,7 +108,7 @@ printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); - if (dev->id.u.pci.vendor != rom_data->vendor || dev->id.u.pci.device != rom_data->device) { + if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) { printk(BIOS_ERR, "Device or Vendor ID mismatch Vendor %04x, Device %04x\n", rom_data->vendor, rom_data->device); Index: corebootv3-anonymous_unions/device/pci_device.c =================================================================== --- corebootv3-anonymous_unions/device/pci_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pci_device.c (Arbeitskopie) @@ -894,8 +894,8 @@ continue; } printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n", - __func__, (*list)->dtsname, (*list)->path.u.pci.devfn); - if ((*list)->path.u.pci.devfn == devfn) { + __func__, (*list)->dtsname, (*list)->path.pci.devfn); + if ((*list)->path.pci.devfn == devfn) { /* Unlink from the list. */ dev = *list; *list = (*list)->sibling; @@ -948,7 +948,7 @@ struct device_id devid; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = devfn; + dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); /* Have we found something? * Some broken boards return 0 if a slot is empty. @@ -960,8 +960,8 @@ return NULL; } devid.type = DEVICE_ID_PCI; - devid.u.pci.vendor = id & 0xffff; - devid.u.pci.device = id >> 16; + devid.pci.vendor = id & 0xffff; + devid.pci.device = id >> 16; dev = alloc_dev(bus, &dummy.path, &devid); } else { /* Enable/disable the device. Once we have found the device @@ -1013,8 +1013,8 @@ /* Store the interesting information in the device structure. */ dev->id.type = DEVICE_ID_PCI; - dev->id.u.pci.vendor = id & 0xffff; - dev->id.u.pci.device = (id >> 16) & 0xffff; + dev->id.pci.vendor = id & 0xffff; + dev->id.pci.device = (id >> 16) & 0xffff; dev->hdr_type = hdr_type; /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */ dev->class = class >> 8; Index: corebootv3-anonymous_unions/device/device_util.c =================================================================== --- corebootv3-anonymous_unions/device/device_util.c (Revision 716) +++ corebootv3-anonymous_unions/device/device_util.c (Arbeitskopie) @@ -81,7 +81,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && (dev->bus->secondary == bus) && - (dev->path.u.pci.devfn == devfn)) { + (dev->path.pci.devfn == devfn)) { result = dev; break; } @@ -104,7 +104,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_I2C) && (dev->bus->secondary == bus) && - (dev->path.u.i2c.device == addr)) { + (dev->path.i2c.device == addr)) { result = dev; break; } @@ -155,8 +155,8 @@ struct device_id id; id.type = DEVICE_ID_PCI; - id.u.pci.vendor = vendor; - id.u.pci.device = device; + id.pci.vendor = vendor; + id.pci.device = device; return dev_find_device(&id, from); } @@ -197,48 +197,48 @@ sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", dev->bus->secondary >> 8, dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.u.pci.devfn), - PCI_FUNC(dev->path.u.pci.devfn)); + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #else sprintf(buffer, "PCI: %02x:%02x.%01x", dev->bus->secondary, - PCI_SLOT(dev->path.u.pci.devfn), - PCI_FUNC(dev->path.u.pci.devfn)); + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #endif break; case DEVICE_PATH_PNP: sprintf(buffer, "PNP: %04x.%01x", - dev->path.u.pnp.port, dev->path.u.pnp.device); + dev->path.pnp.port, dev->path.pnp.device); break; case DEVICE_PATH_I2C: sprintf(buffer, "I2C: %02x:%02x", - dev->bus->secondary, dev->path.u.i2c.device); + dev->bus->secondary, dev->path.i2c.device); break; case DEVICE_PATH_APIC: - sprintf(buffer, "APIC: %02x", dev->path.u.apic.apic_id); + sprintf(buffer, "APIC: %02x", dev->path.apic.apic_id); break; case DEVICE_PATH_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x", - dev->path.u.pci_domain.domain); + dev->path.pci_domain.domain); break; case DEVICE_PATH_PCI_BUS: sprintf(buffer, "PCI_BUS: %04x", - dev->path.u.pci_bus.bus); + dev->path.pci_bus.bus); break; case DEVICE_PATH_APIC_CLUSTER: sprintf(buffer, "APIC_CLUSTER: %01x", - dev->path.u.apic_cluster.cluster); + dev->path.apic_cluster.cluster); break; case DEVICE_PATH_CPU: - sprintf(buffer, "CPU: %02x", dev->path.u.cpu.id); + sprintf(buffer, "CPU: %02x", dev->path.cpu.id); break; case DEVICE_PATH_CPU_BUS: sprintf(buffer, "CPU_BUS: %02x", - dev->path.u.cpu_bus.id); + dev->path.cpu_bus.id); break; case DEVICE_PATH_IOPORT: sprintf(buffer, "IOPORT: %02x", - dev->path.u.ioport.iobase); + dev->path.ioport.iobase); break; default: printk(BIOS_ERR, "%s: Unknown device path type: %d\n", @@ -262,36 +262,36 @@ memcpy(buffer, "Root Device", 12); break; case DEVICE_ID_PCI: - sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor, - id->u.pci.device); + sprintf(buffer, "PCI: %04x:%04x", id->pci.vendor, + id->pci.device); break; case DEVICE_ID_PNP: - sprintf(buffer, "PNP: %04x", id->u.pnp.device); + sprintf(buffer, "PNP: %04x", id->pnp.device); break; case DEVICE_ID_I2C: - sprintf(buffer, "I2C: %04x", id->u.i2c.id); + sprintf(buffer, "I2C: %04x", id->i2c.id); break; case DEVICE_ID_APIC: - sprintf(buffer, "APIC: %02x:%02x", id->u.apic.vendor, - id->u.apic.device); + sprintf(buffer, "APIC: %02x:%02x", id->apic.vendor, + id->apic.device); break; case DEVICE_ID_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x:%04x", - id->u.pci_domain.vendor, - id->u.pci_domain.device); + id->pci_domain.vendor, + id->pci_domain.device); break; case DEVICE_ID_APIC_CLUSTER: sprintf(buffer, "APIC_CLUSTER: %02x:%02x", - id->u.apic_cluster.vendor, - id->u.apic_cluster.device); + id->apic_cluster.vendor, + id->apic_cluster.device); break; case DEVICE_ID_CPU: - sprintf(buffer, "CPU", id->u.cpu.cpuid[0], - id->u.cpu.cpuid[1], id->u.cpu.cpuid[2]); + sprintf(buffer, "CPU", id->cpu.cpuid[0], + id->cpu.cpuid[1], id->cpu.cpuid[2]); break; case DEVICE_ID_CPU_BUS: sprintf(buffer, "CPU_BUS: %02x:%02x", - id->u.cpu_bus.vendor, id->u.cpu_bus.device); + id->cpu_bus.vendor, id->cpu_bus.device); break; default: printk(BIOS_ERR, "%s: Unknown device ID type: %d\n", @@ -321,34 +321,34 @@ equal = 1; break; case DEVICE_PATH_PCI: - equal = (path1->u.pci.devfn == path2->u.pci.devfn); + equal = (path1->pci.devfn == path2->pci.devfn); break; case DEVICE_PATH_PNP: - equal = (path1->u.pnp.port == path2->u.pnp.port) && - (path1->u.pnp.device == path2->u.pnp.device); + equal = (path1->pnp.port == path2->pnp.port) && + (path1->pnp.device == path2->pnp.device); break; case DEVICE_PATH_I2C: - equal = (path1->u.i2c.device == path2->u.i2c.device); + equal = (path1->i2c.device == path2->i2c.device); break; case DEVICE_PATH_APIC: equal = - (path1->u.apic.apic_id == path2->u.apic.apic_id); + (path1->apic.apic_id == path2->apic.apic_id); break; case DEVICE_PATH_PCI_DOMAIN: equal = - (path1->u.pci_domain.domain == - path2->u.pci_domain.domain); + (path1->pci_domain.domain == + path2->pci_domain.domain); break; case DEVICE_PATH_APIC_CLUSTER: equal = - (path1->u.apic_cluster.cluster == - path2->u.apic_cluster.cluster); + (path1->apic_cluster.cluster == + path2->apic_cluster.cluster); break; case DEVICE_PATH_CPU: - equal = (path1->u.cpu.id == path2->u.cpu.id); + equal = (path1->cpu.id == path2->cpu.id); break; case DEVICE_PATH_CPU_BUS: - equal = (path1->u.cpu_bus.id == path2->u.cpu_bus.id); + equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; default: printk(BIOS_ERR, "Unknown device type: %d\n", @@ -370,41 +370,41 @@ equal = 1; break; case DEVICE_ID_PCI: - equal = (path1->u.pci.vendor == path2->u.pci.vendor) - && (path1->u.pci.device == path2->u.pci.device); + equal = (path1->pci.vendor == path2->pci.vendor) + && (path1->pci.device == path2->pci.device); break; case DEVICE_ID_PNP: - equal = (path1->u.pnp.device == path2->u.pnp.device); + equal = (path1->pnp.device == path2->pnp.device); break; case DEVICE_ID_I2C: - equal = (path1->u.i2c.id == path2->u.i2c.id); + equal = (path1->i2c.id == path2->i2c.id); break; case DEVICE_ID_APIC: - equal = (path1->u.apic.vendor == path2->u.apic.vendor) - && (path1->u.apic.device == path2->u.apic.device); + equal = (path1->apic.vendor == path2->apic.vendor) + && (path1->apic.device == path2->apic.device); break; case DEVICE_ID_PCI_DOMAIN: equal = - (path1->u.pci_domain.vendor == - path2->u.pci_domain.vendor) - && (path1->u.pci_domain.device == - path2->u.pci_domain.device); + (path1->pci_domain.vendor == + path2->pci_domain.vendor) + && (path1->pci_domain.device == + path2->pci_domain.device); break; case DEVICE_ID_APIC_CLUSTER: equal = - (path1->u.apic_cluster.vendor == - path2->u.apic_cluster.vendor) - && (path1->u.apic_cluster.device == - path2->u.apic_cluster.device); + (path1->apic_cluster.vendor == + path2->apic_cluster.vendor) + && (path1->apic_cluster.device == + path2->apic_cluster.device); break; case DEVICE_ID_CPU: - equal = (path1->u.cpu.cpuid == path2->u.cpu.cpuid); + equal = (path1->cpu.cpuid == path2->cpu.cpuid); break; case DEVICE_ID_CPU_BUS: equal = - (path1->u.cpu_bus.vendor == path2->u.cpu_bus.vendor) - && (path1->u.cpu_bus.device == - path2->u.cpu_bus.device); + (path1->cpu_bus.vendor == path2->cpu_bus.vendor) + && (path1->cpu_bus.device == + path2->cpu_bus.device); break; default: printk(BIOS_ERR, "Unknown device type: %d\n", Index: corebootv3-anonymous_unions/device/pci_ops.c =================================================================== --- corebootv3-anonymous_unions/device/pci_ops.c (Revision 716) +++ corebootv3-anonymous_unions/device/pci_ops.c (Arbeitskopie) @@ -50,40 +50,40 @@ { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where); + dev->path.pci.devfn, where); } u16 pci_read_config16(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where); + dev->path.pci.devfn, where); } u32 pci_read_config32(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where); + dev->path.pci.devfn, where); } void pci_write_config8(struct device *dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where, val); + dev->path.pci.devfn, where, val); } void pci_write_config16(struct device *dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where, val); + dev->path.pci.devfn, where, val); } void pci_write_config32(struct device *dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where, val); + dev->path.pci.devfn, where, val); } Index: corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c =================================================================== --- corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c (Revision 716) +++ corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c (Arbeitskopie) @@ -224,7 +224,7 @@ /** Operations for when the northbridge is running a PCI domain. */ struct device_operations geodelx_north_domain = { .id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, + {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase2_setup_scan_bus = geodelx_pci_domain_phase2, @@ -239,7 +239,7 @@ /** Operations for when the northbridge is running an APIC cluster. */ struct device_operations geodelx_north_apic = { .id = {.type = DEVICE_ID_APIC_CLUSTER, - .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, + {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase3_scan = 0, @@ -257,7 +257,7 @@ */ struct device_operations geodelx_north_pci = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase3_scan = 0, Index: corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c (Revision 716) +++ corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) @@ -68,7 +68,7 @@ /* See mainboard/emulation/qemu-x86 for an example of how these are used. */ struct device_operations i440bx_domain = { .id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, + {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, .constructor = default_device_constructor, .phase3_scan = pci_domain_scan_bus, .phase4_read_resources = pci_domain_read_resources, Index: corebootv3-anonymous_unions/util/dtc/flattree.c =================================================================== --- corebootv3-anonymous_unions/util/dtc/flattree.c (Revision 716) +++ corebootv3-anonymous_unions/util/dtc/flattree.c (Arbeitskopie) @@ -551,19 +551,19 @@ if (path && path[1]) { path++; if (!strncmp(tree->name, "cpu", 3)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={ .id = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,{.cpu={ .id = 0x%s }}},\n", path); } if (!strncmp(tree->name, "bus", 3)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,{.pci_bus={ .bus = 0x%s }}},\n", path); } if (!strncmp(tree->name, "apic", 4)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,{.apic={ 0x%s }}},\n", path); } if (!strncmp(tree->name, "domain", 6)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%s }}},\n", path); } if (!strncmp(tree->name, "pci", 3)){ @@ -580,11 +580,11 @@ else fn = "0"; - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", dev, fn); } if (!strncmp(tree->name, "ioport", 6)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x%s}}},\n", path); } } Index: corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c =================================================================== --- corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c (Revision 716) +++ corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c (Arbeitskopie) @@ -64,7 +64,7 @@ dev = dev_find_pci_device(X86_DX, X86_CX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; - X86_BL = dev->path.u.pci.devfn; + X86_BL = dev->path.pci.devfn; X86_AH = SUCCESSFUL; X86_EFLAGS &= ~FB_CF; /* clear carry flag */ ret = 1; @@ -79,7 +79,7 @@ dev = dev_find_class(X86_ECX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; - X86_BL = dev->path.u.pci.devfn; + X86_BL = dev->path.pci.devfn; X86_AH = SUCCESSFUL; X86_EFLAGS &= ~FB_CF; /* clear carry flag */ ret = 1; Index: corebootv3-anonymous_unions/util/x86emu/vm86.c =================================================================== --- corebootv3-anonymous_unions/util/x86emu/vm86.c (Revision 716) +++ corebootv3-anonymous_unions/util/x86emu/vm86.c (Arbeitskopie) @@ -249,7 +249,7 @@ *(unsigned char *) i = 0; } - real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.u.pci.devfn); + real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); } @@ -603,7 +603,7 @@ // busnum is an unsigned char; // devfn is an int, so we mask it off. busdevfn = (dev->bus->secondary << 8) - | (dev->path.u.pci.devfn & 0xff); + | (dev->path.pci.devfn & 0xff); printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn); *pebx = busdevfn; retval = 0; Index: corebootv3-anonymous_unions/util/x86emu/biosemu.c =================================================================== --- corebootv3-anonymous_unions/util/x86emu/biosemu.c (Revision 716) +++ corebootv3-anonymous_unions/util/x86emu/biosemu.c (Arbeitskopie) @@ -323,7 +323,7 @@ int i; unsigned short initialcs = (addr & 0xF0000) >> 4; unsigned short initialip = (addr + 3) & 0xFFFF; - unsigned short devfn = dev->bus->secondary << 8 | dev->path.u.pci.devfn; + unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn; X86EMU_intrFuncs intFuncs[256]; X86EMU_setMemBase(0, 0x100000); Index: corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c =================================================================== --- corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c (Revision 716) +++ corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c (Arbeitskopie) @@ -94,7 +94,7 @@ struct device_operations geodelx_cpuops = { {.id = {.type = DEVICE_ID_PCI, /* TODO: This is incorrect, these are _not_ PCI IDs! */ - .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, + {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, .ops = &geodelx_cpuops} .constructor = default_device_constructor, .phase3_scan = NULL, .phase6_init = lx_init, -- http://www.hailfinger.org/ Index: corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c =================================================================== --- corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c (Revision 716) +++ corebootv3-anonymous_unions/southbridge/amd/cs5536/cs5536.c (Arbeitskopie) @@ -696,7 +696,7 @@ struct device_operations cs5536_ops = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, @@ -708,7 +708,7 @@ struct device_operations cs5536_ide = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, .constructor = default_device_constructor, #warning FIXME: what has to go in phase3_scan? Index: corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c (Revision 716) +++ corebootv3-anonymous_unions/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie) @@ -45,10 +45,11 @@ /* the range makes it hard to use the library function. Sorry. * I realize this is not pretty. It would be nice if we could * use anonymous unions. + * We now use anonymous unions. Fix up the code? */ - if ((lpc_dev->id.u.pci.vendor != PCI_VENDOR_ID_NVIDIA) || ( - (lpc_dev->id.u.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || - (lpc_dev->id.u.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) + if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA) || ( + (lpc_dev->id.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || + (lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) ) ) { u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); @@ -80,16 +81,16 @@ unsigned devfn; /* sorry. Again, anonymous unions etc. would make this easier. */ - if(dev->id.u.pci.device==0x0000) { + if(dev->id.pci.device==0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; // vendorid &= 0xffff; } else { // vendorid = dev->vendor; - deviceid = dev->id.u.pci.device; + deviceid = dev->id.pci.device; } - devfn = (dev->path.u.pci.devfn) & ~7; + devfn = (dev->path.pci.devfn) & ~7; switch(deviceid) { case PCI_DEVICE_ID_NVIDIA_MCP55_HT: return; @@ -129,7 +130,7 @@ case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three devfn -= (4<<3); index = 22; - i = (dev->path.u.pci.devfn) & 7; + i = (dev->path.pci.devfn) & 7; if(i>0) { index -= (i+3); } @@ -249,7 +250,7 @@ struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, Index: corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c (Revision 716) +++ corebootv3-anonymous_unions/southbridge/intel/i82371eb/i82371eb.c (Arbeitskopie) @@ -85,7 +85,7 @@ /* You can override or extend each operation as needed for the device. */ struct device_operations i82371eb_isa = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7000}}}, + {.pci = {.vendor = 0x8086,.device = 0x7000}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, @@ -98,7 +98,7 @@ struct device_operations i82371eb_ide = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7010}}}, + {.pci = {.vendor = 0x8086,.device = 0x7010}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, @@ -111,7 +111,7 @@ struct device_operations i82371eb_acpi = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7113}}}, + {.pci = {.vendor = 0x8086,.device = 0x7113}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, Index: corebootv3-anonymous_unions/include/device/path.h =================================================================== --- corebootv3-anonymous_unions/include/device/path.h (Revision 716) +++ corebootv3-anonymous_unions/include/device/path.h (Arbeitskopie) @@ -100,7 +100,7 @@ struct cpu_path cpu; struct cpu_bus_path cpu_bus; struct ioport_path ioport; - } u; + }; }; Index: corebootv3-anonymous_unions/include/device/device.h =================================================================== --- corebootv3-anonymous_unions/include/device/device.h (Revision 716) +++ corebootv3-anonymous_unions/include/device/device.h (Arbeitskopie) @@ -108,7 +108,7 @@ struct apic_cluster_id apic_cluster; struct cpu_id cpu; struct cpu_bus_id cpu_bus; - } u; + }; }; Index: corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c =================================================================== --- corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c (Revision 716) +++ corebootv3-anonymous_unions/superio/winbond/w83627hf/superio.c (Arbeitskopie) @@ -36,13 +36,13 @@ static void pnp_enter_ext_func_mode(struct device * dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } static void pnp_exit_ext_func_mode(struct device * dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void pnp_write_index(u16 port_base, u8 reg, u8 value) @@ -73,7 +73,7 @@ #warning Fix CMOS handling // get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); - pnp_write_index(dev->path.u.pnp.port,7,0x0a); + pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); value &= ~(3<<5); if(power_on) { @@ -128,7 +128,7 @@ } conf = dev->device_configuration; - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627HF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); #warning init_uart8250 @@ -167,7 +167,7 @@ { pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627HF_HWM: printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n"); enable_hwm_smbus(dev); Index: corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c =================================================================== --- corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c (Revision 716) +++ corebootv3-anonymous_unions/superio/fintek/f71805f/superio.c (Arbeitskopie) @@ -41,12 +41,12 @@ static void pnp_enter_conf_state(struct device *dev) { - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); } static void pnp_exit_conf_state(struct device *dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } void f71805f_pnp_set_resources(struct device *dev) @@ -79,7 +79,7 @@ if (!dev->enabled) return; - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case F71805F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); //TODO: needed? fix or remove? Index: corebootv3-anonymous_unions/superio/ite/it8716f/superio.c =================================================================== --- corebootv3-anonymous_unions/superio/ite/it8716f/superio.c (Revision 716) +++ corebootv3-anonymous_unions/superio/ite/it8716f/superio.c (Arbeitskopie) @@ -37,14 +37,14 @@ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(struct device *dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x01, dev->path.u.pnp.port); - outb(0x55, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x01, dev->path.pnp.port); + outb(0x55, dev->path.pnp.port); - if (dev->path.u.pnp.port == 0x4e) { - outb(0xaa, dev->path.u.pnp.port); + if (dev->path.pnp.port == 0x4e) { + outb(0xaa, dev->path.pnp.port); } else { - outb(0x55, dev->path.u.pnp.port); + outb(0x55, dev->path.pnp.port); } } @@ -142,7 +142,7 @@ conf = dev->device_configuration; /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case IT8716F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); // init_uart8250(res0->base, &conf->com1); Index: corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c =================================================================== --- corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c (Revision 716) +++ corebootv3-anonymous_unions/mainboard/emulation/qemu-x86/vga.c (Arbeitskopie) @@ -44,7 +44,7 @@ struct device_operations qemuvga_pci_ops_dev = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS, + {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS, .device = PCI_DEVICE_ID_CIRRUS_5446}}}, .constructor = default_device_constructor, .phase3_scan = 0, Index: corebootv3-anonymous_unions/device/pcie_device.c =================================================================== --- corebootv3-anonymous_unions/device/pcie_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pcie_device.c (Arbeitskopie) @@ -42,8 +42,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pcie_tune_dev(child); Index: corebootv3-anonymous_unions/device/hypertransport.c =================================================================== --- corebootv3-anonymous_unions/device/hypertransport.c (Revision 716) +++ corebootv3-anonymous_unions/device/hypertransport.c (Arbeitskopie) @@ -50,7 +50,7 @@ */ while (last && last->sibling && (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) { + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } if (first) { @@ -344,7 +344,7 @@ u32 id; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = PCI_DEVFN(0, 0); + dummy.path.pci.devfn = PCI_DEVFN(0, 0); id = pci_read_config32(&dummy, PCI_VENDOR_ID); if (!((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000))) { @@ -361,7 +361,7 @@ unsigned int pos, flags; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = devfn; + dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { @@ -498,9 +498,9 @@ /* Update the unitid in the device structure. */ static_count = 1; for (func = dev; func; func = func->sibling) { - func->path.u.pci.devfn += (next_unitid << 3); - static_count = (func->path.u.pci.devfn >> 3) - - (dev->path.u.pci.devfn >> 3) + 1; + func->path.pci.devfn += (next_unitid << 3); + static_count = (func->path.pci.devfn >> 3) + - (dev->path.pci.devfn >> 3) + 1; last_func = func; } @@ -557,7 +557,7 @@ flags); for (func = real_last_dev; func; func = func->sibling) { - func->path.u.pci.devfn -= + func->path.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3); last_func = func; Index: corebootv3-anonymous_unions/device/pnp_device.c =================================================================== --- corebootv3-anonymous_unions/device/pnp_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pnp_device.c (Arbeitskopie) @@ -32,19 +32,19 @@ void pnp_write_config(struct device *dev, u8 reg, u8 value) { - outb(reg, dev->path.u.pnp.port); - outb(value, dev->path.u.pnp.port + 1); + outb(reg, dev->path.pnp.port); + outb(value, dev->path.pnp.port + 1); } u8 pnp_read_config(struct device *dev, u8 reg) { - outb(reg, dev->path.u.pnp.port); - return inb(dev->path.u.pnp.port + 1); + outb(reg, dev->path.pnp.port); + return inb(dev->path.pnp.port + 1); } void pnp_set_logical_device(struct device *dev) { - pnp_write_config(dev, 0x07, dev->path.u.pnp.device); + pnp_write_config(dev, 0x07, dev->path.pnp.device); } void pnp_set_enable(struct device *dev, int enable) @@ -238,11 +238,11 @@ int i; path.type = DEVICE_PATH_PNP; - path.u.pnp.port = base_dev->path.u.pnp.port; + path.pnp.port = base_dev->path.pnp.port; /* Setup the ops and resources on the newly allocated devices. */ for (i = 0; i < functions; i++) { - path.u.pnp.device = info[i].function; + path.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path, &id); /* Don't initialize a device multiple times. */ Index: corebootv3-anonymous_unions/device/pcix_device.c =================================================================== --- corebootv3-anonymous_unions/device/pcix_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pcix_device.c (Arbeitskopie) @@ -66,8 +66,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pcix_tune_dev(child); Index: corebootv3-anonymous_unions/device/agp_device.c =================================================================== --- corebootv3-anonymous_unions/device/agp_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/agp_device.c (Arbeitskopie) @@ -40,8 +40,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } agp_tune_dev(child); Index: corebootv3-anonymous_unions/device/pci_rom.c =================================================================== --- corebootv3-anonymous_unions/device/pci_rom.c (Revision 716) +++ corebootv3-anonymous_unions/device/pci_rom.c (Arbeitskopie) @@ -45,8 +45,8 @@ * or readonly. */ init_archive(&archive); - sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor, - dev->id.u.pci.device); + sprintf(pcifile, "pci%04x,%04x.rom", dev->id.pci.vendor, + dev->id.pci.device); ret = find_file(&archive, pcifile, &result); if (ret) { @@ -108,7 +108,7 @@ printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); - if (dev->id.u.pci.vendor != rom_data->vendor || dev->id.u.pci.device != rom_data->device) { + if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) { printk(BIOS_ERR, "Device or Vendor ID mismatch Vendor %04x, Device %04x\n", rom_data->vendor, rom_data->device); Index: corebootv3-anonymous_unions/device/pci_device.c =================================================================== --- corebootv3-anonymous_unions/device/pci_device.c (Revision 716) +++ corebootv3-anonymous_unions/device/pci_device.c (Arbeitskopie) @@ -894,8 +894,8 @@ continue; } printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n", - __func__, (*list)->dtsname, (*list)->path.u.pci.devfn); - if ((*list)->path.u.pci.devfn == devfn) { + __func__, (*list)->dtsname, (*list)->path.pci.devfn); + if ((*list)->path.pci.devfn == devfn) { /* Unlink from the list. */ dev = *list; *list = (*list)->sibling; @@ -948,7 +948,7 @@ struct device_id devid; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = devfn; + dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); /* Have we found something? * Some broken boards return 0 if a slot is empty. @@ -960,8 +960,8 @@ return NULL; } devid.type = DEVICE_ID_PCI; - devid.u.pci.vendor = id & 0xffff; - devid.u.pci.device = id >> 16; + devid.pci.vendor = id & 0xffff; + devid.pci.device = id >> 16; dev = alloc_dev(bus, &dummy.path, &devid); } else { /* Enable/disable the device. Once we have found the device @@ -1013,8 +1013,8 @@ /* Store the interesting information in the device structure. */ dev->id.type = DEVICE_ID_PCI; - dev->id.u.pci.vendor = id & 0xffff; - dev->id.u.pci.device = (id >> 16) & 0xffff; + dev->id.pci.vendor = id & 0xffff; + dev->id.pci.device = (id >> 16) & 0xffff; dev->hdr_type = hdr_type; /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */ dev->class = class >> 8; Index: corebootv3-anonymous_unions/device/device_util.c =================================================================== --- corebootv3-anonymous_unions/device/device_util.c (Revision 716) +++ corebootv3-anonymous_unions/device/device_util.c (Arbeitskopie) @@ -81,7 +81,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && (dev->bus->secondary == bus) && - (dev->path.u.pci.devfn == devfn)) { + (dev->path.pci.devfn == devfn)) { result = dev; break; } @@ -104,7 +104,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_I2C) && (dev->bus->secondary == bus) && - (dev->path.u.i2c.device == addr)) { + (dev->path.i2c.device == addr)) { result = dev; break; } @@ -155,8 +155,8 @@ struct device_id id; id.type = DEVICE_ID_PCI; - id.u.pci.vendor = vendor; - id.u.pci.device = device; + id.pci.vendor = vendor; + id.pci.device = device; return dev_find_device(&id, from); } @@ -197,48 +197,48 @@ sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", dev->bus->secondary >> 8, dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.u.pci.devfn), - PCI_FUNC(dev->path.u.pci.devfn)); + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #else sprintf(buffer, "PCI: %02x:%02x.%01x", dev->bus->secondary, - PCI_SLOT(dev->path.u.pci.devfn), - PCI_FUNC(dev->path.u.pci.devfn)); + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #endif break; case DEVICE_PATH_PNP: sprintf(buffer, "PNP: %04x.%01x", - dev->path.u.pnp.port, dev->path.u.pnp.device); + dev->path.pnp.port, dev->path.pnp.device); break; case DEVICE_PATH_I2C: sprintf(buffer, "I2C: %02x:%02x", - dev->bus->secondary, dev->path.u.i2c.device); + dev->bus->secondary, dev->path.i2c.device); break; case DEVICE_PATH_APIC: - sprintf(buffer, "APIC: %02x", dev->path.u.apic.apic_id); + sprintf(buffer, "APIC: %02x", dev->path.apic.apic_id); break; case DEVICE_PATH_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x", - dev->path.u.pci_domain.domain); + dev->path.pci_domain.domain); break; case DEVICE_PATH_PCI_BUS: sprintf(buffer, "PCI_BUS: %04x", - dev->path.u.pci_bus.bus); + dev->path.pci_bus.bus); break; case DEVICE_PATH_APIC_CLUSTER: sprintf(buffer, "APIC_CLUSTER: %01x", - dev->path.u.apic_cluster.cluster); + dev->path.apic_cluster.cluster); break; case DEVICE_PATH_CPU: - sprintf(buffer, "CPU: %02x", dev->path.u.cpu.id); + sprintf(buffer, "CPU: %02x", dev->path.cpu.id); break; case DEVICE_PATH_CPU_BUS: sprintf(buffer, "CPU_BUS: %02x", - dev->path.u.cpu_bus.id); + dev->path.cpu_bus.id); break; case DEVICE_PATH_IOPORT: sprintf(buffer, "IOPORT: %02x", - dev->path.u.ioport.iobase); + dev->path.ioport.iobase); break; default: printk(BIOS_ERR, "%s: Unknown device path type: %d\n", @@ -262,36 +262,36 @@ memcpy(buffer, "Root Device", 12); break; case DEVICE_ID_PCI: - sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor, - id->u.pci.device); + sprintf(buffer, "PCI: %04x:%04x", id->pci.vendor, + id->pci.device); break; case DEVICE_ID_PNP: - sprintf(buffer, "PNP: %04x", id->u.pnp.device); + sprintf(buffer, "PNP: %04x", id->pnp.device); break; case DEVICE_ID_I2C: - sprintf(buffer, "I2C: %04x", id->u.i2c.id); + sprintf(buffer, "I2C: %04x", id->i2c.id); break; case DEVICE_ID_APIC: - sprintf(buffer, "APIC: %02x:%02x", id->u.apic.vendor, - id->u.apic.device); + sprintf(buffer, "APIC: %02x:%02x", id->apic.vendor, + id->apic.device); break; case DEVICE_ID_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x:%04x", - id->u.pci_domain.vendor, - id->u.pci_domain.device); + id->pci_domain.vendor, + id->pci_domain.device); break; case DEVICE_ID_APIC_CLUSTER: sprintf(buffer, "APIC_CLUSTER: %02x:%02x", - id->u.apic_cluster.vendor, - id->u.apic_cluster.device); + id->apic_cluster.vendor, + id->apic_cluster.device); break; case DEVICE_ID_CPU: - sprintf(buffer, "CPU", id->u.cpu.cpuid[0], - id->u.cpu.cpuid[1], id->u.cpu.cpuid[2]); + sprintf(buffer, "CPU", id->cpu.cpuid[0], + id->cpu.cpuid[1], id->cpu.cpuid[2]); break; case DEVICE_ID_CPU_BUS: sprintf(buffer, "CPU_BUS: %02x:%02x", - id->u.cpu_bus.vendor, id->u.cpu_bus.device); + id->cpu_bus.vendor, id->cpu_bus.device); break; default: printk(BIOS_ERR, "%s: Unknown device ID type: %d\n", @@ -321,34 +321,34 @@ equal = 1; break; case DEVICE_PATH_PCI: - equal = (path1->u.pci.devfn == path2->u.pci.devfn); + equal = (path1->pci.devfn == path2->pci.devfn); break; case DEVICE_PATH_PNP: - equal = (path1->u.pnp.port == path2->u.pnp.port) && - (path1->u.pnp.device == path2->u.pnp.device); + equal = (path1->pnp.port == path2->pnp.port) && + (path1->pnp.device == path2->pnp.device); break; case DEVICE_PATH_I2C: - equal = (path1->u.i2c.device == path2->u.i2c.device); + equal = (path1->i2c.device == path2->i2c.device); break; case DEVICE_PATH_APIC: equal = - (path1->u.apic.apic_id == path2->u.apic.apic_id); + (path1->apic.apic_id == path2->apic.apic_id); break; case DEVICE_PATH_PCI_DOMAIN: equal = - (path1->u.pci_domain.domain == - path2->u.pci_domain.domain); + (path1->pci_domain.domain == + path2->pci_domain.domain); break; case DEVICE_PATH_APIC_CLUSTER: equal = - (path1->u.apic_cluster.cluster == - path2->u.apic_cluster.cluster); + (path1->apic_cluster.cluster == + path2->apic_cluster.cluster); break; case DEVICE_PATH_CPU: - equal = (path1->u.cpu.id == path2->u.cpu.id); + equal = (path1->cpu.id == path2->cpu.id); break; case DEVICE_PATH_CPU_BUS: - equal = (path1->u.cpu_bus.id == path2->u.cpu_bus.id); + equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; default: printk(BIOS_ERR, "Unknown device type: %d\n", @@ -370,41 +370,41 @@ equal = 1; break; case DEVICE_ID_PCI: - equal = (path1->u.pci.vendor == path2->u.pci.vendor) - && (path1->u.pci.device == path2->u.pci.device); + equal = (path1->pci.vendor == path2->pci.vendor) + && (path1->pci.device == path2->pci.device); break; case DEVICE_ID_PNP: - equal = (path1->u.pnp.device == path2->u.pnp.device); + equal = (path1->pnp.device == path2->pnp.device); break; case DEVICE_ID_I2C: - equal = (path1->u.i2c.id == path2->u.i2c.id); + equal = (path1->i2c.id == path2->i2c.id); break; case DEVICE_ID_APIC: - equal = (path1->u.apic.vendor == path2->u.apic.vendor) - && (path1->u.apic.device == path2->u.apic.device); + equal = (path1->apic.vendor == path2->apic.vendor) + && (path1->apic.device == path2->apic.device); break; case DEVICE_ID_PCI_DOMAIN: equal = - (path1->u.pci_domain.vendor == - path2->u.pci_domain.vendor) - && (path1->u.pci_domain.device == - path2->u.pci_domain.device); + (path1->pci_domain.vendor == + path2->pci_domain.vendor) + && (path1->pci_domain.device == + path2->pci_domain.device); break; case DEVICE_ID_APIC_CLUSTER: equal = - (path1->u.apic_cluster.vendor == - path2->u.apic_cluster.vendor) - && (path1->u.apic_cluster.device == - path2->u.apic_cluster.device); + (path1->apic_cluster.vendor == + path2->apic_cluster.vendor) + && (path1->apic_cluster.device == + path2->apic_cluster.device); break; case DEVICE_ID_CPU: - equal = (path1->u.cpu.cpuid == path2->u.cpu.cpuid); + equal = (path1->cpu.cpuid == path2->cpu.cpuid); break; case DEVICE_ID_CPU_BUS: equal = - (path1->u.cpu_bus.vendor == path2->u.cpu_bus.vendor) - && (path1->u.cpu_bus.device == - path2->u.cpu_bus.device); + (path1->cpu_bus.vendor == path2->cpu_bus.vendor) + && (path1->cpu_bus.device == + path2->cpu_bus.device); break; default: printk(BIOS_ERR, "Unknown device type: %d\n", Index: corebootv3-anonymous_unions/device/pci_ops.c =================================================================== --- corebootv3-anonymous_unions/device/pci_ops.c (Revision 716) +++ corebootv3-anonymous_unions/device/pci_ops.c (Arbeitskopie) @@ -50,40 +50,40 @@ { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read8(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where); + dev->path.pci.devfn, where); } u16 pci_read_config16(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read16(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where); + dev->path.pci.devfn, where); } u32 pci_read_config32(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read32(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where); + dev->path.pci.devfn, where); } void pci_write_config8(struct device *dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write8(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where, val); + dev->path.pci.devfn, where, val); } void pci_write_config16(struct device *dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write16(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where, val); + dev->path.pci.devfn, where, val); } void pci_write_config32(struct device *dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, - dev->path.u.pci.devfn, where, val); + dev->path.pci.devfn, where, val); } Index: corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c =================================================================== --- corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c (Revision 716) +++ corebootv3-anonymous_unions/northbridge/amd/geodelx/geodelx.c (Arbeitskopie) @@ -224,7 +224,7 @@ /** Operations for when the northbridge is running a PCI domain. */ struct device_operations geodelx_north_domain = { .id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, + {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase2_setup_scan_bus = geodelx_pci_domain_phase2, @@ -239,7 +239,7 @@ /** Operations for when the northbridge is running an APIC cluster. */ struct device_operations geodelx_north_apic = { .id = {.type = DEVICE_ID_APIC_CLUSTER, - .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, + {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase3_scan = 0, @@ -257,7 +257,7 @@ */ struct device_operations geodelx_north_pci = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase3_scan = 0, Index: corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c (Revision 716) +++ corebootv3-anonymous_unions/northbridge/intel/i440bxemulation/i440bx.c (Arbeitskopie) @@ -68,7 +68,7 @@ /* See mainboard/emulation/qemu-x86 for an example of how these are used. */ struct device_operations i440bx_domain = { .id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, + {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, .constructor = default_device_constructor, .phase3_scan = pci_domain_scan_bus, .phase4_read_resources = pci_domain_read_resources, Index: corebootv3-anonymous_unions/util/dtc/flattree.c =================================================================== --- corebootv3-anonymous_unions/util/dtc/flattree.c (Revision 716) +++ corebootv3-anonymous_unions/util/dtc/flattree.c (Arbeitskopie) @@ -551,19 +551,19 @@ if (path && path[1]) { path++; if (!strncmp(tree->name, "cpu", 3)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={ .id = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,{.cpu={ .id = 0x%s }}},\n", path); } if (!strncmp(tree->name, "bus", 3)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,{.pci_bus={ .bus = 0x%s }}},\n", path); } if (!strncmp(tree->name, "apic", 4)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,{.apic={ 0x%s }}},\n", path); } if (!strncmp(tree->name, "domain", 6)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%s }}},\n", path); } if (!strncmp(tree->name, "pci", 3)){ @@ -580,11 +580,11 @@ else fn = "0"; - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", dev, fn); } if (!strncmp(tree->name, "ioport", 6)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x%s}}},\n", path); } } Index: corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c =================================================================== --- corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c (Revision 716) +++ corebootv3-anonymous_unions/util/x86emu/pcbios/pcibios.c (Arbeitskopie) @@ -64,7 +64,7 @@ dev = dev_find_pci_device(X86_DX, X86_CX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; - X86_BL = dev->path.u.pci.devfn; + X86_BL = dev->path.pci.devfn; X86_AH = SUCCESSFUL; X86_EFLAGS &= ~FB_CF; /* clear carry flag */ ret = 1; @@ -79,7 +79,7 @@ dev = dev_find_class(X86_ECX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; - X86_BL = dev->path.u.pci.devfn; + X86_BL = dev->path.pci.devfn; X86_AH = SUCCESSFUL; X86_EFLAGS &= ~FB_CF; /* clear carry flag */ ret = 1; Index: corebootv3-anonymous_unions/util/x86emu/vm86.c =================================================================== --- corebootv3-anonymous_unions/util/x86emu/vm86.c (Revision 716) +++ corebootv3-anonymous_unions/util/x86emu/vm86.c (Arbeitskopie) @@ -249,7 +249,7 @@ *(unsigned char *) i = 0; } - real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.u.pci.devfn); + real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); } @@ -603,7 +603,7 @@ // busnum is an unsigned char; // devfn is an int, so we mask it off. busdevfn = (dev->bus->secondary << 8) - | (dev->path.u.pci.devfn & 0xff); + | (dev->path.pci.devfn & 0xff); printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn); *pebx = busdevfn; retval = 0; Index: corebootv3-anonymous_unions/util/x86emu/biosemu.c =================================================================== --- corebootv3-anonymous_unions/util/x86emu/biosemu.c (Revision 716) +++ corebootv3-anonymous_unions/util/x86emu/biosemu.c (Arbeitskopie) @@ -323,7 +323,7 @@ int i; unsigned short initialcs = (addr & 0xF0000) >> 4; unsigned short initialip = (addr + 3) & 0xFFFF; - unsigned short devfn = dev->bus->secondary << 8 | dev->path.u.pci.devfn; + unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn; X86EMU_intrFuncs intFuncs[256]; X86EMU_setMemBase(0, 0x100000); Index: corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c =================================================================== --- corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c (Revision 716) +++ corebootv3-anonymous_unions/arch/x86/geodelx/cpu.c (Arbeitskopie) @@ -94,7 +94,7 @@ struct device_operations geodelx_cpuops = { {.id = {.type = DEVICE_ID_PCI, /* TODO: This is incorrect, these are _not_ PCI IDs! */ - .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, + {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, .ops = &geodelx_cpuops} .constructor = default_device_constructor, .phase3_scan = NULL, .phase6_init = lx_init,

4 7

Re: [coreboot] r3474 - in trunk/payloads/libpayload: drivers i386 include
by Peter Stuge 10 Aug '08

10 Aug '08

On Thu, Aug 07, 2008 at 12:21:05PM +0200, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-08-07 12:21:05 +0200 (Thu, 07 Aug 2008) > New Revision: 3474 > > Added: > trunk/payloads/libpayload/drivers/options.c > Modified: > trunk/payloads/libpayload/drivers/Makefile.inc > trunk/payloads/libpayload/i386/coreboot.c > trunk/payloads/libpayload/include/coreboot_tables.h > trunk/payloads/libpayload/include/sysinfo.h > Log: > add get_option to libpayload, so coreboot cmos options can be queried. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> > Acked-by: Peter Stuge <peter(a)stuge.se> Sorry. This breaks my build. I should have tested. :\ cc -m32 -Wall -Werror -fno-stack-protector -nostdinc -I./include -I/usr/lib/gcc/i686-pc-linux-gnu/4.2.2/include -c -o drivers/options.o drivers/options.c cc1: warnings being treated as errors drivers/options.c: In function 'get_option': drivers/options.c:93: warning: pointer targets in passing argument 1 of 'memcmp' differ in signedness make: *** [drivers/options.o] Error 1 >From the patch: > + if (memcmp(cmos_entry->name, name, len)) .. > +#define CB_TAG_OPTION 0x00c9 > +#define CMOS_MAX_NAME_LENGTH 32 > +struct cb_cmos_entries { > + u32 tag; > + u32 size; > + u32 bit; > + u32 length; > + u32 config; > + u32 config_id; > + u8 name[CMOS_MAX_NAME_LENGTH]; > +}; memcmp() expects char * What should change? I'm thinking memcmp() and friends. Later revisions breaks more stuff. :\ //Peter

4 10

pci and console changes
by ron minnich 10 Aug '08

10 Aug '08

Added a find function, and other things. I would really appreciate a review here. Peter is supposed to be in greece on the beach. HA! This is working on DBE62. Now that it is done I can do some more K8 work -- assuming it meets with approval. ron

3 10

r730 - in coreboot-v3: arch/x86/geodelx device include/device mainboard/emulation/qemu-x86 northbridge/amd/geodelx northbridge/intel/i440bxemulation southbridge/amd/cs5536 southbridge/intel/i82371eb southbridge/nvidia/mcp55 superio/fintek/f71805f superio/ite/it8716f superio/winbond/w83627hf util/dtc util/x86emu util/x86emu/pcbios
by svn＠coreboot.org 10 Aug '08

10 Aug '08

Author: hailfinger Date: 2008-08-10 02:20:24 +0200 (Sun, 10 Aug 2008) New Revision: 730 Modified: coreboot-v3/arch/x86/geodelx/cpu.c coreboot-v3/device/agp_device.c coreboot-v3/device/device_util.c coreboot-v3/device/hypertransport.c coreboot-v3/device/pci_device.c coreboot-v3/device/pci_ops.c coreboot-v3/device/pci_rom.c coreboot-v3/device/pcie_device.c coreboot-v3/device/pcix_device.c coreboot-v3/device/pnp_device.c coreboot-v3/include/device/device.h coreboot-v3/include/device/path.h coreboot-v3/mainboard/emulation/qemu-x86/vga.c coreboot-v3/northbridge/amd/geodelx/geodelx.c coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c coreboot-v3/southbridge/amd/cs5536/cs5536.c coreboot-v3/southbridge/intel/i82371eb/i82371eb.c coreboot-v3/southbridge/nvidia/mcp55/mcp55.c coreboot-v3/superio/fintek/f71805f/superio.c coreboot-v3/superio/ite/it8716f/superio.c coreboot-v3/superio/winbond/w83627hf/superio.c coreboot-v3/util/dtc/flattree.c coreboot-v3/util/x86emu/biosemu.c coreboot-v3/util/x86emu/pcbios/pcibios.c coreboot-v3/util/x86emu/vm86.c Log: The named unions in the device tree code are obnoxious and degrade readability. Move to anonymous unions. Build tested on all targets. Boot tested on qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Ron tested this and it boots to Linux. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/geodelx/cpu.c =================================================================== --- coreboot-v3/arch/x86/geodelx/cpu.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/arch/x86/geodelx/cpu.c 2008-08-10 00:20:24 UTC (rev 730) @@ -94,7 +94,7 @@ struct device_operations geodelx_cpuops = { {.id = {.type = DEVICE_ID_PCI, /* TODO: This is incorrect, these are _not_ PCI IDs! */ - .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, + {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}}, .ops = &geodelx_cpuops} .constructor = default_device_constructor, .phase3_scan = NULL, .phase6_init = lx_init, Modified: coreboot-v3/device/agp_device.c =================================================================== --- coreboot-v3/device/agp_device.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/agp_device.c 2008-08-10 00:20:24 UTC (rev 730) @@ -40,8 +40,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } agp_tune_dev(child); Modified: coreboot-v3/device/device_util.c =================================================================== --- coreboot-v3/device/device_util.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/device_util.c 2008-08-10 00:20:24 UTC (rev 730) @@ -81,7 +81,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && (dev->bus->secondary == bus) && - (dev->path.u.pci.devfn == devfn)) { + (dev->path.pci.devfn == devfn)) { result = dev; break; } @@ -104,7 +104,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_I2C) && (dev->bus->secondary == bus) && - (dev->path.u.i2c.device == addr)) { + (dev->path.i2c.device == addr)) { result = dev; break; } @@ -155,8 +155,8 @@ struct device_id id; id.type = DEVICE_ID_PCI; - id.u.pci.vendor = vendor; - id.u.pci.device = device; + id.pci.vendor = vendor; + id.pci.device = device; return dev_find_device(&id, from); } @@ -197,48 +197,48 @@ sprintf(buffer, "PCI: %04x:%02x:%02x.%01x", dev->bus->secondary >> 8, dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.u.pci.devfn), - PCI_FUNC(dev->path.u.pci.devfn)); + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #else sprintf(buffer, "PCI: %02x:%02x.%01x", dev->bus->secondary, - PCI_SLOT(dev->path.u.pci.devfn), - PCI_FUNC(dev->path.u.pci.devfn)); + PCI_SLOT(dev->path.pci.devfn), + PCI_FUNC(dev->path.pci.devfn)); #endif break; case DEVICE_PATH_PNP: sprintf(buffer, "PNP: %04x.%01x", - dev->path.u.pnp.port, dev->path.u.pnp.device); + dev->path.pnp.port, dev->path.pnp.device); break; case DEVICE_PATH_I2C: sprintf(buffer, "I2C: %02x:%02x", - dev->bus->secondary, dev->path.u.i2c.device); + dev->bus->secondary, dev->path.i2c.device); break; case DEVICE_PATH_APIC: - sprintf(buffer, "APIC: %02x", dev->path.u.apic.apic_id); + sprintf(buffer, "APIC: %02x", dev->path.apic.apic_id); break; case DEVICE_PATH_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x", - dev->path.u.pci_domain.domain); + dev->path.pci_domain.domain); break; case DEVICE_PATH_PCI_BUS: sprintf(buffer, "PCI_BUS: %04x", - dev->path.u.pci_bus.bus); + dev->path.pci_bus.bus); break; case DEVICE_PATH_APIC_CLUSTER: sprintf(buffer, "APIC_CLUSTER: %01x", - dev->path.u.apic_cluster.cluster); + dev->path.apic_cluster.cluster); break; case DEVICE_PATH_CPU: - sprintf(buffer, "CPU: %02x", dev->path.u.cpu.id); + sprintf(buffer, "CPU: %02x", dev->path.cpu.id); break; case DEVICE_PATH_CPU_BUS: sprintf(buffer, "CPU_BUS: %02x", - dev->path.u.cpu_bus.id); + dev->path.cpu_bus.id); break; case DEVICE_PATH_IOPORT: sprintf(buffer, "IOPORT: %02x", - dev->path.u.ioport.iobase); + dev->path.ioport.iobase); break; default: printk(BIOS_ERR, "%s: Unknown device path type: %d\n", @@ -262,36 +262,36 @@ memcpy(buffer, "Root Device", 12); break; case DEVICE_ID_PCI: - sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor, - id->u.pci.device); + sprintf(buffer, "PCI: %04x:%04x", id->pci.vendor, + id->pci.device); break; case DEVICE_ID_PNP: - sprintf(buffer, "PNP: %04x", id->u.pnp.device); + sprintf(buffer, "PNP: %04x", id->pnp.device); break; case DEVICE_ID_I2C: - sprintf(buffer, "I2C: %04x", id->u.i2c.id); + sprintf(buffer, "I2C: %04x", id->i2c.id); break; case DEVICE_ID_APIC: - sprintf(buffer, "APIC: %02x:%02x", id->u.apic.vendor, - id->u.apic.device); + sprintf(buffer, "APIC: %02x:%02x", id->apic.vendor, + id->apic.device); break; case DEVICE_ID_PCI_DOMAIN: sprintf(buffer, "PCI_DOMAIN: %04x:%04x", - id->u.pci_domain.vendor, - id->u.pci_domain.device); + id->pci_domain.vendor, + id->pci_domain.device); break; case DEVICE_ID_APIC_CLUSTER: sprintf(buffer, "APIC_CLUSTER: %02x:%02x", - id->u.apic_cluster.vendor, - id->u.apic_cluster.device); + id->apic_cluster.vendor, + id->apic_cluster.device); break; case DEVICE_ID_CPU: - sprintf(buffer, "CPU", id->u.cpu.cpuid[0], - id->u.cpu.cpuid[1], id->u.cpu.cpuid[2]); + sprintf(buffer, "CPU", id->cpu.cpuid[0], + id->cpu.cpuid[1], id->cpu.cpuid[2]); break; case DEVICE_ID_CPU_BUS: sprintf(buffer, "CPU_BUS: %02x:%02x", - id->u.cpu_bus.vendor, id->u.cpu_bus.device); + id->cpu_bus.vendor, id->cpu_bus.device); break; default: printk(BIOS_ERR, "%s: Unknown device ID type: %d\n", @@ -321,34 +321,34 @@ equal = 1; break; case DEVICE_PATH_PCI: - equal = (path1->u.pci.devfn == path2->u.pci.devfn); + equal = (path1->pci.devfn == path2->pci.devfn); break; case DEVICE_PATH_PNP: - equal = (path1->u.pnp.port == path2->u.pnp.port) && - (path1->u.pnp.device == path2->u.pnp.device); + equal = (path1->pnp.port == path2->pnp.port) && + (path1->pnp.device == path2->pnp.device); break; case DEVICE_PATH_I2C: - equal = (path1->u.i2c.device == path2->u.i2c.device); + equal = (path1->i2c.device == path2->i2c.device); break; case DEVICE_PATH_APIC: equal = - (path1->u.apic.apic_id == path2->u.apic.apic_id); + (path1->apic.apic_id == path2->apic.apic_id); break; case DEVICE_PATH_PCI_DOMAIN: equal = - (path1->u.pci_domain.domain == - path2->u.pci_domain.domain); + (path1->pci_domain.domain == + path2->pci_domain.domain); break; case DEVICE_PATH_APIC_CLUSTER: equal = - (path1->u.apic_cluster.cluster == - path2->u.apic_cluster.cluster); + (path1->apic_cluster.cluster == + path2->apic_cluster.cluster); break; case DEVICE_PATH_CPU: - equal = (path1->u.cpu.id == path2->u.cpu.id); + equal = (path1->cpu.id == path2->cpu.id); break; case DEVICE_PATH_CPU_BUS: - equal = (path1->u.cpu_bus.id == path2->u.cpu_bus.id); + equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; default: printk(BIOS_ERR, "Unknown device type: %d\n", @@ -370,41 +370,41 @@ equal = 1; break; case DEVICE_ID_PCI: - equal = (path1->u.pci.vendor == path2->u.pci.vendor) - && (path1->u.pci.device == path2->u.pci.device); + equal = (path1->pci.vendor == path2->pci.vendor) + && (path1->pci.device == path2->pci.device); break; case DEVICE_ID_PNP: - equal = (path1->u.pnp.device == path2->u.pnp.device); + equal = (path1->pnp.device == path2->pnp.device); break; case DEVICE_ID_I2C: - equal = (path1->u.i2c.id == path2->u.i2c.id); + equal = (path1->i2c.id == path2->i2c.id); break; case DEVICE_ID_APIC: - equal = (path1->u.apic.vendor == path2->u.apic.vendor) - && (path1->u.apic.device == path2->u.apic.device); + equal = (path1->apic.vendor == path2->apic.vendor) + && (path1->apic.device == path2->apic.device); break; case DEVICE_ID_PCI_DOMAIN: equal = - (path1->u.pci_domain.vendor == - path2->u.pci_domain.vendor) - && (path1->u.pci_domain.device == - path2->u.pci_domain.device); + (path1->pci_domain.vendor == + path2->pci_domain.vendor) + && (path1->pci_domain.device == + path2->pci_domain.device); break; case DEVICE_ID_APIC_CLUSTER: equal = - (path1->u.apic_cluster.vendor == - path2->u.apic_cluster.vendor) - && (path1->u.apic_cluster.device == - path2->u.apic_cluster.device); + (path1->apic_cluster.vendor == + path2->apic_cluster.vendor) + && (path1->apic_cluster.device == + path2->apic_cluster.device); break; case DEVICE_ID_CPU: - equal = (path1->u.cpu.cpuid == path2->u.cpu.cpuid); + equal = (path1->cpu.cpuid == path2->cpu.cpuid); break; case DEVICE_ID_CPU_BUS: equal = - (path1->u.cpu_bus.vendor == path2->u.cpu_bus.vendor) - && (path1->u.cpu_bus.device == - path2->u.cpu_bus.device); + (path1->cpu_bus.vendor == path2->cpu_bus.vendor) + && (path1->cpu_bus.device == + path2->cpu_bus.device); break; default: printk(BIOS_ERR, "Unknown device type: %d\n", Modified: coreboot-v3/device/hypertransport.c =================================================================== --- coreboot-v3/device/hypertransport.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/hypertransport.c 2008-08-10 00:20:24 UTC (rev 730) @@ -50,7 +50,7 @@ */ while (last && last->sibling && (last->sibling->path.type == DEVICE_PATH_PCI) && - (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) { + (last->sibling->path.pci.devfn > last->path.pci.devfn)) { last = last->sibling; } if (first) { @@ -344,7 +344,7 @@ u32 id; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = PCI_DEVFN(0, 0); + dummy.path.pci.devfn = PCI_DEVFN(0, 0); id = pci_read_config32(&dummy, PCI_VENDOR_ID); if (!((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000))) { @@ -361,7 +361,7 @@ unsigned int pos, flags; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = devfn; + dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { @@ -498,9 +498,9 @@ /* Update the unitid in the device structure. */ static_count = 1; for (func = dev; func; func = func->sibling) { - func->path.u.pci.devfn += (next_unitid << 3); - static_count = (func->path.u.pci.devfn >> 3) - - (dev->path.u.pci.devfn >> 3) + 1; + func->path.pci.devfn += (next_unitid << 3); + static_count = (func->path.pci.devfn >> 3) + - (dev->path.pci.devfn >> 3) + 1; last_func = func; } @@ -557,7 +557,7 @@ flags); for (func = real_last_dev; func; func = func->sibling) { - func->path.u.pci.devfn -= + func->path.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3); last_func = func; Modified: coreboot-v3/device/pci_device.c =================================================================== --- coreboot-v3/device/pci_device.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/pci_device.c 2008-08-10 00:20:24 UTC (rev 730) @@ -894,8 +894,8 @@ continue; } printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n", - __func__, (*list)->dtsname, (*list)->path.u.pci.devfn); - if ((*list)->path.u.pci.devfn == devfn) { + __func__, (*list)->dtsname, (*list)->path.pci.devfn); + if ((*list)->path.pci.devfn == devfn) { /* Unlink from the list. */ dev = *list; *list = (*list)->sibling; @@ -948,7 +948,7 @@ struct device_id devid; dummy.bus = bus; dummy.path.type = DEVICE_PATH_PCI; - dummy.path.u.pci.devfn = devfn; + dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); /* Have we found something? * Some broken boards return 0 if a slot is empty. @@ -960,8 +960,8 @@ return NULL; } devid.type = DEVICE_ID_PCI; - devid.u.pci.vendor = id & 0xffff; - devid.u.pci.device = id >> 16; + devid.pci.vendor = id & 0xffff; + devid.pci.device = id >> 16; dev = alloc_dev(bus, &dummy.path, &devid); } else { /* Enable/disable the device. Once we have found the device @@ -1013,8 +1013,8 @@ /* Store the interesting information in the device structure. */ dev->id.type = DEVICE_ID_PCI; - dev->id.u.pci.vendor = id & 0xffff; - dev->id.u.pci.device = (id >> 16) & 0xffff; + dev->id.pci.vendor = id & 0xffff; + dev->id.pci.device = (id >> 16) & 0xffff; dev->hdr_type = hdr_type; /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */ dev->class = class >> 8; Modified: coreboot-v3/device/pci_ops.c =================================================================== --- coreboot-v3/device/pci_ops.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/pci_ops.c 2008-08-10 00:20:24 UTC (rev 730) @@ -50,7 +50,7 @@ { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read8(PCI_BDEVFN(dev->bus->secondary, - dev->path.u.pci.devfn), + dev->path.pci.devfn), where); } @@ -58,7 +58,7 @@ { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read16(PCI_BDEVFN(dev->bus->secondary, - dev->path.u.pci.devfn), + dev->path.pci.devfn), where); } @@ -66,7 +66,7 @@ { struct bus *pbus = get_pbus(dev); return ops_pci_bus(pbus)->read32(PCI_BDEVFN(dev->bus->secondary, - dev->path.u.pci.devfn), + dev->path.pci.devfn), where); } @@ -74,7 +74,7 @@ { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write8(PCI_BDEVFN(dev->bus->secondary, - dev->path.u.pci.devfn), + dev->path.pci.devfn), where, val); } @@ -82,7 +82,7 @@ { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write16(PCI_BDEVFN(dev->bus->secondary, - dev->path.u.pci.devfn), + dev->path.pci.devfn), where, val); } @@ -90,6 +90,6 @@ { struct bus *pbus = get_pbus(dev); ops_pci_bus(pbus)->write32(PCI_BDEVFN(dev->bus->secondary, - dev->path.u.pci.devfn), + dev->path.pci.devfn), where, val); } Modified: coreboot-v3/device/pci_rom.c =================================================================== --- coreboot-v3/device/pci_rom.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/pci_rom.c 2008-08-10 00:20:24 UTC (rev 730) @@ -45,8 +45,8 @@ * or readonly. */ init_archive(&archive); - sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor, - dev->id.u.pci.device); + sprintf(pcifile, "pci%04x,%04x.rom", dev->id.pci.vendor, + dev->id.pci.device); ret = find_file(&archive, pcifile, &result); if (ret) { @@ -108,7 +108,7 @@ printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n", rom_data->vendor, rom_data->device); - if (dev->id.u.pci.vendor != rom_data->vendor || dev->id.u.pci.device != rom_data->device) { + if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device != rom_data->device) { printk(BIOS_ERR, "Device or Vendor ID mismatch Vendor %04x, Device %04x\n", rom_data->vendor, rom_data->device); Modified: coreboot-v3/device/pcie_device.c =================================================================== --- coreboot-v3/device/pcie_device.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/pcie_device.c 2008-08-10 00:20:24 UTC (rev 730) @@ -42,8 +42,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pcie_tune_dev(child); Modified: coreboot-v3/device/pcix_device.c =================================================================== --- coreboot-v3/device/pcix_device.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/pcix_device.c 2008-08-10 00:20:24 UTC (rev 730) @@ -66,8 +66,8 @@ struct device *child; max = pci_scan_bus(bus, min_devfn, max_devfn, max); for (child = bus->children; child; child = child->sibling) { - if ((child->path.u.pci.devfn < min_devfn) || - (child->path.u.pci.devfn > max_devfn)) { + if ((child->path.pci.devfn < min_devfn) || + (child->path.pci.devfn > max_devfn)) { continue; } pcix_tune_dev(child); Modified: coreboot-v3/device/pnp_device.c =================================================================== --- coreboot-v3/device/pnp_device.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/device/pnp_device.c 2008-08-10 00:20:24 UTC (rev 730) @@ -32,19 +32,19 @@ void pnp_write_config(struct device *dev, u8 reg, u8 value) { - outb(reg, dev->path.u.pnp.port); - outb(value, dev->path.u.pnp.port + 1); + outb(reg, dev->path.pnp.port); + outb(value, dev->path.pnp.port + 1); } u8 pnp_read_config(struct device *dev, u8 reg) { - outb(reg, dev->path.u.pnp.port); - return inb(dev->path.u.pnp.port + 1); + outb(reg, dev->path.pnp.port); + return inb(dev->path.pnp.port + 1); } void pnp_set_logical_device(struct device *dev) { - pnp_write_config(dev, 0x07, dev->path.u.pnp.device); + pnp_write_config(dev, 0x07, dev->path.pnp.device); } void pnp_set_enable(struct device *dev, int enable) @@ -238,11 +238,11 @@ int i; path.type = DEVICE_PATH_PNP; - path.u.pnp.port = base_dev->path.u.pnp.port; + path.pnp.port = base_dev->path.pnp.port; /* Setup the ops and resources on the newly allocated devices. */ for (i = 0; i < functions; i++) { - path.u.pnp.device = info[i].function; + path.pnp.device = info[i].function; dev = alloc_find_dev(base_dev->bus, &path, &id); /* Don't initialize a device multiple times. */ Modified: coreboot-v3/include/device/device.h =================================================================== --- coreboot-v3/include/device/device.h 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/include/device/device.h 2008-08-10 00:20:24 UTC (rev 730) @@ -108,7 +108,7 @@ struct apic_cluster_id apic_cluster; struct cpu_id cpu; struct cpu_bus_id cpu_bus; - } u; + }; }; Modified: coreboot-v3/include/device/path.h =================================================================== --- coreboot-v3/include/device/path.h 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/include/device/path.h 2008-08-10 00:20:24 UTC (rev 730) @@ -100,7 +100,7 @@ struct cpu_path cpu; struct cpu_bus_path cpu_bus; struct ioport_path ioport; - } u; + }; }; Modified: coreboot-v3/mainboard/emulation/qemu-x86/vga.c =================================================================== --- coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-08-10 00:20:24 UTC (rev 730) @@ -44,7 +44,7 @@ struct device_operations qemuvga_pci_ops_dev = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS, + {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS, .device = PCI_DEVICE_ID_CIRRUS_5446}}}, .constructor = default_device_constructor, .phase3_scan = 0, Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-08-10 00:20:24 UTC (rev 730) @@ -224,7 +224,7 @@ /** Operations for when the northbridge is running a PCI domain. */ struct device_operations geodelx_north_domain = { .id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, + {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase2_setup_scan_bus = geodelx_pci_domain_phase2, @@ -239,7 +239,7 @@ /** Operations for when the northbridge is running an APIC cluster. */ struct device_operations geodelx_north_apic = { .id = {.type = DEVICE_ID_APIC_CLUSTER, - .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, + {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase3_scan = 0, @@ -257,7 +257,7 @@ */ struct device_operations geodelx_north_pci = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .constructor = default_device_constructor, .phase3_scan = 0, Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c =================================================================== --- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-10 00:20:24 UTC (rev 730) @@ -68,7 +68,7 @@ /* See mainboard/emulation/qemu-x86 for an example of how these are used. */ struct device_operations i440bx_domain = { .id = {.type = DEVICE_ID_PCI_DOMAIN, - .u = {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, + {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}}, .constructor = default_device_constructor, .phase3_scan = pci_domain_scan_bus, .phase4_read_resources = pci_domain_read_resources, Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c =================================================================== --- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-10 00:20:24 UTC (rev 730) @@ -696,7 +696,7 @@ struct device_operations cs5536_ops = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_ISA}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, @@ -708,7 +708,7 @@ struct device_operations cs5536_ide = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}}, .constructor = default_device_constructor, #warning FIXME: what has to go in phase3_scan? Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-08-10 00:20:24 UTC (rev 730) @@ -85,7 +85,7 @@ /* You can override or extend each operation as needed for the device. */ struct device_operations i82371eb_isa = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7000}}}, + {.pci = {.vendor = 0x8086,.device = 0x7000}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, @@ -98,7 +98,7 @@ struct device_operations i82371eb_ide = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7010}}}, + {.pci = {.vendor = 0x8086,.device = 0x7010}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, @@ -111,7 +111,7 @@ struct device_operations i82371eb_acpi = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = 0x8086,.device = 0x7113}}}, + {.pci = {.vendor = 0x8086,.device = 0x7113}}}, .constructor = default_device_constructor, .phase3_scan = 0, .phase4_read_resources = pci_dev_read_resources, Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c =================================================================== --- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-10 00:20:24 UTC (rev 730) @@ -45,10 +45,11 @@ /* the range makes it hard to use the library function. Sorry. * I realize this is not pretty. It would be nice if we could * use anonymous unions. + * We now use anonymous unions. Fix up the code? */ - if ((lpc_dev->id.u.pci.vendor != PCI_VENDOR_ID_NVIDIA) || ( - (lpc_dev->id.u.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || - (lpc_dev->id.u.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) + if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA) || ( + (lpc_dev->id.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) || + (lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO) ) ) { u32 id; id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); @@ -80,16 +81,16 @@ unsigned devfn; /* sorry. Again, anonymous unions etc. would make this easier. */ - if(dev->id.u.pci.device==0x0000) { + if(dev->id.pci.device==0x0000) { vendorid = pci_read_config32(dev, PCI_VENDOR_ID); deviceid = (vendorid>>16) & 0xffff; // vendorid &= 0xffff; } else { // vendorid = dev->vendor; - deviceid = dev->id.u.pci.device; + deviceid = dev->id.pci.device; } - devfn = (dev->path.u.pci.devfn) & ~7; + devfn = (dev->path.pci.devfn) & ~7; switch(deviceid) { case PCI_DEVICE_ID_NVIDIA_MCP55_HT: return; @@ -129,7 +130,7 @@ case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three devfn -= (4<<3); index = 22; - i = (dev->path.u.pci.devfn) & 7; + i = (dev->path.pci.devfn) & 7; if(i>0) { index -= (i+3); } @@ -249,7 +250,7 @@ struct device_operations nvidia_ops = { .id = {.type = DEVICE_ID_PCI, - .u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, + {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA, .device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}}, .constructor = default_device_constructor, .phase3_scan = scan_static_bus, Modified: coreboot-v3/superio/fintek/f71805f/superio.c =================================================================== --- coreboot-v3/superio/fintek/f71805f/superio.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-08-10 00:20:24 UTC (rev 730) @@ -41,12 +41,12 @@ static void pnp_enter_conf_state(struct device *dev) { - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); } static void pnp_exit_conf_state(struct device *dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } void f71805f_pnp_set_resources(struct device *dev) @@ -79,7 +79,7 @@ if (!dev->enabled) return; - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case F71805F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); //TODO: needed? fix or remove? Modified: coreboot-v3/superio/ite/it8716f/superio.c =================================================================== --- coreboot-v3/superio/ite/it8716f/superio.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/superio/ite/it8716f/superio.c 2008-08-10 00:20:24 UTC (rev 730) @@ -37,14 +37,14 @@ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(struct device *dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x01, dev->path.u.pnp.port); - outb(0x55, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x01, dev->path.pnp.port); + outb(0x55, dev->path.pnp.port); - if (dev->path.u.pnp.port == 0x4e) { - outb(0xaa, dev->path.u.pnp.port); + if (dev->path.pnp.port == 0x4e) { + outb(0xaa, dev->path.pnp.port); } else { - outb(0x55, dev->path.u.pnp.port); + outb(0x55, dev->path.pnp.port); } } @@ -142,7 +142,7 @@ conf = dev->device_configuration; /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ - switch (dev->path.u.pnp.device) { + switch (dev->path.pnp.device) { case IT8716F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); // init_uart8250(res0->base, &conf->com1); Modified: coreboot-v3/superio/winbond/w83627hf/superio.c =================================================================== --- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-08-10 00:20:24 UTC (rev 730) @@ -36,13 +36,13 @@ static void pnp_enter_ext_func_mode(struct device * dev) { - outb(0x87, dev->path.u.pnp.port); - outb(0x87, dev->path.u.pnp.port); + outb(0x87, dev->path.pnp.port); + outb(0x87, dev->path.pnp.port); } static void pnp_exit_ext_func_mode(struct device * dev) { - outb(0xaa, dev->path.u.pnp.port); + outb(0xaa, dev->path.pnp.port); } static void pnp_write_index(u16 port_base, u8 reg, u8 value) @@ -73,7 +73,7 @@ #warning Fix CMOS handling // get_option(&power_on, "power_on_after_fail"); pnp_enter_ext_func_mode(dev); - pnp_write_index(dev->path.u.pnp.port,7,0x0a); + pnp_write_index(dev->path.pnp.port,7,0x0a); value = pnp_read_config(dev, 0xE4); value &= ~(3<<5); if(power_on) { @@ -128,7 +128,7 @@ } conf = dev->device_configuration; - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627HF_SP1: res0 = find_resource(dev, PNP_IDX_IO0); #warning init_uart8250 @@ -167,7 +167,7 @@ { pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); - switch(dev->path.u.pnp.device) { + switch(dev->path.pnp.device) { case W83627HF_HWM: printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n"); enable_hwm_smbus(dev); Modified: coreboot-v3/util/dtc/flattree.c =================================================================== --- coreboot-v3/util/dtc/flattree.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/util/dtc/flattree.c 2008-08-10 00:20:24 UTC (rev 730) @@ -551,19 +551,19 @@ if (path && path[1]) { path++; if (!strncmp(tree->name, "cpu", 3)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={ .id = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,{.cpu={ .id = 0x%s }}},\n", path); } if (!strncmp(tree->name, "bus", 3)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_BUS,{.pci_bus={ .bus = 0x%s }}},\n", path); } if (!strncmp(tree->name, "apic", 4)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,{.apic={ 0x%s }}},\n", path); } if (!strncmp(tree->name, "domain", 6)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%s }}},\n", path); } if (!strncmp(tree->name, "pci", 3)){ @@ -580,11 +580,11 @@ else fn = "0"; - fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n", dev, fn); } if (!strncmp(tree->name, "ioport", 6)){ - fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n", + fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x%s}}},\n", path); } } Modified: coreboot-v3/util/x86emu/biosemu.c =================================================================== --- coreboot-v3/util/x86emu/biosemu.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/util/x86emu/biosemu.c 2008-08-10 00:20:24 UTC (rev 730) @@ -323,7 +323,7 @@ int i; unsigned short initialcs = (addr & 0xF0000) >> 4; unsigned short initialip = (addr + 3) & 0xFFFF; - unsigned short devfn = dev->bus->secondary << 8 | dev->path.u.pci.devfn; + unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn; X86EMU_intrFuncs intFuncs[256]; X86EMU_setMemBase(0, 0x100000); Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c =================================================================== --- coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-08-10 00:20:24 UTC (rev 730) @@ -64,7 +64,7 @@ dev = dev_find_pci_device(X86_DX, X86_CX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; - X86_BL = dev->path.u.pci.devfn; + X86_BL = dev->path.pci.devfn; X86_AH = SUCCESSFUL; X86_EFLAGS &= ~FB_CF; /* clear carry flag */ ret = 1; @@ -79,7 +79,7 @@ dev = dev_find_class(X86_ECX, dev); if (dev != 0) { X86_BH = dev->bus->secondary; - X86_BL = dev->path.u.pci.devfn; + X86_BL = dev->path.pci.devfn; X86_AH = SUCCESSFUL; X86_EFLAGS &= ~FB_CF; /* clear carry flag */ ret = 1; Modified: coreboot-v3/util/x86emu/vm86.c =================================================================== --- coreboot-v3/util/x86emu/vm86.c 2008-08-09 21:03:57 UTC (rev 729) +++ coreboot-v3/util/x86emu/vm86.c 2008-08-10 00:20:24 UTC (rev 730) @@ -249,7 +249,7 @@ *(unsigned char *) i = 0; } - real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.u.pci.devfn); + real_mode_switch_call_vga((dev->bus->secondary << 8) | dev->path.pci.devfn); } @@ -603,7 +603,7 @@ // busnum is an unsigned char; // devfn is an int, so we mask it off. busdevfn = (dev->bus->secondary << 8) - | (dev->path.u.pci.devfn & 0xff); + | (dev->path.pci.devfn & 0xff); printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn); *pebx = busdevfn; retval = 0;

1 0

buildrom: Fix ": Unsupported scheme." error message and a typo
by Peter Stuge 09 Aug '08

09 Aug '08

Cristi, note that this was the cause of the error message when I tested your code too. The executed command is: wget "" -P /home/stuge/co/kvm/sources http://kernel.org/pub/linux/kernel/v2.6//linux-2.6.22.2.tar.bz2 And of course wget can't download an empty string. Makefile variables shouldn't have quotes. I can't commit to the buildrom repo so the commiter could change this to := at will, and I'd be fine with that too. :) //Peter

2 1

r218 - in buildrom-devel: . packages/kernel
by svn＠coreboot.org 09 Aug '08

09 Aug '08

Author: ward Date: 2008-08-10 01:10:31 +0200 (Sun, 10 Aug 2008) New Revision: 218 Modified: buildrom-devel/Makefile buildrom-devel/packages/kernel/norwich.mk Log: buildrom: Fix ": Unsupported scheme." error message and a typo Signed-off-by: Peter Stuge <peter(a)stuge.se> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/Makefile =================================================================== --- buildrom-devel/Makefile 2008-08-08 08:43:59 UTC (rev 217) +++ buildrom-devel/Makefile 2008-08-09 23:10:31 UTC (rev 218) @@ -62,9 +62,9 @@ # Pass -q to wget if the user doesn't want to see a download progressbar. ifeq ($(CONFIG_SHOW_DOWNLOAD_PROGRESSBAR),y) -WGET_Q = "" +WGET_Q= else -WGET_Q = "-q" +WGET_Q=-q endif DEPENDS-y= Modified: buildrom-devel/packages/kernel/norwich.mk =================================================================== --- buildrom-devel/packages/kernel/norwich.mk 2008-08-08 08:43:59 UTC (rev 217) +++ buildrom-devel/packages/kernel/norwich.mk 2008-08-09 23:10:31 UTC (rev 218) @@ -10,7 +10,7 @@ $(SOURCE_DIR)/$(KERNEL_SOURCE): @ mkdir -p $(SOURCE_DIR) - @ wget $(wGET_Q) -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE) + @ wget $(WGET_Q) -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE) include $(PACKAGE_DIR)/kernel/kernel.inc

1 0

patch: make low level pci ops really low level.
by ron minnich 09 Aug '08

09 Aug '08

Comment in patch. Tested on dbe62. Note comment w.r.t. regressions, which we need to fix. thanks ron

2 1

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coreboot August 2008