coreboot August 2008

coreboot@coreboot.org

64 participants
593 discussions

r727 - in coreboot-v3/arch/x86: . amd
by svn＠coreboot.org 09 Aug '08

09 Aug '08

Author: hailfinger Date: 2008-08-09 21:16:43 +0200 (Sat, 09 Aug 2008) New Revision: 727 Modified: coreboot-v3/arch/x86/amd/stage0.S coreboot-v3/arch/x86/stage0_i586.S Log: Change the GAS bug workaround in CAR code to be more readable. The problem was that gas treated whitespace asargument delimiter. Removing the whitespace in crtitical places is the most obvious fix. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/arch/x86/amd/stage0.S =================================================================== --- coreboot-v3/arch/x86/amd/stage0.S 2008-08-09 15:59:17 UTC (rev 726) +++ coreboot-v3/arch/x86/amd/stage0.S 2008-08-09 19:16:43 UTC (rev 727) @@ -275,15 +275,10 @@ * windowoffset is the 32k-aligned window into CAR size */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) - extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) - extractmask gas_bug_workaround, %edx -/* Without the gas bug workaround, the entire macro would consist only of the - * two lines below. - extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - extractmask (((\carsize - \windowoffset) / 0x1000)), %edx - */ +/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is + * interpreted as an argument delimiter by some versions of GNU as. */ + extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax + extractmask (((\carsize-\windowoffset)/0x1000)), %edx .endm #if CacheSize > 0x10000 Modified: coreboot-v3/arch/x86/stage0_i586.S =================================================================== --- coreboot-v3/arch/x86/stage0_i586.S 2008-08-09 15:59:17 UTC (rev 726) +++ coreboot-v3/arch/x86/stage0_i586.S 2008-08-09 19:16:43 UTC (rev 727) @@ -319,15 +319,10 @@ * windowoffset is the 32k-aligned window into CAR size */ .macro simplemask carsize, windowoffset - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) - extractmask gas_bug_workaround, %eax - .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) - extractmask gas_bug_workaround, %edx -/* Without the gas bug workaround, the entire macro would consist only of the - * two lines below. - extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - extractmask (((\carsize - \windowoffset) / 0x1000)), %edx - */ +/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is + * interpreted as an argument delimiter by some versions of GNU as. */ + extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax + extractmask (((\carsize-\windowoffset)/0x1000)), %edx .endm #if CacheSize > 0x10000

1 0

[flashrom] convert lb_ to cb_
by Sean Nelson 09 Aug '08

09 Aug '08

change all references of lb_/LB_ to cb_/CB_ in flashrom Signed-off-by: Sean Nelson <snelson(a)nmt.edu> ---

4 6

v3 make distclean broken
by Carl-Daniel Hailfinger 09 Aug '08

09 Aug '08

Hi, I have a v3 tree (svn HEAD) which refuses to run "make clean" or "make distclean". Steps to reproduce: Simply drop the attached .config in any recent v3 tree, then try to run "make clean". /sources/tmptrees/corebootv3-car_gas_bug_workaround> make distclean Makefile:113: mainboard//Makefile: No such file or directory make: *** No rule to make target `mainboard//Makefile'. Stop. Removing .config fixes it. I'd appreciate hints or fixes. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

help with K8
by ron minnich 09 Aug '08

09 Aug '08

I can always use good help :=) anyone want to look at this? HOSTCC build/util/options/build_opt_tbl OPTIONS build/mainboard/gigabyte/m57sli/option_table.c Error - Range end (122) does not match define (125) in line checksum 392 983 984 I don't even understand the error ... in line ? ron

2 1

r726 - coreboot-v3/mainboard/gigabyte/m57sli
by svn＠coreboot.org 09 Aug '08

09 Aug '08

Author: hailfinger Date: 2008-08-09 17:59:17 +0200 (Sat, 09 Aug 2008) New Revision: 726 Modified: coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout Log: Fix the following build error: OPTIONS build/mainboard/gigabyte/m57sli/option_table.c Error - Range end (122) does not match define (125) in line checksum 392 983 984 cmos.layout did not conform to the requirements of the option table creation code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout 2008-08-09 13:45:22 UTC (rev 725) +++ coreboot-v3/mainboard/gigabyte/m57sli/cmos.layout 2008-08-09 15:59:17 UTC (rev 726) @@ -114,6 +114,6 @@ checksums -checksum 392 983 984 +checksum 392 1007 1008

1 0

r725 - coreboot-v3/arch/x86/amd
by svn＠coreboot.org 09 Aug '08

09 Aug '08

Author: hailfinger Date: 2008-08-09 15:45:22 +0200 (Sat, 09 Aug 2008) New Revision: 725 Modified: coreboot-v3/arch/x86/amd/stage0.S Log: Remove Family 10h revision Ax support from v3 CAR code. This is an errata for early silicon and is not mentioned in the public rev guide. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: coreboot-v3/arch/x86/amd/stage0.S =================================================================== --- coreboot-v3/arch/x86/amd/stage0.S 2008-08-06 23:31:35 UTC (rev 724) +++ coreboot-v3/arch/x86/amd/stage0.S 2008-08-09 13:45:22 UTC (rev 725) @@ -212,15 +212,6 @@ #endif -#ifdef CONFIG_CPU_AMD_K10 - /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. - Re-enable it in after RAM is initialized and before CAR is disabled */ - movl $0xc001102a, %ecx - rdmsr - bts $15, %eax - wrmsr -#endif - /* Set MtrrFixDramModEn for clear fixed mtrr */ enable_fixed_mtrr_dram_modify: movl $SYSCFG_MSR, %ecx

1 0

patch: grow grafix memory, and fix PLL on dbe62
by ron minnich 09 Aug '08

09 Aug '08

This grows graphics mem to 16M per artec's recommendation. The PLL autoconfig works now, so move to an auto value instead of manual config. This does not fix the problem with the memory errors. We've still got something wrong in memory, and it is not clear what. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> I forgot it in the patch. ron

7 20

Porting ASUS P5P800-VM
by abhijit sarma 09 Aug '08

09 Aug '08

Hi All, I want to run coreboot in my PC but the motherboard is not supported. The southbridge, superio and the cpu etc seems to be supported. How can I create a new target. I can modify the code if I know the relevent details. The main board is ASUS P5P800-VM Socket 775, Intel 865G + Intel ICH5, Dual Channel DDR 8xAGP VGA Integrated The vendors support page is: - http://support.asus.com/download/download_item.aspx?product=1&model=P5P800-… superiotools output is: - superiotool r3429 Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e The lspci output is: - 00:00.0 Host bridge: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface (rev 02) 00:02.0 VGA compatible controller: Intel Corporation 82865G Integrated Graphics Controller (rev 02) 00:1d.0 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 (rev 02) 00:1d.1 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 (rev 02) 00:1d.2 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 (rev 02) 00:1d.3 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 (rev 02) 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2) 00:1f.0 ISA bridge: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller (rev 02) 00:1f.2 IDE interface: Intel Corporation 82801EB (ICH5) SATA Controller (rev 02) 00:1f.5 Multimedia audio controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller (rev 02) 01:0d.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10) Abhijit

1 0

[PATCH] libpayload - add block io functions
by Stefan Reinauer 08 Aug '08

08 Aug '08

see patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

r3490 - trunk/payloads/coreinfo/util/kconfig
by svn＠coreboot.org 08 Aug '08

08 Aug '08

Author: stepan Date: 2008-08-08 20:36:14 +0200 (Fri, 08 Aug 2008) New Revision: 3490 Modified: trunk/payloads/coreinfo/util/kconfig/Makefile Log: i messed this up. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/payloads/coreinfo/util/kconfig/Makefile =================================================================== --- trunk/payloads/coreinfo/util/kconfig/Makefile 2008-08-08 14:17:46 UTC (rev 3489) +++ trunk/payloads/coreinfo/util/kconfig/Makefile 2008-08-08 18:36:14 UTC (rev 3490) @@ -4,7 +4,7 @@ PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config -Kconfig := Config.in +Kconfig := Kconfig xconfig: prepare $(objk)/qconf $(Q)$(objk)/qconf $(Kconfig)

1 0

← Newer
1
...
41
42
43
44
45
46
47
...
60
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot August 2008