coreboot April 2008

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r3270 - in trunk/payloads/libpayload: drivers include libc
by svn＠coreboot.org 25 Apr '08

25 Apr '08

Author: jcrouse Date: 2008-04-26 01:09:39 +0200 (Sat, 26 Apr 2008) New Revision: 3270 Modified: trunk/payloads/libpayload/drivers/keyboard.c trunk/payloads/libpayload/include/libpayload.h trunk/payloads/libpayload/libc/console.c Log: libpayload: Enable keyboard translation so that we can use scancode set 1 The qemu keyboard controller defaults to using scancode set 2, we use set 1. Turn on the translate mode in the keyboard controller to force the issue. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/payloads/libpayload/drivers/keyboard.c =================================================================== --- trunk/payloads/libpayload/drivers/keyboard.c 2008-04-25 23:08:47 UTC (rev 3269) +++ trunk/payloads/libpayload/drivers/keyboard.c 2008-04-25 23:09:39 UTC (rev 3270) @@ -29,6 +29,11 @@ #include <libpayload.h> +#define I8042_CMD_READ_MODE 0x20 +#define I8042_CMD_WRITE_MODE 0x60 + +#define I8042_MODE_XLATE 0x40 + unsigned char map[2][0x57] = { { 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, @@ -118,3 +123,54 @@ return ret; } + +static int keyboard_wait_read(void) +{ + int timeout = 10000; + + while(timeout-- && !(inb(0x64) & 0x01)) + udelay(50); + + return (timeout <= 0) ? -1 : 0; +} + +static int keyboard_wait_write(void) +{ + int timeout = 10000; + + while(timeout-- && (inb(0x64) & 0x02)) + udelay(50); + + return (timeout <= 0) ? -1 : 0; +} + +static unsigned char keyboard_get_mode(void) +{ + outb(I8042_CMD_READ_MODE, 0x64); + keyboard_wait_read(); + return inb(0x60); +} + +static void keyboard_set_mode(unsigned char mode) +{ + outb(I8042_CMD_WRITE_MODE, 0x64); + keyboard_wait_write(); + outb(mode, 0x60); +} + +void keyboard_init(void) +{ + u8 mode; + + /* Read the current mode */ + mode = keyboard_get_mode(); + + /* Turn on scancode translate mode so that we can + use the scancode set 1 tables */ + + mode |= I8042_MODE_XLATE; + + /* Write the new mode */ + keyboard_set_mode(mode); +} + Modified: trunk/payloads/libpayload/include/libpayload.h =================================================================== --- trunk/payloads/libpayload/include/libpayload.h 2008-04-25 23:08:47 UTC (rev 3269) +++ trunk/payloads/libpayload/include/libpayload.h 2008-04-25 23:09:39 UTC (rev 3270) @@ -67,6 +67,7 @@ void nvram_write(u8 val, u8 addr); /* drivers/keyboard.c */ +void keyboard_init(void); int keyboard_havechar(void); unsigned char keyboard_get_scancode(void); int keyboard_getchar(void); Modified: trunk/payloads/libpayload/libc/console.c =================================================================== --- trunk/payloads/libpayload/libc/console.c 2008-04-25 23:08:47 UTC (rev 3269) +++ trunk/payloads/libpayload/libc/console.c 2008-04-25 23:09:39 UTC (rev 3270) @@ -37,6 +37,9 @@ #ifdef CONFIG_SERIAL_CONSOLE serial_init(); #endif +#ifdef CONFIG_PC_KEYBOARD + keyboard_init(); +#endif } static void device_putchar(unsigned char c)

1 0

r3269 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 25 Apr '08

25 Apr '08

Author: jcrouse Date: 2008-04-26 01:08:47 +0200 (Sat, 26 Apr 2008) New Revision: 3269 Modified: trunk/payloads/libpayload/libc/malloc.c Log: libpayload: Fix malloc allocation Apparently the previous version worked on luck. Fix the allocation and add parens to better guide the compiler. Also, halt() if the heap is poisoned (like by an overrun). Finally, fix calloc() so that it actually works. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/payloads/libpayload/libc/malloc.c =================================================================== --- trunk/payloads/libpayload/libc/malloc.c 2008-04-25 23:07:39 UTC (rev 3268) +++ trunk/payloads/libpayload/libc/malloc.c 2008-04-25 23:08:47 UTC (rev 3269) @@ -67,7 +67,8 @@ static void setup(void) { - int size = (unsigned int)(_heap - _eheap) - HDRSIZE; + int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE; + *((hdrtype_t *) hstart) = FREE_BLOCK(size); } @@ -91,9 +92,12 @@ header = *((hdrtype_t *) ptr); int size = SIZE(header); + if (!HAS_MAGIC(header) || size == 0) + halt(); + if (header & FLAG_FREE) { if (len <= size) { - void *nptr = ptr + HDRSIZE + len; + void *nptr = ptr + (HDRSIZE + len); int nsize = size - (len + 8); /* Mark the block as used. */ @@ -102,6 +106,7 @@ /* If there is still room in this block, * then mark it as such. */ + if (nsize > 0) *((hdrtype_t *) nptr) = FREE_BLOCK(nsize - 4); @@ -184,8 +189,8 @@ void *calloc(size_t nmemb, size_t size) { - unsigned int total = (nmemb * size); - void *ptr = alloc(size); + size_t total = nmemb * size; + void *ptr = alloc(total); if (ptr) memset(ptr, 0, total);

1 0

r3268 - trunk/payloads/libpayload/libc
by svn＠coreboot.org 25 Apr '08

25 Apr '08

Author: jcrouse Date: 2008-04-26 01:07:39 +0200 (Sat, 26 Apr 2008) New Revision: 3268 Modified: trunk/payloads/libpayload/libc/string.c Log: libpayload: Add the null terminator to the end of the duplicated string Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/payloads/libpayload/libc/string.c =================================================================== --- trunk/payloads/libpayload/libc/string.c 2008-04-25 22:56:57 UTC (rev 3267) +++ trunk/payloads/libpayload/libc/string.c 2008-04-25 23:07:39 UTC (rev 3268) @@ -173,11 +173,12 @@ char *strdup(const char *s) { int n = strlen(s); - char *p = malloc(n); + char *p = malloc(n + 1); if (p != NULL) strncpy(p, s, n); + p[n] = 0; return p; }

1 0

[patch][v2] serengeti_cheetah_fam10 abuild
by Marc Jones 25 Apr '08

25 Apr '08

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb. The FAM10 code takes up more space in the uncompressed "ROMCC" portion of coreboot. Also, It is still growing as features are added. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2008-04-25 13:47:58.000000000 -0600 +++ coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2008-04-25 13:52:24.000000000 -0600 @@ -13,7 +13,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x22200 + option ROM_IMAGE_SIZE=0x3f000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end

2 3

r3267 - trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10
by svn＠coreboot.org 25 Apr '08

25 Apr '08

Author: mjones Date: 2008-04-26 00:56:57 +0200 (Sat, 26 Apr 2008) New Revision: 3267 Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb Log: Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb. The FAM10 code takes up more space in the uncompressed "ROMCC" portion of coreboot. Also, It is still growing as features are added. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb =================================================================== --- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2008-04-25 21:34:25 UTC (rev 3266) +++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2008-04-25 22:56:57 UTC (rev 3267) @@ -13,7 +13,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 - option ROM_IMAGE_SIZE=0x22200 + option ROM_IMAGE_SIZE=0x3f000 option COREBOOT_EXTRA_VERSION=".0-fallback" payload __PAYLOAD__ end

1 0

r3266 build service
by coreboot information 25 Apr '08

25 Apr '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "mjones" checked in revision 3266 to the coreboot source repository and caused the following changes: Change Log: Remove inline from FAM10 CPU initialization functions. This doesn't save any space for me but it is the right thing to allow GCC to optimize. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3266&device=serengeti_chee… If something broke during this checkin please be a pain in mjones's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[patch][v2] remove inline functions in fam10 source
by Marc Jones 25 Apr '08

25 Apr '08

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Remove inline from FAM10 CPU initialization functions. This should save some ROM space. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/fidvid.c 2008-04-24 16:58:10.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c 2008-04-24 16:03:23.000000000 -0600 @@ -25,21 +25,21 @@ // if we are tight of CAR stack, disable it #define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 -static inline void print_debug_fv(const char *str, u32 val) +static void print_debug_fv(const char *str, u32 val) { #if FAM10_SET_FIDVID_DEBUG == 1 printk_debug("%s%x\n", str, val); #endif } -static inline void print_debug_fv_8(const char *str, u8 val) +static void print_debug_fv_8(const char *str, u8 val) { #if FAM10_SET_FIDVID_DEBUG == 1 printk_debug("%s%02x\n", str, val); #endif } -static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) +static void print_debug_fv_64(const char *str, u32 val, u32 val2) { #if FAM10_SET_FIDVID_DEBUG == 1 printk_debug("%s%x%x\n", str, val, val2); Index: coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-24 16:58:15.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-24 16:03:21.000000000 -0600 @@ -30,24 +30,24 @@ #define FAM10_SET_FIDVID_CORE0_ONLY 0 #endif -static inline void print_initcpu8 (const char *strval, u8 val) +static void print_initcpu8 (const char *strval, u8 val) { printk_debug("%s%02x\n", strval, val); } -static inline void print_initcpu8_nocr (const char *strval, u8 val) +static void print_initcpu8_nocr (const char *strval, u8 val) { printk_debug("%s%02x", strval, val); } -static inline void print_initcpu16 (const char *strval, u16 val) +static void print_initcpu16 (const char *strval, u16 val) { printk_debug("%s%04x\n", strval, val); } -static inline void print_initcpu(const char *strval, u32 val) +static void print_initcpu(const char *strval, u32 val) { printk_debug("%s%08x\n", strval, val); } @@ -59,7 +59,7 @@ void cpuSetAMDMSR(void); #if PCI_IO_CFG_EXT == 1 -static inline void set_EnableCf8ExtCfg(void) +static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; msr_t msr; @@ -69,7 +69,7 @@ wrmsr(NB_CFG_MSR, msr); } #else -static inline void set_EnableCf8ExtCfg(void) { } +static void set_EnableCf8ExtCfg(void) { } #endif @@ -78,7 +78,7 @@ /* because we will use gs to store hi, so need to make sure lo can start from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/ -static inline void set_pci_mmio_conf_reg(void) +static void set_pci_mmio_conf_reg(void) { #if MMCONF_SUPPORT msr_t msr; @@ -184,7 +184,7 @@ } /* FIXME: Duplicate of what is in lapic.h? */ -static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) +static int lapic_remote_read(int apicid, int reg, u32 *pvalue) { int timeout; u32 status; Index: coreboot-v2/src/cpu/amd/quadcore/quadcore.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/quadcore/quadcore.c 2008-04-24 17:30:29.000000000 -0600 +++ coreboot-v2/src/cpu/amd/quadcore/quadcore.c 2008-04-24 16:06:06.000000000 -0600 @@ -24,7 +24,7 @@ #include "cpu/amd/quadcore/quadcore_id.c" -static inline u32 get_core_num_in_bsp(u32 nodeid) +static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); @@ -34,7 +34,7 @@ } #if SET_NB_CFG_54 == 1 -static inline u8 set_apicid_cpuid_lo(void) +static u8 set_apicid_cpuid_lo(void) { // set the NB_CFG[54]=1; why the OS will be happy with that ??? msr_t msr; @@ -46,12 +46,12 @@ } #else -static inline void set_apicid_cpuid_lo(void) { } +static void set_apicid_cpuid_lo(void) { } #endif -static inline void real_start_other_core(u32 nodeid, u32 cores) +static void real_start_other_core(u32 nodeid, u32 cores) { u32 dword; @@ -78,7 +78,7 @@ } //it is running on core0 of node0 -static inline void start_other_cores(void) +static void start_other_cores(void) { u32 nodes; u32 nodeid; Index: coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/quadcore/quadcore_id.c 2008-04-24 17:30:36.000000000 -0600 +++ coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c 2008-04-24 16:06:04.000000000 -0600 @@ -32,7 +32,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static inline u32 get_initial_apicid(void) +static u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xff); } @@ -67,12 +67,12 @@ return id; } -static inline u32 get_core_num(void) +static u32 get_core_num(void) { return (cpuid_ecx(0x80000008) & 0xff); } -static inline struct node_core_id get_node_core_id_x(void) { +static struct node_core_id get_node_core_id_x(void) { return get_node_core_id( read_nb_cfg_54() ); } Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-24 17:33:57.000000000 -0600 +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-24 16:11:12.000000000 -0600 @@ -102,7 +102,7 @@ } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +static void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 int ret,i; @@ -119,7 +119,7 @@ } -static inline int spd_read_byte(u32 device, u32 address) +static int spd_read_byte(u32 device, u32 address) { int result; result = smbus_read_byte(device, address); Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mct_d_gcc.h 2008-04-24 17:33:15.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h 2008-04-24 16:07:47.000000000 -0600 @@ -18,7 +18,7 @@ */ -static inline void _WRMSR(u32 addr, u32 lo, u32 hi) +static void _WRMSR(u32 addr, u32 lo, u32 hi) { __asm__ volatile ( "wrmsr" @@ -28,7 +28,7 @@ } -static inline void _RDMSR(u32 addr, u32 *lo, u32 *hi) +static void _RDMSR(u32 addr, u32 *lo, u32 *hi) { __asm__ volatile ( "rdmsr" @@ -38,7 +38,7 @@ } -static inline void _RDTSC(u32 *lo, u32 *hi) +static void _RDTSC(u32 *lo, u32 *hi) { __asm__ volatile ( "rdtsc" @@ -47,7 +47,7 @@ } -static inline void _cpu_id(u32 addr, u32 *val) +static void _cpu_id(u32 addr, u32 *val) { __asm__ volatile( "cpuid" @@ -60,7 +60,7 @@ } -static inline u32 bsr(u32 x) +static u32 bsr(u32 x) { u8 i; u32 ret = 0; @@ -77,7 +77,7 @@ } -static inline u32 bsf(u32 x) +static u32 bsf(u32 x) { u8 i; u32 ret = 32; @@ -99,7 +99,7 @@ /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") -static inline u32 read_cr4(void) +static u32 read_cr4(void) { u32 cr4; __asm__ volatile ("movl %%cr4, %0" : "=r" (cr4)); @@ -107,7 +107,7 @@ } -static inline void write_cr4(u32 cr4) +static void write_cr4(u32 cr4) { __asm__ volatile ("movl %0, %%cr4" : : "r" (cr4)); } Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c =================================================================== --- coreboot-v2.orig/src/northbridge/amd/amdmct/mct/mctdqs_d.c 2008-04-24 17:33:28.000000000 -0600 +++ coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c 2008-04-24 16:07:45.000000000 -0600 @@ -65,7 +65,7 @@ #define DQS_TRAIN_DEBUG 0 -static inline void print_debug_dqs(const char *str, u32 val, u8 level) +static void print_debug_dqs(const char *str, u32 val, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -74,7 +74,7 @@ #endif } -static inline void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) +static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) {

4 6

r3266 - in trunk/coreboot-v2/src: cpu/amd/model_10xxx cpu/amd/quadcore mainboard/amd/serengeti_cheetah_fam10 northbridge/amd/amdmct/mct
by svn＠coreboot.org 25 Apr '08

25 Apr '08

Author: mjones Date: 2008-04-25 23:34:25 +0200 (Fri, 25 Apr 2008) New Revision: 3266 Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore.c trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c Log: Remove inline from FAM10 CPU initialization functions. This doesn't save any space for me but it is the right thing to allow GCC to optimize. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/fidvid.c 2008-04-25 21:34:25 UTC (rev 3266) @@ -25,21 +25,21 @@ // if we are tight of CAR stack, disable it #define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 -static inline void print_debug_fv(const char *str, u32 val) +static void print_debug_fv(const char *str, u32 val) { #if FAM10_SET_FIDVID_DEBUG == 1 printk_debug("%s%x\n", str, val); #endif } -static inline void print_debug_fv_8(const char *str, u8 val) +static void print_debug_fv_8(const char *str, u8 val) { #if FAM10_SET_FIDVID_DEBUG == 1 printk_debug("%s%02x\n", str, val); #endif } -static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) +static void print_debug_fv_64(const char *str, u32 val, u32 val2) { #if FAM10_SET_FIDVID_DEBUG == 1 printk_debug("%s%x%x\n", str, val, val2); Modified: trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-25 21:34:25 UTC (rev 3266) @@ -30,24 +30,24 @@ #define FAM10_SET_FIDVID_CORE0_ONLY 0 #endif -static inline void print_initcpu8 (const char *strval, u8 val) +static void print_initcpu8 (const char *strval, u8 val) { printk_debug("%s%02x\n", strval, val); } -static inline void print_initcpu8_nocr (const char *strval, u8 val) +static void print_initcpu8_nocr (const char *strval, u8 val) { printk_debug("%s%02x", strval, val); } -static inline void print_initcpu16 (const char *strval, u16 val) +static void print_initcpu16 (const char *strval, u16 val) { printk_debug("%s%04x\n", strval, val); } -static inline void print_initcpu(const char *strval, u32 val) +static void print_initcpu(const char *strval, u32 val) { printk_debug("%s%08x\n", strval, val); } @@ -59,7 +59,7 @@ void cpuSetAMDMSR(void); #if PCI_IO_CFG_EXT == 1 -static inline void set_EnableCf8ExtCfg(void) +static void set_EnableCf8ExtCfg(void) { // set the NB_CFG[46]=1; msr_t msr; @@ -69,7 +69,7 @@ wrmsr(NB_CFG_MSR, msr); } #else -static inline void set_EnableCf8ExtCfg(void) { } +static void set_EnableCf8ExtCfg(void) { } #endif @@ -78,7 +78,7 @@ /* because we will use gs to store hi, so need to make sure lo can start from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/ -static inline void set_pci_mmio_conf_reg(void) +static void set_pci_mmio_conf_reg(void) { #if MMCONF_SUPPORT msr_t msr; @@ -184,7 +184,7 @@ } /* FIXME: Duplicate of what is in lapic.h? */ -static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) +static int lapic_remote_read(int apicid, int reg, u32 *pvalue) { int timeout; u32 status; Modified: trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore.c 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore.c 2008-04-25 21:34:25 UTC (rev 3266) @@ -24,7 +24,7 @@ #include "cpu/amd/quadcore/quadcore_id.c" -static inline u32 get_core_num_in_bsp(u32 nodeid) +static u32 get_core_num_in_bsp(u32 nodeid) { u32 dword; dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8); @@ -34,7 +34,7 @@ } #if SET_NB_CFG_54 == 1 -static inline u8 set_apicid_cpuid_lo(void) +static u8 set_apicid_cpuid_lo(void) { // set the NB_CFG[54]=1; why the OS will be happy with that ??? msr_t msr; @@ -46,12 +46,12 @@ } #else -static inline void set_apicid_cpuid_lo(void) { } +static void set_apicid_cpuid_lo(void) { } #endif -static inline void real_start_other_core(u32 nodeid, u32 cores) +static void real_start_other_core(u32 nodeid, u32 cores) { u32 dword; @@ -78,7 +78,7 @@ } //it is running on core0 of node0 -static inline void start_other_cores(void) +static void start_other_cores(void) { u32 nodes; u32 nodeid; Modified: trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/cpu/amd/quadcore/quadcore_id.c 2008-04-25 21:34:25 UTC (rev 3266) @@ -32,7 +32,7 @@ return ( ( msr.hi >> (54-32)) & 1); } -static inline u32 get_initial_apicid(void) +static u32 get_initial_apicid(void) { return ((cpuid_ebx(1) >> 24) & 0xff); } @@ -67,12 +67,12 @@ return id; } -static inline u32 get_core_num(void) +static u32 get_core_num(void) { return (cpuid_ecx(0x80000008) & 0xff); } -static inline struct node_core_id get_node_core_id_x(void) { +static struct node_core_id get_node_core_id_x(void) { return get_node_core_id( read_nb_cfg_54() ); } Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2008-04-25 21:34:25 UTC (rev 3266) @@ -102,7 +102,7 @@ } -static inline void activate_spd_rom(const struct mem_controller *ctrl) +static void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 int ret,i; @@ -119,7 +119,7 @@ } -static inline int spd_read_byte(u32 device, u32 address) +static int spd_read_byte(u32 device, u32 address) { int result; result = smbus_read_byte(device, address); Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d_gcc.h 2008-04-25 21:34:25 UTC (rev 3266) @@ -60,7 +60,7 @@ } -static inline u32 bsr(u32 x) +static u32 bsr(u32 x) { u8 i; u32 ret = 0; @@ -77,7 +77,7 @@ } -static inline u32 bsf(u32 x) +static u32 bsf(u32 x) { u8 i; u32 ret = 32; Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c =================================================================== --- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c 2008-04-25 02:02:33 UTC (rev 3265) +++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mctdqs_d.c 2008-04-25 21:34:25 UTC (rev 3266) @@ -65,7 +65,7 @@ #define DQS_TRAIN_DEBUG 0 -static inline void print_debug_dqs(const char *str, u32 val, u8 level) +static void print_debug_dqs(const char *str, u32 val, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) { @@ -74,7 +74,7 @@ #endif } -static inline void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) +static void print_debug_dqs_pair(const char *str, u32 val, const char *str2, u32 val2, u8 level) { #if DQS_TRAIN_DEBUG > 0 if (DQS_TRAIN_DEBUG >= level) {

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[patch][v2] fam10 AP CAR cleanup
by Marc Jones 25 Apr '08

25 Apr '08

-- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors On APs the ClLinesToNbDis was being left enabled from CAR setup. Disabling it should help performance. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c =================================================================== --- coreboot-v2.orig/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-23 17:08:42.000000000 -0600 +++ coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c 2008-04-23 17:11:01.000000000 -0600 @@ -295,6 +295,13 @@ static void STOP_CAR_AND_CPU() { + msr_t msr; + + /* Disable L2 IC to L3 connection (Only for CAR) */ + msr = rdmsr(BU_CFG2); + msr.lo &= ~(1 << ClLinesToNbDis); + wrmsr(BU_CFG2, msr); + disable_cache_as_ram(); // inline stop_this_cpu(); }

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Re: [coreboot] r156 - in buildrom-devel: config/platforms packages/coreboot-v2 packages/filo/conf packages/kernel packages/kernel/conf
by Uwe Hermann 25 Apr '08

25 Apr '08

On Thu, Apr 24, 2008 at 03:41:18PM +0200, svn(a)coreboot.org wrote: > Copied: buildrom-devel/packages/coreboot-v2/tyan-generic.mk (from rev 152, buildrom-devel/packages/coreboot-v2/tyan-s2891.mk) > =================================================================== > --- buildrom-devel/packages/coreboot-v2/tyan-generic.mk (rev 0) > +++ buildrom-devel/packages/coreboot-v2/tyan-generic.mk 2008-04-24 13:41:17 UTC (rev 156) > @@ -0,0 +1,43 @@ > +# This is the Generic coreboot target Generic Tyan target maybe. > +ifeq ($(CONFIG_PAYLOAD_KERNEL),y) > + CBV2_CONFIG = Config-lab.lb > + CBV2_PAYLOAD_FILE_EXT = elf.lzma > +endif > + > +ifeq ($(CONFIG_PAYLOAD_LAB),y) > + CBV2_CONFIG = Config-lab.lb > + CBV2_PAYLOAD_FILE_EXT = elf.lzma > +endif Can we move this snippet to a generic file? I think it's the same for all LAB targets but appears many times in various board files. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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coreboot April 2008