November 2008 - coreboot - mail.coreboot.org

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release
by coreboot Feb. 16, 2009

Feb. 16, 2009

#105: flashrom: add documentation files (ChangeLog etc) that need to be in the release ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: documentation | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/105> coreboot <http://www.coreboot.org/>

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[PATCH] Fix bayou payload execution
by Ulf Jordan Feb. 10, 2009

Feb. 10, 2009

Bayou svn HEAD cannot execute its payloads correctly, due to payloads overwriting bayou in memory. This is in turn due to the lpgcc link run trying to apply both libpayload's and bayou's ldscripts. The two attached patches a) makes lpgcc's choice of ldscript overridable and b) adjusts bayou's ldscript to work with the recent MB changes in libpayload. Compile and runtime tested with bayou, coreinfo and coreboot-v3 in QEMU. /ulf

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flashrom on intel dg33tl
by Andriy Gapon Feb. 2, 2009

Feb. 2, 2009

Below is output of flashrom -V. It couldn't find the flash chip. This is ICH9 (G33) chipset. There is one WARNING and one FAILED messages. Calibrating delay loop... 257M loops per second, 100 myus = 196 us. OK. No coreboot table found. Found chipset "Intel ICH9R", enabling flash write... BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0xa tried to set 0xdc to 0xb on Intel ICH9R failed (WARNING ONLY) Root Complex Register Block address = 0xfed1c000 GCS = 0xc01444: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x00: 0x0035 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 0, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000a0b (FRAP) BMWAG 0, BMRAG 0, BRWA 10, BRRA 11 0x54: 0x00000000 (FREG0) 0x58: 0x00ff0035 (FREG1) 0x5C: 0x00340003 (FREG2) 0x60: 0x00020001 (FREG3) 0x64: 0x00000fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0xB0: 0x00000000 (FDOC) SPI Read Configuration: prefetching enabled, caching enabled, FAILED! Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for ASD AE49F2008, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES... done RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A25L40P, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for EMST F49B002UA, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x3, id2 0x75 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x3, id2 0x75 Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x3, id2 0x55 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1005, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L2005, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L4005, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L8005, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L1605, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L3205, 4096 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX25L6405, 8192 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xf9, id2 0x63 Probing for Numonyx M25PE10, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE20, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE40, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE80, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Numonyx M25PE16, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV010, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV020, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV040, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm25LV512, 64 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC Pm49FL002, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for PMC Pm49FL004, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF016B, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST25VF040B, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x3, id2 0x55 Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST29EE020A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xeb, id2 0xce, id1 parity violation Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF002A/B, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST49LF003A/B, 384 KB: probe_jedec: id1 0x81, id2 0x7c, id1 parity violation Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x3, id2 0x55 Probing for SST SST49LF008A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF040B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SST SST49LF080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P10-A, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P20, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P40, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P40-old, 512 KB: RDID returned 1f 45 01. Probing for ST M25P80, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P16, 2048 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P32, 4096 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P64, 8192 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M25P128, 16384 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST M29F002B, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for ST M29F002T/NT, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x3, id2 0x55 Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x3, id2 0x75 Probing for ST M29W010B, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for ST M29W040B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0x3, id2 0x55 Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0x3, id2 0x55 Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xf9, id2 0x63 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x3, id2 0x55 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for SyncMOS S29C31004T, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for SyncMOS S29C51001T, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for SyncMOS S29C51002T, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for SyncMOS S29C51004T, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W25x10, 128 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25x20, 256 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25x40, 512 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W25x80, 1024 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Winbond W29C011, 128 KB: probe_jedec: id1 0x32, id2 0x0 Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W29EE011, 128 KB: === Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. === Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0x3, id2 0x55, id1 parity violation Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W49F002U, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W49V002FA, 256 KB: probe_jedec: id1 0xf9, id2 0x63, id1 parity violation Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: vid 0xff, did 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: vid 0x3, did 0x55 Probing for EON unknown EON SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for Macronix unknown Macronix SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for PMC unknown PMC SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for SST unknown SST SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 Probing for ST unknown ST SPI chip, 0 KB: RDID returned 1f 45 01. probe_spi_rdid_generic: id1 0x1f, id2 0x4501 No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. -- Andriy Gapon

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[LinuxBIOS] Add initial support for intel i855gme northbridge
by Jon Dufresne Jan. 20, 2009

Jan. 20, 2009

Add initial support for i855gme. This is a work in progress and I don't expect it to work on all boards, or even any besides mine. This is based heavily on i855pm. Signed off by Jon Dufresne <jon.dufresne(a)gmail.com>

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2 keypoints to use coreboot+seabios to achieve WINDOWS-XP's s3 sleep/resume
by JasonZhao＠viatech.com.cn Dec. 19, 2008

Dec. 19, 2008

Firstly, you need download two patchs:the Kevin's for using Seabios as payload, and Rudolf's for s3. http://www.coreboot.org/pipermail/coreboot/2008-September/038551.html www.coreboot.org/pipermail/coreboot/2008-January/028787.html Then there are two steps to do (Rudolf gave me much advice on IRC :-) , he is a good teacher) #1 Since OS put some realmode code to the s3 resume vector before it demands the mainboard to enter sleep, we need to backup the resume code before coreboot using real memory(may destroy the resume code) and recovery it before Coreboot jumps into the resume vector. In the main()of cache_as_ram_auto.c, just before the stack switching code, add this: if( (bootmode == 3){ print_debug("copy memory to high memory to protect s3 wakeup vector code \r\n"); memcpy((unsigned char *)(highmem_bakaddress),(unsigned char *)0, 0x100000);//highmem_bakaddress=512M-xxM } In the acpi_jump_wake() of wakeup.c, add this: memcpy((unsigned char *)(resumevector), (unsigned char *)(highmem_bakaddress+resumevector), 0x1000); //(ubuntu's vector=0x2000, XP's =0x1c000, but you should just get this from the FACS table as in Kevin's patch, even he move the FACS to the highend memory) #2 Since when resume from S3, coreboot do not go into payload, so in vga driver codes need be added to do vga init after it judged that this is a boot waked from s3. if(acpi_sleep_type==3) {printk_debug("Enable VGA console\n"); vga_enable_console();} if(acpi_sleep_type==3) {xxxxxx} if(acpi_sleep_type==3) {xxxxxx}

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option roms in SeaBIOS and Coreboot
by Rudolf Marek Dec. 9, 2008

Dec. 9, 2008

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, I obtained some SAS PCIe card. I have some good and bad news ;) 1) it does not work at all, PCI ROM signature wrong. 2) it does work with some help glitch 3) it does not work as expected I solved 1) with a simple hack patch (attached) The PCI ROM BARs should not be relocated. The K8 processor has some PCI hole resource and imho there is a problem that even the PCI hole starts at TOPMEM, it still hits RAM because of video framebuffer for integrated VGA. I fixed this isssue by not touching PCI ROM base, check the patch. 2) It does work! PCI option rom get executed. This particular ROM has "press space to skip" option, and if I do that I get to grub/linux whatever. 3) If I do not press space, the PCI option rom is supposed to init the HW. it just freezes somewhere inside, but keyboard IRQ still delivered. With original BIOS, some other screen is printed with another screen mode, but it freezes too ;))) Some remark to the end. I'm not sure if next_rom pointer should be adjusted before the rom is copied. In my case VGA has someting like 36KB and with 2K align it gets to 0xCA000 for next ROM. I tried with ALIGN of 64KB but it does not help that particular silly option rom :) Maybe the align should be handled also depending on actual rom size. I mean "allow spaces for aligns between roms". Rudolf Here are some debug messages: Attempting to find coreboot table Copying ACPI RSDP from 1bff0000 to 000ff330 init SMBIOS tables Found 1 cpu(s) SMBIOS table addr=0x000ff350 ram_size=0x1bff0000 Scan for VGA option rom Attempting to init PCI bdf 00000100 Copying option rom from fff80000 (ROM) to 000c0000 (RAM) Running option rom at 0000c000:00000003 fail handle_155fXX:47(00000086): a=00005f18 b=000002e4 c=00000000 d=000003c3 si=00000000 di=0000e261 ds=00000000 es=0000f000 ip=00008c26 cs=0000c000 f=00000006 r=00007926 Turning on vga console Starting SeaBIOS ... ... Attempting to map option rom on dev 000000c3 Option rom sizing returned 00000000 00000000 Attempting to init PCI bdf 00000200 Attempting to map option rom on dev 00000200 Option rom sizing returned f1100000 fffc0000 Card 00000200 option rom mapped at f1100000 Copying option rom from f1100000 (ROM) to 000d0000 (RAM) Running option rom at 0000d000:00000003 Changing serial settings was 00000003/00000002 now 00000003/00000000 Attempting to init PCI bdf 00000408 Attempting to map option rom on dev 00000408 Option rom sizing returned 00000000 00000000 Press F12 for boot menu. Some example of PCI/MEMORY resources, from another computer via the k8resdump (check Coreboot util) DRAM map: #0 0x0000000000 - 0x003fffffff Access: R/W IntlvEN:0x0 IntlvSEL:0x0 Dstnode:0 DRAM map: #1 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:1 DRAM map: #2 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:2 DRAM map: #3 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:3 DRAM map: #4 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:4 DRAM map: #5 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:5 DRAM map: #6 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:6 DRAM map: #7 0x0000000000 - 0x0000ffffff Access: / IntlvEN:0x0 IntlvSEL:0x0 Dstnode:7 MMIO map: #0 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #1 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #2 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #3 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #4 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #5 0x0000000000 - 0x000000ffff Access: / Dstnode:0 DstLink 0 MMIO map: #6 0x00000a0000 - 0x00000bffff Access: R/W Dstnode:0 DstLink 0 MMIO map: #7 0x0040000000 - 0x00ff70ffff Access: R/W Dstnode:0 DstLink 0 IO map: #0 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0 IO map: #1 0x001000 - 0x0fffff Access: R/W VGA Dstnode:0 DstLink 0 IO map: #2 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0 IO map: #3 0x000000 - 0x000fff Access: / Dstnode:0 DstLink 0 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkkrNaEACgkQ3J9wPJqZRNWa6gCeLV7DszkrcuNR0vGzzZs9GW7H ALQAmgKV18+HnsAGgmRNiKM3enmYT6Xe =PXog -----END PGP SIGNATURE-----

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#102: flashrom: coreboot ROM image file identification heuristic is broken
by coreboot Dec. 8, 2008

Dec. 8, 2008

#102: flashrom: coreboot ROM image file identification heuristic is broken -----------------------------------+---------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: blocker | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: rom image heuristic | Dependencies: Patchstatus: patch needs work | -----------------------------------+---------------------------------------- Non-coreboot ROM images are incorrectly identified as coreboot images, and arbitrary data is used in flashrom code. The heuristic is far too simplistic, we need a proper signature in all coreboot images. The suggested fix is to add a LAR header to the ROM image, I like that too. When an image is incorrectly identified, junk data used by flashrom typically causes flashrom to segfault. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/102> coreboot <http://www.coreboot.org/>

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Re: [coreboot] Spi flash
by Carl-Daniel Hailfinger Dec. 7, 2008

Dec. 7, 2008

Hi Yves, please keep the list in CC so they know what's going on. Thanks. On 13.11.2008 18:51, Dupont Yves wrote: > here is the corresponding dump : > > Calibrating delay loop... 326M loops per second, 100 myus = 193 us. OK. > No coreboot table found. > Found chipset "Intel ICH7M", enabling flash write... > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) > [...] > SPI Read Configuration: prefetching disabled, caching enabled, OK. > [...] > Probing for Atmel AT25DF321, 4096 KB: Programming OPCODES... done > RDID returned ff ff ff. > The flash chip doesn't support RDID. > RDID byte 0 parity violation. > probe_spi_rdid_generic: id1 0xff, id2 0xffff > [...] > Probing for ST M25P40-old, 512 KB: RDID returned ff ff ff. > RES returned 13. > But the chip supports RES. > probe_spi_res: id 0x13 > [....] > No EEPROM/flash device found. > The big problem is that ~30 chips from different manufacturers with different sizes all have the same RES ID. I will try to cook up a patch checking REMS (which is more accurate). > It seems to bea SPI flash device but I don't want to open my laptop. > Any idea? > I will create a patch to improve detection, but that may take a week or so. If you don't hear anything back from me in the next 7 days, please ask me for a status. Regards, Carl-Daniel -- http://www.hailfinger.org/

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#107: flashrom: Display test status in -L chip listing
by coreboot Dec. 6, 2008

Dec. 6, 2008

#107: flashrom: Display test status in -L chip listing ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: testing | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/107> coreboot <http://www.coreboot.org/>

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[PATCH] inteltool: i965, i975, ICH8M and Darwin support.
by Stefan Reinauer Dec. 4, 2008

Dec. 4, 2008

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Patch to util/inteltool: * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO This does not include additional changes from Lu Zhihe yet, I'll integrate them in the next iteration. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: gpio.c =================================================================== --- gpio.c (revision 3783) +++ gpio.c (working copy) @@ -18,7 +18,6 @@ */ #include <stdio.h> -#include <sys/io.h> #include "inteltool.h" static const io_register_t ich0_gpio_registers[] = { @@ -78,6 +77,26 @@ { 0x3C, 4, "RESERVED" } }; +static const io_register_t ich8_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, + { 0x04, 4, "GP_IO_SEL" }, + { 0x08, 4, "RESERVED" }, + { 0x0c, 4, "GP_LVL" }, + { 0x10, 4, "GPIO_USE_SEL Override (LOW)" }, + { 0x14, 4, "RESERVED" }, + { 0x18, 4, "GPO_BLINK" }, + { 0x1c, 4, "GP_SER_BLINK" }, + { 0x20, 4, "GP_SB_CMDSTS" }, + { 0x24, 4, "GP_SB_DATA" }, + { 0x28, 4, "RESERVED" }, + { 0x2c, 4, "GPI_INV" }, + { 0x30, 4, "GPIO_USE_SEL2" }, + { 0x34, 4, "GP_IO_SEL2" }, + { 0x38, 4, "GP_LVL2" }, + { 0x3C, 4, "GPIO_USE_SEL Override (HIGH)" } +}; + + int print_gpios(struct pci_dev *sb) { int i, size; @@ -87,6 +106,11 @@ printf("\n============= GPIOS =============\n\n"); switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH8M: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = ich8_gpio_registers; + size = ARRAY_SIZE(ich8_gpio_registers); + break; case PCI_DEVICE_ID_INTEL_ICH7: case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: Index: inteltool.h =================================================================== --- inteltool.h (revision 3783) +++ inteltool.h (working copy) @@ -18,6 +18,11 @@ */ #include <stdint.h> +#ifndef DARWIN +#include <sys/io.h> +#else +#include <DirectIO/darwinio.h> +#endif #include <pci/pci.h> #define INTELTOOL_VERSION "1.0" @@ -33,17 +38,23 @@ #define PCI_DEVICE_ID_INTEL_ICH7 0x27b8 #define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7MDH 0x27bd +#define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 +#define PCI_DEVICE_ID_INTEL_PM965 0x2a00 +#define PCI_DEVICE_ID_INTEL_82975X 0x277c #define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0]))) +#ifndef DARWIN typedef struct { uint32_t hi, lo; } msr_t; +#endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; -extern int fd_mem; +void *map_physical(unsigned long phys_addr, int len); +void unmap_physical(void *virt_addr, int len); unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); Index: pcie.c =================================================================== --- pcie.c (revision 3783) +++ pcie.c (working copy) @@ -19,8 +19,6 @@ #include <stdio.h> #include <stdlib.h> -#include <sys/mman.h> - #include "inteltool.h" /* @@ -30,15 +28,20 @@ { int i, size = (4 * 1024); volatile uint8_t *epbar; - uint32_t epbar_phys; + uint64_t epbar_phys; printf("\n============= EPBAR =============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; + epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have EPBAR.\n"); return 1; @@ -47,21 +50,20 @@ return 1; } - epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) epbar_phys); + epbar = map_physical(epbar_phys, size); - if (epbar == MAP_FAILED) { + if (epbar == NULL) { perror("Error mapping EPBAR"); exit(1); } - printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys); + printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(epbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i)); } - munmap((void *)epbar, size); + unmap_physical((void *)epbar, size); return 0; } @@ -72,15 +74,20 @@ { int i, size = (4 * 1024); volatile uint8_t *dmibar; - uint32_t dmibar_phys; + uint64_t dmibar_phys; printf("\n============= DMIBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; + dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have DMIBAR.\n"); return 1; @@ -89,21 +96,20 @@ return 1; } - dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) dmibar_phys); + dmibar = map_physical(dmibar_phys, size); - if (dmibar == MAP_FAILED) { + if (dmibar == NULL) { perror("Error mapping DMIBAR"); exit(1); } - printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys); + printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(dmibar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i)); } - munmap((void *)dmibar, size); + unmap_physical((void *)dmibar, size); return 0; } @@ -112,8 +118,8 @@ */ int print_pciexbar(struct pci_dev *nb) { - uint32_t pciexbar_reg; - uint32_t pciexbar_phys; + uint64_t pciexbar_reg; + uint64_t pciexbar_phys; volatile uint8_t *pciexbar; int max_busses, devbase, i; int bus, dev, fn; @@ -123,8 +129,13 @@ switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: pciexbar_reg = pci_read_long(nb, 0x48); break; + case PCI_DEVICE_ID_INTEL_PM965: + pciexbar_reg = pci_read_long(nb, 0x60); + pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("Error: This northbrigde does not have PCIEXBAR.\n"); return 1; @@ -140,15 +151,15 @@ switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); + pciexbar_phys = pciexbar_reg & (0xff << 28); max_busses = 256; break; case 1: // 128M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); + pciexbar_phys = pciexbar_reg & (0x1ff << 27); max_busses = 128; break; case 2: // 64M - pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); + pciexbar_phys = pciexbar_reg & (0x3ff << 26); max_busses = 64; break; default: // RSVD @@ -156,12 +167,11 @@ return 1; } - printf("PCIEXBAR: 0x%08x\n", pciexbar_phys); + printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys); - pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ, - MAP_SHARED, fd_mem, (off_t) pciexbar_phys); + pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024)); - if (pciexbar == MAP_FAILED) { + if (pciexbar == NULL) { perror("Error mapping PCIEXBAR"); exit(1); } @@ -194,7 +204,7 @@ } } - munmap((void *)pciexbar, (max_busses * 1024 * 1024)); + unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024)); return 0; } Index: powermgt.c =================================================================== --- powermgt.c (revision 3783) +++ powermgt.c (working copy) @@ -19,8 +19,6 @@ */ #include <stdio.h> -#include <sys/io.h> - #include "inteltool.h" int print_pmbase(struct pci_dev *sb) @@ -35,6 +33,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8M: pmbase = pci_read_word(sb, 0x40) & 0xfffc; break; case 0x1234: // Dummy for non-existent functionality @@ -48,6 +47,13 @@ printf("PMBASE = 0x%04x (IO)\n\n", pmbase); for (i = 0; i < size; i += 4) { +#ifdef DARWIN + if (i==0x14) { + /* Reading this register will hang a macbook pro */ + printf("pmbase+0x%04x: 0xXXXXXXXX\n", i); + continue; + } +#endif printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i)); } Index: cpu.c =================================================================== --- cpu.c (revision 3783) +++ cpu.c (working copy) @@ -33,13 +33,18 @@ unsigned int ret; unsigned int dummy2, dummy3, dummy4; asm volatile ( - "cpuid" - : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) + "pushl %%ebx \n" + "cpuid \n" + "movl %%ebx, %1 \n" + "popl %%ebx \n" + : "=a" (ret), "=r" (dummy2), "=c" (dummy3), "=d" (dummy4) : "a" (op) + : "cc" ); return ret; } +#ifndef DARWIN int msr_readerror = 0; msr_t rdmsr(int addr) @@ -72,6 +77,7 @@ return msr; } +#endif int print_intel_core_msrs(void) { @@ -273,12 +279,14 @@ return -1; } +#ifndef DARWIN fd_msr = open("/dev/cpu/0/msr", O_RDWR); if (fd_msr < 0) { perror("Error while opening /dev/cpu/0/msr"); printf("Did you run 'modprobe msr'?\n"); return -1; } +#endif printf("\n===================== SHARED MSRs (All Cores) =====================\n"); @@ -292,6 +300,7 @@ close(fd_msr); for (core = 0; core < 8; core++) { +#ifndef DARWIN char msrfilename[64]; memset(msrfilename, 0, 64); sprintf(msrfilename, "/dev/cpu/%d/msr", core); @@ -303,7 +312,7 @@ */ if (fd_msr < 0) break; - +#endif printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core); for (i = 0; i < cpu->num_per_core_msrs; i++) { @@ -312,13 +321,15 @@ cpu->per_core_msrs[i].number, msr.hi, msr.lo, cpu->per_core_msrs[i].name); } - +#ifndef DARWIN close(fd_msr); +#endif } +#ifndef DARWIN if (msr_readerror) printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n"); - +#endif return 0; } Index: rootcmplx.c =================================================================== --- rootcmplx.c (revision 3783) +++ rootcmplx.c (working copy) @@ -18,18 +18,8 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include <errno.h> -#include <fcntl.h> -#include <unistd.h> #include <stdio.h> -#include <string.h> #include <stdlib.h> -#include <stdint.h> -#include <getopt.h> -#include <sys/mman.h> -#include <sys/io.h> -#include <pci/pci.h> - #include "inteltool.h" int print_rcba(struct pci_dev *sb) @@ -45,6 +35,7 @@ case PCI_DEVICE_ID_INTEL_ICH7M: case PCI_DEVICE_ID_INTEL_ICH7DH: case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8M: rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; break; case PCI_DEVICE_ID_INTEL_ICH: @@ -58,10 +49,9 @@ return 1; } - rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) rcba_phys); + rcba = map_physical(rcba_phys, size); - if (rcba == MAP_FAILED) { + if (rcba == NULL) { perror("Error mapping RCBA"); exit(1); } @@ -73,7 +63,7 @@ printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i)); } - munmap((void *)rcba, size); + unmap_physical((void *)rcba, size); return 0; } Index: memory.c =================================================================== --- memory.c (revision 3783) +++ memory.c (working copy) @@ -20,8 +20,6 @@ #include <stdio.h> #include <stdlib.h> -#include <sys/mman.h> - #include "inteltool.h" /* @@ -31,15 +29,20 @@ { int i, size = (16 * 1024); volatile uint8_t *mchbar; - uint32_t mchbar_phys; + uint64_t mchbar_phys; printf("\n============= MCHBAR ============\n\n"); switch (nb->device_id) { case PCI_DEVICE_ID_INTEL_82945GM: case PCI_DEVICE_ID_INTEL_82945P: + case PCI_DEVICE_ID_INTEL_82975X: mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; break; + case PCI_DEVICE_ID_INTEL_PM965: + mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); return 1; @@ -48,22 +51,21 @@ return 1; } - mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t) mchbar_phys); + mchbar = map_physical(mchbar_phys, size); - if (mchbar == MAP_FAILED) { + if (mchbar == NULL) { perror("Error mapping MCHBAR"); exit(1); } - printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys); + printf("MCHBAR = 0x%08llx (MEM)\n\n", mchbar_phys); for (i = 0; i < size; i += 4) { if (*(uint32_t *)(mchbar + i)) printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i)); } - munmap((void *)mchbar, size); + unmap_physical((void *)mchbar, size); return 0; } Index: inteltool.c =================================================================== --- inteltool.c (revision 3783) +++ inteltool.c (working copy) @@ -21,9 +21,8 @@ #include <stdio.h> #include <stdlib.h> #include <getopt.h> -#include <sys/io.h> #include <fcntl.h> - +#include <sys/mman.h> #include "inteltool.h" static const struct { @@ -33,6 +32,9 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8M, "ICH8-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7MDH, "ICH7-M DH" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" }, @@ -44,8 +46,30 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" } }; -int fd_mem; +#ifndef DARWIN +static int fd_mem; +void *map_physical(unsigned long phys_addr, int len) +{ + void *virt_addr; + + virt_addr = mmap(0, len, PROT_WRITE | PROT_READ, MAP_SHARED, + fd_mem, (off_t) phys_addr); + + if (virt_addr == MAP_FAILED) { + printf("Error mapping physical memory 0x%08x[0x%x]\n", phys_addr, len); + return NULL; + } + + return virt_addr; +} + +void unmap_physical(void *virt_addr, int len) +{ + munmap((void *)rcba, size); +} +#endif + void print_version(void) { printf("inteltool v%s -- ", INTELTOOL_VERSION); @@ -164,10 +188,12 @@ exit(1); } +#ifndef DARWIN if ((fd_mem = open("/dev/mem", O_RDWR)) < 0) { perror("Can not open /dev/mem"); exit(1); } +#endif pacc = pci_alloc(); pci_init(pacc); Index: Makefile =================================================================== --- Makefile (revision 3783) +++ Makefile (working copy) @@ -29,6 +29,13 @@ OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o +OS_ARCH = $(shell uname) +ifeq ($(OS_ARCH), Darwin) +CFLAGS += -DDARWIN -I/usr/local/include +LDFLAGS = -framework IOKit -framework DirectIO -L/usr/local/lib -lpci -lz +# OBJS += darwinio.o +endif + all: pciutils dep $(PROGRAM) $(PROGRAM): $(OBJS) @@ -41,10 +48,10 @@ rm -f .dependencies dep: - @$(CC) -MM *.c > .dependencies + @$(CC) $(CFLAGS) -MM *.c > .dependencies pciutils: - @echo; echo -n "Checking for pciutils and zlib... " + @echo; /bin/echo -n "Checking for pciutils and zlib... " @$(shell ( echo "#include <pci/pci.h>"; \ echo "struct pci_access *pacc;"; \ echo "int main(int argc, char **argv)"; \ @@ -54,12 +61,12 @@ echo "Please install pciutils-devel and zlib-devel."; \ echo "See README for more information."; echo; \ rm -f .test.c .test; exit 1) - @rm -f .test.c .test + @rm -rf .test.c .test .test.dSYM install: $(PROGRAM) - $(INSTALL) $(PROGRAM) $(PREFIX)/sbin - mkdir -p $(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin + mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils

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