November 2008 - coreboot - mail.coreboot.org

[PATCH] flashrom: Add a bunch of new IDs
by Carl-Daniel Hailfinger Dec. 4, 2008

Dec. 4, 2008

Add RDID/REMS IDs for the following flash chips: SST_25VF512A_REMS SST_25VF010_REMS SST_25VF020_REMS SST_25VF040_REMS SST_25VF040B_REMS SST_25VF080_REMS SST_25VF080B_REMS SST_25VF032B_REMS SST_26VF016 SST_26VF032 W_25X16 W_25X32 W_25X64 Straight from the data sheets. The REMS IDs help in case the RDID opcode is unavailable (due to opcode lockdown) or unsupported by the chip. Some day, we need to pair probe functions together with IDs. Multiple pairs can exist per chip and duplicating chip definitions does not really make sense. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_sst_winbond_chips/flash.h =================================================================== --- flashrom-spi_sst_winbond_chips/flash.h (Revision 3773) +++ flashrom-spi_sst_winbond_chips/flash.h (Arbeitskopie) @@ -289,10 +289,20 @@ #define SST_25WF010 0x2502 #define SST_25WF020 0x2503 #define SST_25WF040 0x2504 +#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */ +#define SST_25VF010_REMS 0x49 /* REMS or RES opcode */ +#define SST_25VF020_REMS 0x43 /* REMS or RES opcode */ +#define SST_25VF040_REMS 0x44 /* REMS or RES opcode */ +#define SST_25VF040B 0x258D +#define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */ +#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */ +#define SST_25VF080B 0x258E +#define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */ #define SST_25VF016B 0x2541 #define SST_25VF032B 0x254A -#define SST_25VF040B 0x258D -#define SST_25VF080B 0x258E +#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_26VF016 0x2601 +#define SST_26VF032 0x2602 #define SST_27SF512 0xA4 #define SST_27SF010 0xA5 #define SST_27SF020 0xA6 @@ -377,6 +387,9 @@ #define W_25X20 0x3012 #define W_25X40 0x3013 #define W_25X80 0x3014 +#define W_25X16 0x3015 +#define W_25X32 0x3016 +#define W_25X64 0x3017 #define W_29C011 0xC1 #define W_29C020C 0x45 #define W_29C040P 0x46 -- http://www.hailfinger.org/

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[PATCH] v3: make inline asm declarations consistent
by Carl-Daniel Hailfinger Dec. 4, 2008

Dec. 4, 2008

v3 uses all combinations of __asm__, asm, __volatile__, volatile and single variations to declare inline asm statements. "asm" is a GNU C extension, while volatile is ANSI C. That means: - __volatile__ can be replaced by volatile unless you use a pure K&R compiler. - asm is not a reserved keyword and should be replaced by __asm__. As a bonus, grepping for __asm__ returns less hits than asm because asm is also used as a normal word in comments. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/msr.h =================================================================== --- corebootv3-inline_asm_consistent_underscores/include/arch/x86/msr.h (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/msr.h (Arbeitskopie) @@ -36,7 +36,7 @@ static inline struct msr rdmsr(u32 index) { struct msr result; - __asm__ __volatile__ ( + __asm__ volatile ( "rdmsr" : "=a" (result.lo), "=d" (result.hi) : "c" (index) @@ -46,7 +46,7 @@ static inline void wrmsr(u32 index, struct msr msr) { - __asm__ __volatile__ ( + __asm__ volatile ( "wrmsr" : /* No outputs */ : "c" (index), "a" (msr.lo), "d" (msr.hi) Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/io.h =================================================================== --- corebootv3-inline_asm_consistent_underscores/include/arch/x86/io.h (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/io.h (Arbeitskopie) @@ -28,43 +28,43 @@ static inline void outb(u8 value, u16 port) { - __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port)); + __asm__ volatile ("outb %b0, %w1" : : "a" (value), "Nd" (port)); } static inline void outw(u16 value, u16 port) { - __asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port)); + __asm__ volatile ("outw %w0, %w1" : : "a" (value), "Nd" (port)); } static inline void outl(u32 value, u16 port) { - __asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port)); + __asm__ volatile ("outl %0, %w1" : : "a" (value), "Nd" (port)); } static inline u8 inb(u16 port) { u8 value; - __asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port)); + __asm__ volatile ("inb %w1, %b0" : "=a"(value) : "Nd" (port)); return value; } static inline u16 inw(u16 port) { u16 value; - __asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port)); + __asm__ volatile ("inw %w1, %w0" : "=a"(value) : "Nd" (port)); return value; } static inline u32 inl(u16 port) { u32 value; - __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port)); + __asm__ volatile ("inl %w1, %0" : "=a"(value) : "Nd" (port)); return value; } static inline void outsb(u16 port, const void *addr, unsigned long count) { - __asm__ __volatile__ ( + __asm__ volatile ( "cld ; rep ; outsb " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) @@ -73,7 +73,7 @@ static inline void outsw(u16 port, const void *addr, unsigned long count) { - __asm__ __volatile__ ( + __asm__ volatile ( "cld ; rep ; outsw " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) @@ -82,7 +82,7 @@ static inline void outsl(u16 port, const void *addr, unsigned long count) { - __asm__ __volatile__ ( + __asm__ volatile ( "cld ; rep ; outsl " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) @@ -92,7 +92,7 @@ static inline void insb(u16 port, void *addr, unsigned long count) { - __asm__ __volatile__ ( + __asm__ volatile ( "cld ; rep ; insb " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) @@ -101,7 +101,7 @@ static inline void insw(u16 port, void *addr, unsigned long count) { - __asm__ __volatile__ ( + __asm__ volatile ( "cld ; rep ; insw " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) @@ -110,7 +110,7 @@ static inline void insl(u16 port, void *addr, unsigned long count) { - __asm__ __volatile__ ( + __asm__ volatile ( "cld ; rep ; insl " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/arch/spinlock.h =================================================================== --- corebootv3-inline_asm_consistent_underscores/include/arch/x86/arch/spinlock.h (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/arch/spinlock.h (Arbeitskopie) @@ -29,7 +29,7 @@ * * We make no fairness assumptions. They have a cost. */ -#define barrier() __asm__ __volatile__("": : :"memory") +#define barrier() __asm__ volatile("": : :"memory") #define spin_is_locked(x) (*(volatile char *)(&(x)->lock) <= 0) #define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x)) @@ -53,14 +53,14 @@ static inline __attribute__((always_inline)) void spin_lock(struct spinlock *lock) { - __asm__ __volatile__( + __asm__ volatile( spin_lock_string :"=m" (lock->lock) : : "memory"); } static inline __attribute__((always_inline)) void spin_unlock(struct spinlock *lock) { - __asm__ __volatile__( + __asm__ volatile( spin_unlock_string :"=m" (lock->lock) : : "memory"); } Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/cpu.h =================================================================== --- corebootv3-inline_asm_consistent_underscores/include/arch/x86/cpu.h (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/cpu.h (Arbeitskopie) @@ -149,23 +149,23 @@ static inline unsigned long read_cr0(void) { unsigned long cr0; - asm volatile("movl %%cr0, %0" : "=r" (cr0)); + __asm__ volatile("movl %%cr0, %0" : "=r" (cr0)); return cr0; } static inline void write_cr0(unsigned long cr0) { - asm volatile("movl %0, %%cr0" : : "r" (cr0)); + __asm__ volatile("movl %0, %%cr0" : : "r" (cr0)); } static inline void invd(void) { - asm volatile("invd" : : : "memory"); + __asm__ volatile("invd" : : : "memory"); } static inline void wbinvd(void) { - asm volatile("wbinvd"); + __asm__ volatile("wbinvd"); } static inline void enable_cache(void) @@ -194,7 +194,7 @@ */ static inline void cpu_relax(void) { - __asm__ __volatile__("rep; nop" : : : "memory"); + __asm__ volatile("rep; nop" : : : "memory"); } /** @@ -206,7 +206,7 @@ */ static inline __attribute__((always_inline)) void hlt(void) { - __asm__ __volatile__("hlt" : : : "memory"); + __asm__ volatile("hlt" : : : "memory"); } /** @@ -216,7 +216,7 @@ */ static inline void clear_memory(void *addr, unsigned long size) { - asm volatile( + __asm__ volatile( "cld \n\t" "rep; stosl\n\t" : /* No outputs */ Index: corebootv3-inline_asm_consistent_underscores/include/arch/x86/lapic.h =================================================================== --- corebootv3-inline_asm_consistent_underscores/include/arch/x86/lapic.h (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/include/arch/x86/lapic.h (Arbeitskopie) @@ -93,19 +93,19 @@ { switch (size) { case 1: - __asm__ __volatile__("xchgb %b0,%1" + __asm__ volatile("xchgb %b0,%1" :"=q" (x) :"m" (*__xg(ptr)), "0" (x) :"memory"); break; case 2: - __asm__ __volatile__("xchgw %w0,%1" + __asm__ volatile("xchgw %w0,%1" :"=r" (x) :"m" (*__xg(ptr)), "0" (x) :"memory"); break; case 4: - __asm__ __volatile__("xchgl %0,%1" + __asm__ volatile("xchgl %0,%1" :"=r" (x) :"m" (*__xg(ptr)), "0" (x) :"memory"); Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/k8/dqs.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/northbridge/amd/k8/dqs.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/k8/dqs.c (Arbeitskopie) @@ -139,13 +139,13 @@ static inline unsigned long read_cr4(void) { unsigned long cr4; - asm volatile ("movl %%cr4, %0" : "=r" (cr4)); + __asm__ volatile ("movl %%cr4, %0" : "=r" (cr4)); return cr4; } static inline void write_cr4(unsigned long cr4) { - asm volatile ("movl %0, %%cr4" : : "r" (cr4)); + __asm__ volatile ("movl %0, %%cr4" : : "r" (cr4)); } Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/raminit.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/raminit.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/raminit.c (Arbeitskopie) @@ -815,7 +815,7 @@ post_code(POST_MEM_SETUP_GOOD); /* Make sure there is nothing stale in the cache. */ - /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */ + /* CAR stack is in the cache __asm__ volatile("wbinvd\n"); */ /* The RAM dll needs a write to lock on so generate a few dummy * writes. Note: The descriptor needs to be enabled to point at memory. Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/vsmsetup.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/vsmsetup.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/vsmsetup.c (Arbeitskopie) @@ -50,7 +50,7 @@ u16 entryHi = (VSA2_ENTRY_POINT & 0xffff0000) >> 4; u16 entryLo = (VSA2_ENTRY_POINT & 0xffff); - __asm__ __volatile__( + __asm__ volatile( /* Paranoia -- does ecx get saved? not sure. This is * the easiest safe thing to do. */ @@ -148,7 +148,7 @@ u32 VSA_vrRead(u16 classIndex) { unsigned eax, ebx, ecx, edx; - asm volatile ( + __asm__ volatile ( "movw $0x0AC1C, %%dx \n" "orl $0x0FC530000, %%eax \n" "outl %%eax, %%dx \n" @@ -164,7 +164,7 @@ u32 VSA_msrRead(u32 msrAddr) { unsigned eax, ebx, ecx, edx; - asm volatile ( + __asm__ volatile ( "movw $0x0AC1C, %%dx \n" "movl $0x0FC530007, %%eax \n" "outl %%eax, %%dx \n" Index: corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/geodelxinit.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/northbridge/amd/geodelx/geodelxinit.c (Arbeitskopie) @@ -758,7 +758,7 @@ GLPCI_init(); clock_gating_init(); - __asm__ __volatile__("FINIT\n"); /* TODO: Create finit() function? */ + __asm__ volatile("FINIT\n"); /* TODO: Create finit() function? */ printk(BIOS_DEBUG, "Exit %s\n", __FUNCTION__); } Index: corebootv3-inline_asm_consistent_underscores/arch/x86/geodelx/stage1.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/arch/x86/geodelx/stage1.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/arch/x86/geodelx/stage1.c (Arbeitskopie) @@ -65,8 +65,8 @@ * the data back over itself, and the wbinvd should then * flush to memory. Let's see. */ - __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); - __asm__ __volatile__ ("wbinvd\n"); + __asm__ volatile("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory"); + __asm__ volatile ("wbinvd\n"); banner(BIOS_DEBUG, "Disable_car: done wbinvd"); northbridge_init_early(); banner(BIOS_DEBUG, "disable_car: done"); Index: corebootv3-inline_asm_consistent_underscores/arch/x86/archtables.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/arch/x86/archtables.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/arch/x86/archtables.c (Arbeitskopie) @@ -54,7 +54,7 @@ memcpy((void*)newgdt, &gdt, num_gdt_bytes); gdtarg.base = newgdt; gdtarg.limit = num_gdt_bytes - 1; - __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); + __asm__ volatile ("lgdt %0\n\t" : : "m" (gdtarg)); printk(BIOS_DEBUG,"OK\n"); } #endif Index: corebootv3-inline_asm_consistent_underscores/arch/x86/amd/k8/stage1.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/arch/x86/amd/k8/stage1.c (Revision 858) +++ corebootv3-inline_asm_consistent_underscores/arch/x86/amd/k8/stage1.c (Arbeitskopie) @@ -45,7 +45,7 @@ * The solution for geode of using a inline asm memcpy of the stack * onto itself will not mark the cache tags as dirty on K8. */ - __asm__ __volatile__( + __asm__ volatile( " movl %[carbase], %%esi \n" " movl %[backuplocation], %%edi \n" " movl %[carsizequads], %%ecx \n" Index: corebootv3-inline_asm_consistent_underscores/arch/x86/stage1.c =================================================================== --- corebootv3-inline_asm_consistent_underscores/arch/x86/stage1.c (Revision 856) +++ corebootv3-inline_asm_consistent_underscores/arch/x86/stage1.c (Arbeitskopie) @@ -117,7 +117,7 @@ u64 cycles(void) { u64 ret; - asm volatile ("rdtsc" : "=A" (ret)); + __asm__ volatile ("rdtsc" : "=A" (ret)); return ret; } -- http://www.hailfinger.org/

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#109: flash base autodetection on AMD SC520
by coreboot Dec. 3, 2008

Dec. 3, 2008

#109: flash base autodetection on AMD SC520 ----------------------------------+----------------------------------------- Reporter: stepan | Owner: stepan Type: defect | Status: new Priority: major | Milestone: Component: adlo | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- this code has been sitting on my hard disk for a while. It drops the nasty ifdefs and implements auto detection for AMD SC520 systems, such as the Technologic Systems TS5300. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/109> coreboot <http://www.coreboot.org/>

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Free chips, not required by me, and a question
by Chris Lingard Dec. 2, 2008

Dec. 2, 2008

I have: 6 W38V040 12 SST25VF032B, (tiny little chips) Anybody want them, just send a snail mail address? Now I need help, my machine has Pm49FL004 chips as standard, I have some Pm49FL008 too. I want a 32 M Bit flash chip, if there is such a thing for this type of chip, please let me know the part number. (I would much appreciate the exact detail, as the supplier asks incomprehensible questions) Chris Lingard

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Patches for ACPI support on dbm690t (RS600 and SB600)
by Bao, Zheng Dec. 2, 2008

Dec. 2, 2008

Hi, Attachment are the patches for Chipset AMD RS690, AMD SB600 and mainboard DBM690T. The following ACPI features are supported. 1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse). 2. AMD powernow-k8 driver. 3. Thermal configuration based on ADT7461. 4. IDE timing settings. 5. HPET timer. 6. Interrupt routing based on ACPI table. Signed-off-by: Joe Bao <zheng.bao(a)amd.com> Reviewed-by: Maggie Li <maggie.li(a)amd.com>

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tyan s2875 processor issues
by Darren F. Hall Dec. 2, 2008

Dec. 2, 2008

Hello everyone, I've been working working on getting coreboot to run on a Tyan Tiger S2875 with filo but have run into a problem coreboot can't seem to initialize the second cpu. The boards running two AMD Opteron 250's. With the proprietary bios both processors will show up under /proc/cpuinfo but under coreboot only 1 will. Coreboot's logs complain about being unable to start 'cpu 0x01'. Looking through the list archives I saw a similiar problem with with a Tyan S2882 but couldn't locate an answer. Below is the debugging output using SVN 3730, on debug level 8. Any help would be appreciated. Thanks. --------------------------------------------------- coreboot-2.0.0_Fallback Thu Jan 1 00:06:26 EST 2004 starting... (0,1) link=01 (1,0) link=01 02 nodes initialized. SBLink=00 NC node|link=00 ht reset - coreboot-2.0.0_Fallback Thu Jan 1 00:06:26 EST 2004 starting... (0,1) link=01 (1,0) link=01 02 nodes initialized. SBLink=00 NC node|link=00 Ram1.00 Ram1.01 Ram2.00 Ram2.01 No memory for this cpu Ram3 Initializing memory: done Ram4 v_esp=000cffe4 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing coreboot to RAM. src=fffe0000 dst=00004000 coreboot_ram.nrv2b length = 0000da24 coreboot_ram.bin length = 00026fac Jumping to coreboot. coreboot-2.0.0_Fallback Thu Jan 1 00:06:26 EST 2004 booting... Enumerating buses... APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.3 siblings=0 CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] enabled PCI: 01:00.0 [1022/7454] enabled PCI: 01:01.0 [1022/7454] enabled next_unitid: 0004 PCI: 01:00.0 [1022/7460] enabled PCI: 01:04.0 [1022/7460] enabled next_unitid: 0008 PCI: pci_scan_bus for bus 01 PCI: 01:01.0 [1022/7454] enabled PCI: 01:02.0 [1022/7455] enabled PCI: 01:04.0 [1022/7460] enabled PCI: 01:05.0 [1022/7468] enabled PCI: 01:05.1 [1022/7469] enabled PCI: 01:05.2 [1022/746a] enabled PCI: 01:05.3 [1022/746b] enabled PCI: 01:05.5 [1022/746d] enabled PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [10de/0326] enabled PCI: pci_scan_bus returning with max=002 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [1022/7464] enabled PCI: 03:00.1 [1022/7464] enabled PCI: 03:03.0 [8086/1076] enabled PCI: 03:05.0 [1095/3114] enabled PCI: 03:0a.0 [1106/3044] enabled PCI: 03:0b.0 [1106/3038] enabled PCI: 03:0b.1 [1106/3038] enabled PCI: 03:0b.2 [1106/3104] enabled PCI: pci_scan_bus returning with max=003 PNP: 002e.0 enabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b enabled PCI: pci_scan_bus returning with max=003 PCI: pci_scan_bus returning with max=003 done Allocating resources... Reading resources... PCI: 01:02.0 1c <- [0x00fffff000 - 0x00ffffefff] size 0x00000000 gran 0x0c bus 02 io PCI: 01:04.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 prefmem Done reading resources. Allocating VGA resource PCI: 02:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 01:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 1b8 <- [0x00e0000000 - 0x00f7ffffff] size 0x18000000 gran 0x14 prefmem <node 0 link 0> PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io <node 0 link 0> PCI: 00:18.0 1b0 <- [0x00fc000000 - 0x00fd2fffff] size 0x01300000 gran 0x14 mem <node 0 link 0> PCI: 01:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:01.0 14 <- [0x00fd200000 - 0x00fd200000] size 0x00000001 gran 0x00 mem PCI: 01:02.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 02 prefmem PCI: 01:02.0 20 <- [0x00fc000000 - 0x00fd0fffff] size 0x01100000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x00fc000000 - 0x00fcffffff] size 0x01000000 gran 0x18 mem PCI: 02:00.0 14 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem PCI: 02:00.0 30 <- [0x00fd000000 - 0x00fd01ffff] size 0x00020000 gran 0x11 romem PCI: 01:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 01:04.0 20 <- [0x00fd100000 - 0x00fd1fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00fd160000 - 0x00fd160fff] size 0x00001000 gran 0x0c mem PCI: 03:00.1 10 <- [0x00fd161000 - 0x00fd161fff] size 0x00001000 gran 0x0c mem PCI: 03:03.0 10 <- [0x00fd100000 - 0x00fd11ffff] size 0x00020000 gran 0x11 mem PCI: 03:03.0 14 <- [0x00fd120000 - 0x00fd13ffff] size 0x00020000 gran 0x11 mem PCI: 03:03.0 18 <- [0x0000001080 - 0x00000010bf] size 0x00000040 gran 0x06 io PCI: 03:03.0 30 <- [0x00fd140000 - 0x00fd15ffff] size 0x00020000 gran 0x11 romem PCI: 03:05.0 10 <- [0x0000001410 - 0x0000001417] size 0x00000008 gran 0x03 io PCI: 03:05.0 14 <- [0x0000001430 - 0x0000001433] size 0x00000004 gran 0x02 io PCI: 03:05.0 18 <- [0x0000001420 - 0x0000001427] size 0x00000008 gran 0x03 io PCI: 03:05.0 1c <- [0x0000001440 - 0x0000001443] size 0x00000004 gran 0x02 io PCI: 03:05.0 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 03:05.0 24 <- [0x00fd163000 - 0x00fd1633ff] size 0x00000400 gran 0x0a mem PCI: 03:05.0 30 <- [0x00fff80000 - 0x00ffffffff] size 0x00080000 gran 0x13 romem PCI: 03:0a.0 10 <- [0x00fd162000 - 0x00fd1627ff] size 0x00000800 gran 0x0b mem PCI: 03:0a.0 14 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io PCI: 03:0b.0 20 <- [0x00000010c0 - 0x00000010df] size 0x00000020 gran 0x05 io PCI: 03:0b.1 20 <- [0x00000010e0 - 0x00000010ff] size 0x00000020 gran 0x05 io PCI: 03:0b.2 10 <- [0x00fd164000 - 0x00fd1640ff] size 0x00000100 gran 0x08 mem PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq PCI: 01:05.1 20 <- [0x0000002860 - 0x000000286f] size 0x00000010 gran 0x04 io PCI: 01:05.2 10 <- [0x0000002840 - 0x000000285f] size 0x00000020 gran 0x05 io PCI: 01:05.3 58 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 01:05.5 10 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 01:05.5 14 <- [0x0000002800 - 0x000000283f] size 0x00000040 gran 0x06 io PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart> Done setting resources. Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 01:01.0 subsystem <- 10f1/2875 PCI: 01:01.0 cmd <- 06 PCI: 01:02.0 bridge ctrl <- 000b PCI: 01:02.0 cmd <- 07 PCI: 02:00.0 cmd <- 03 PCI: 01:04.0 bridge ctrl <- 0003 PCI: 01:04.0 cmd <- 07 PCI: 03:00.0 subsystem <- 10f1/2875 PCI: 03:00.0 cmd <- 02 PCI: 03:00.1 subsystem <- 10f1/2875 PCI: 03:00.1 cmd <- 02 PCI: 03:03.0 cmd <- 03 PCI: 03:05.0 subsystem <- 10f1/2875 PCI: 03:05.0 cmd <- 03 PCI: 03:0a.0 cmd <- 83 PCI: 03:0b.0 cmd <- 01 PCI: 03:0b.1 cmd <- 01 PCI: 03:0b.2 cmd <- 02 PCI: 01:05.0 subsystem <- 10f1/2875 PCI: 01:05.0 cmd <- 0f w83627hf hwm smbus enabled PCI: 01:05.1 subsystem <- 10f1/2875 PCI: 01:05.1 cmd <- 01 PCI: 01:05.2 subsystem <- 10f1/2875 PCI: 01:05.2 cmd <- 01 PCI: 01:05.3 subsystem <- 10f1/2875 PCI: 01:05.3 cmd <- 01 PCI: 01:05.5 subsystem <- 10f1/2875 PCI: 01:05.5 cmd <- 01 PCI: 00:18.1 subsystem <- 10f1/2875 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 10f1/2875 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:19.0 cmd <- 00 PCI: 00:19.1 cmd <- 00 PCI: 00:19.2 cmd <- 00 PCI: 00:19.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor AMD device f5a CPU: family 0f, model 05, stepping 0a Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB Setting variable MTRR 2, base: 3072MB, range: 512MB, type WB DONE variable MTRRs Clear out the extra MTRR's MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent rev id = 0x004a, current patch id = 0x00000000 microcode: patch id to apply = 0x00000047 microcode: updated to patch id = 0x00000047 success CPU model AMD Opteron(tm) Processor 250 Setting up local apic... apic_id: 0x00 done. Clearing memory 2048K - 4194304K: --------------------------------------------------------------- done CPU #0 Initialized CPU 0x01 would not start! CPU 0x01 did not initialize! All AP CPUs stopped PCI: 00:18.0 init PCI: 01:02.0 init PCI: 01:04.0 init PCI: 03:05.0 init rom address for PCI: 03:05.0 = fff80000 Incorrect Expansion ROM Header Signature 457f PCI: 01:05.0 init amd8111: ioapic bsp_apicid = 00 RTC Init Invalid CMOS LB checksum enabling HPET @0xfed00000 PNP: 002e.0 init PNP: 002e.2 init PNP: 002e.5 init Keyboard init... PNP: 002e.b init PCI: 01:05.1 init IDE1 IDE0 PCI: 01:05.3 init set power on after power fail PCI: 00:18.1 init PCI: 00:18.2 init PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.0 init PCI: 00:19.1 init PCI: 00:19.2 init PCI: 00:19.3 init NB: Function 3 Misc Control.. done. PCI: 02:00.0 init rom address for PCI: 02:00.0 = fd000000 copying VGA ROM Image from 0xfd000000 to 0xc0000, 0xf800 bytes entering emulator halt_sys: file /home/doc/tars/core/trunk/coreboot-v2/src/devices/emulator/x86emu/ops.c, line 4387 PCI: 03:03.0 init rom address for PCI: 03:03.0 = fd140000 Incorrect Expansion ROM Header Signature ffff PCI: 03:0a.0 init PCI: 03:0b.0 init PCI: 03:0b.1 init PCI: 03:0b.2 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...done Checking IRQ routing table consistency... check_pirq_routing_table() - irq_routing_table located at: 0x000f0000 /home/doc/tars/core/trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c: 37:check_pirq_routing_table() - checksum is: 0xcf but should be: 0xd0 done. bus_isa=4 bus_8151_1=2 Wrote the mp table end at: 00000020 - 000001f0 Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000e38 checksum 917c elfboot: Attempting to load payload. rom_stream: 0xfffc0000 - 0xfffdffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 New segment addr 0x100000 size 0x39d270 offset 0xe0 filesize 0x159c0 (cleaned up) New segment addr 0x100000 size 0x39d270 offset 0xe0 filesize 0x159c0 New segment addr 0x49d280 size 0x48 offset 0x15aa0 filesize 0x48 (cleaned up) New segment addr 0x49d280 size 0x48 offset 0x15aa0 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000039d270 filesz: 0x00000000000159c0 Clearing Segment: addr: 0x00000000001159c0 memsz: 0x00000000003878b0 Loading Segment: addr: 0x000000000049d280 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x100080 FILO version 0.6.0rc1 (doc@darkstar) Thu Jan 1 00:03:58 EST 2004 ERROR: No such CMOS option (boot_devices) Press <Enter> for default menu.lst (hda1:/boot/grub/menu.lst), or <Esc> for prompt... 1 timed out menu: hda1:/boot/grub/menu.lst

2 2

[PATCH] Athlon64 K8 fixes
by Robert Millan Dec. 1, 2008

Dec. 1, 2008

Hi, My Athlon64 / K8 socket 939 setup needed the following adjustments to fix memory read/write errors. Thanks to Rudolf for hinting on which bits I should check for. Details: - bit 9, mandated by spec to always be set on sodimm or socket 939 dual dimm. - bit 28, enable 2T timing. no idea why, but I get memory errors without it. - bit 29, upper chip select. mandated by spec on socket 939. My patch also adds missing descriptions, based on the ones from the spec (http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/260…) -- Robert Millan The DRM opt-in fallacy: "Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all."

5 8

[PATCH] superiotool: dump winbond hardware monitor registers
by Stefan Reinauer Dec. 1, 2008

Dec. 1, 2008

See patch. The Winbond SuperIO chips have another indirection of registers. The hwmon has generic registers and banked registers, mostly temperature handling, and SMI/GPIO stuff. Regards, Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 * Not all LDNs are switched via register offset 0x07, make it a parameter * add support for dumping the hardware monitor of Winbond W83627THF/THG parts with -e Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: fintek.c =================================================================== --- fintek.c (revision 3779) +++ fintek.c (working copy) @@ -137,7 +137,7 @@ get_superio_name(reg_table, did), vid, did, port); chip_found = 1; - dump_superio("Fintek", reg_table, port, did); + dump_superio("Fintek", reg_table, port, did, LDN_SEL); exit_conf_mode_winbond_fintek_ite_8787(port); } Index: winbond.c =================================================================== --- winbond.c (revision 3779) +++ winbond.c (working copy) @@ -468,6 +468,51 @@ {EOT} }; +static const struct superio_registers hwm_table[] = { + {0x828, "W83627THF/THG", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09, + 0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13, + 0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d, + 0x1e,0x1f, + 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29, + 0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34, + 0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e, + 0x3f, + 0x40,0x41,0x42,0x43,0x44,0x47,0x48,0x49,0x4a,0x4b, + 0x4c,0x4d,0x4e,0x4f,EOT}, + {RSVD,0xff,RSVD,0xff,0x00,0x00,0x00,0x00,0x01,0x01, + 0x01,0x01,0x3c,0x3c,0x0a,0x0a,RSVD,0xff,0x00,0x00, + 0x00,0x01,0x01,0x3c,0x43,RSVD,0xff,0xff,RSVD,RSVD, + NANA,NANA, + NANA,NANA,NANA,NANA,NANA,RSVD,RSVD,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + RSVD,RSVD,RSVD,RSVD,NANA,NANA,NANA,NANA,NANA,RSVD, + RSVD, + 0x03,0x00,0x00,0xfe,0xff,0x5f,NANA,0x03,RSVD,0x44, + 0x18,0x15,0x80,0x5c,EOT}}, + {0x0, "BANK 0", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59, + 0x5d,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,0x00,0x80,0x90,0x70, + 0x00,EOT}}, + {0x1, "BANK 1", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x2, "BANK 2", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,EOT}, + {NANA,NANA,0x00,0x4b,0x00,0x50,0x00,EOT}}, + {0x4, "BANK 4", + {0x50,0x51,0x53,0x54,0x55,0x56,0x59,0x5a,0x5b,EOT}, + {0x00,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "BANK 5", + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, + {EOT} +}; + + static void enter_conf_mode_winbond_88(uint16_t port) { OUTB(0x88, port); @@ -486,7 +531,7 @@ static void probe_idregs_winbond_helper(const char *init, uint16_t port) { - uint16_t id; + uint16_t id, hwmport; uint8_t devid, rev, olddevid; probing_for("Winbond", init, port); @@ -522,7 +567,28 @@ get_superio_name(reg_table, id), devid, rev, port); chip_found = 1; - dump_superio("Winbond", reg_table, port, id); + dump_superio("Winbond", reg_table, port, id, LDN_SEL); + + if (extra_dump) { + regwrite(port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */ + + if ((regval(port, 0x30) & (1 << 0)) != (1 << 0)) { + printf("Hardware Monitor disabled or does not exist.\n"); + return; + } + + /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */ + hwmport = regval(port, 0x60) << 8; + hwmport |= regval(port, 0x61); + + /* HWM address register = HWM base address + 5. */ + hwmport += 5; + + printf("Hardware Monitor (0x%04x)\n", hwmport); + dump_superio("Winbond-HWM", hwm_table, hwmport, id, + WINBOND_HWM_SEL); + } + } void probe_idregs_winbond(uint16_t port) Index: ite.c =================================================================== --- ite.c (revision 3779) +++ ite.c (working copy) @@ -534,7 +534,7 @@ get_superio_name(reg_table, id), id, chipver, port); chip_found = 1; - dump_superio("ITE", reg_table, port, id); + dump_superio("ITE", reg_table, port, id, LDN_SEL); if (extra_dump) { regwrite(port, 0x07, 0x04); /* Select LDN 4 (EC). */ @@ -547,7 +547,7 @@ ecport += 5; printf("Environment controller (0x%04x)\n", ecport); - dump_superio("ITE-EC", ec_table, ecport, id); + dump_superio("ITE-EC", ec_table, ecport, id, LDN_SEL); } } Index: nsc.c =================================================================== --- nsc.c (revision 3779) +++ nsc.c (working copy) @@ -506,7 +506,7 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; - dump_superio("NSC", reg_table, port, id); + dump_superio("NSC", reg_table, port, id, LDN_SEL); } void print_nsc_chips(void) Index: superiotool.c =================================================================== --- superiotool.c (revision 3779) +++ superiotool.c (working copy) @@ -82,7 +82,7 @@ } static void dump_regs(const struct superio_registers reg_table[], - int i, int j, uint16_t port) + int i, int j, uint16_t port, uint8_t bank_sel) { int k; const int16_t *idx; @@ -91,7 +91,7 @@ printf("LDN 0x%02x", reg_table[i].ldn[j].ldn); if (reg_table[i].ldn[j].name != NULL) printf(" (%s)", reg_table[i].ldn[j].name); - regwrite(port, 0x07, reg_table[i].ldn[j].ldn); + regwrite(port, bank_sel, reg_table[i].ldn[j].ldn); } else { printf("Register dump:"); } @@ -131,7 +131,7 @@ void dump_superio(const char *vendor, const struct superio_registers reg_table[], - uint16_t port, uint16_t id) + uint16_t port, uint16_t id, uint8_t bank_sel) { int i, j, no_dump_available = 1; @@ -149,7 +149,7 @@ if (reg_table[i].ldn[j].ldn == EOT) break; no_dump_available = 0; - dump_regs(reg_table, i, j, port); + dump_regs(reg_table, i, j, port, bank_sel); } if (no_dump_available) Index: ali.c =================================================================== --- ali.c (revision 3779) +++ ali.c (working copy) @@ -95,7 +95,7 @@ get_superio_name(reg_table, id), id, rev, port); chip_found = 1; - dump_superio("ALi", reg_table, port, id); + dump_superio("ALi", reg_table, port, id, LDN_SEL); exit_conf_mode_ali(port); } Index: smsc.c =================================================================== --- smsc.c (revision 3779) +++ smsc.c (working copy) @@ -643,7 +643,7 @@ id, rev, port); chip_found = 1; - dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id); + dump_superio((id == 0x77 ? "ASUS" : "SMSC"), reg_table, port, id, LDN_SEL); exit_conf_mode_smsc(port); } Index: superiotool.h =================================================================== --- superiotool.h (revision 3779) +++ superiotool.h (working copy) @@ -73,10 +73,14 @@ #define MISC -5 /* Needs special comment in output */ #define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ -#define MAXNUMIDX 170 /* Maximum number of indexes */ +#define MAXNUMIDX 170 /* Maximum number of indices */ #define IDXSIZE (MAXNUMIDX + 1) #define MAXNUMPORTS (6 + 1) /* Maximum number of Super I/O ports */ +/* select registers for various components */ +#define LDN_SEL 0x07 /* LDN select register */ +#define WINBOND_HWM_SEL 0x4e /* Hardware Monitor Bank Select */ + /* Command line parameters. */ extern int dump, verbose, extra_dump; @@ -102,7 +106,7 @@ const char *get_superio_name(const struct superio_registers reg_table[], uint16_t id); void dump_superio(const char *name, const struct superio_registers reg_table[], - uint16_t port, uint16_t id); + uint16_t port, uint16_t id, uint8_t bank_sel); void probing_for(const char *vendor, const char *info, uint16_t port); void print_vendor_chips(const char *vendor, const struct superio_registers reg_table[]);

2 2

[RFC] flashrom: sector-based flashing
by Carl-Daniel Hailfinger Dec. 1, 2008

Dec. 1, 2008

Hi, flashrom hasn't seen any major design changes in the last few months and most chips still perform whole-chip erase instead of sector-based erase. I'd like to introduce a function which takes a range and rounds the start and the end of the range to the nearest block boundary. void roundup(struct flashchip *flash, int *startpos, int *endpos); Take an example 256 kByte flash chip with the following sector layout: 0x00000-0x0ffff 64kB block 0x10000-0x1ffff 64kB block 0x20000-0x2ffff 64kB block 0x30000-0x37fff 32kB block 0x38000-0x3bfff 16kB block 0x3c000-0x3dfff 8kB block 0x3e000-0x3efff 4kB block 0x3f000-0x3ffff 4kB block startpos=0x38123; endpos=0x3e005; roundup(flash, &startpos, &endpos); //results follow: //startpos=0x38000; //endpos=0x3efff; That way, it is easily possible to check whether a given range can be handled by sector-based erase and write. You can use that result to tell the user that a range outside the intended range will get flashed. It is also possible to refuse flashing in that case. Since the function will be generic and take a struct flashchip, there's no need to store a pointer to it with each chip and you can call the generic one from anywhere. What do you think? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [coreboot] r3783 - in trunk/coreboot-v2: src/config util/options
by Carl-Daniel Hailfinger Nov. 30, 2008

Nov. 30, 2008

On 30.11.2008 15:52, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-11-30 15:52:46 +0100 (Sun, 30 Nov 2008) > New Revision: 3783 > > Modified: > trunk/coreboot-v2/src/config/Config.lb > trunk/coreboot-v2/util/options/build_opt_tbl.c > Log: > ok, another attempt to the build_opt_tbl problem: > - create temp files and move them afterwards > - remove dummy option -b > - fix usage > - drop implicit creation of .c file if no --option is specified. > > Now let's see if this fixes the issue. :-) We don't want to take 24s > instead of 6s to build an image reliably (Yes, yes, I know Tiano takes > over 20 minutes) > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > Awesome, thanks! Although this is already committed, I want to ack it retroactively. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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