coreboot January 2008

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[PATCH] superiotool: Fix Winbond W83627EHF support
by Uwe Hermann 19 Jan '08

19 Jan '08

See patch. Tested on actual hardware. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r3064 - trunk/util/superiotool
by svn＠coreboot.org 19 Jan '08

19 Jan '08

Author: uwe Date: 2008-01-19 10:43:48 +0100 (Sat, 19 Jan 2008) New Revision: 3064 Modified: trunk/util/superiotool/README Log: Add Bingxun Shi <bingxunshi(a)gmail.com> to the list of contributors (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/README =================================================================== --- trunk/util/superiotool/README 2008-01-19 09:40:17 UTC (rev 3063) +++ trunk/util/superiotool/README 2008-01-19 09:43:48 UTC (rev 3064) @@ -88,6 +88,7 @@ Contributors ------------ +Bingxun Shi <bingxunshi(a)gmail.com> Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> David Hendricks <david.hendricks(a)gmail.com> Frieder Ferlemann <Frieder.Ferlemann(a)web.de>

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r3063 - trunk/util/superiotool
by svn＠coreboot.org 19 Jan '08

19 Jan '08

Author: uwe Date: 2008-01-19 10:40:17 +0100 (Sat, 19 Jan 2008) New Revision: 3063 Modified: trunk/util/superiotool/winbond.c Log: Small superiotool fix to detect more Winbond W83627EHF chips. The patch is tested on actual hardware. As per datasheet the ID should be 0x886? for those chips. Not mentioned in the datasheet, but sensors-detect says 0x8853 is also possible. Also, the ASUS A8V-E Deluxe (W83627EHF) has an ID of 0x8854 (verified on actual hardware). So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/superiotool/winbond.c =================================================================== --- trunk/util/superiotool/winbond.c 2008-01-19 00:32:07 UTC (rev 3062) +++ trunk/util/superiotool/winbond.c 2008-01-19 09:40:17 UTC (rev 3063) @@ -195,54 +195,6 @@ {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00, EOT}}, {EOT}}}, - {0x886, "W83627EHF/EF/EHG/EG", { /* sensors-detect: 0x8853 possible */ - {NOLDN, NULL, - {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, - 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, - {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50, - 0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}}, - {0x0, "Floppy", - {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, - 0xf5,EOT}, - {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, - 0x00,EOT}}, - {0x1, "Parallel port", - {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, - {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, - {0x2, "COM1", - {0x30,0x60,0x61,0x70,0xf0,EOT}, - {0x01,0x03,0xf8,0x04,0x00,EOT}}, - {0x3, "COM2", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, - {0x5, "Keyboard", - {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, - {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}}, - {0x6, "Serial flash interface", - {0x30,0x62,0x63,EOT}, - {0x00,0x00,0x00,EOT}}, - {0x7, "GPIO 1, GPIO 6, game port, MIDI port", - {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3, - 0xf4,0xf5,0xf6,0xf7,EOT}, - {0x00,0x02,0x01,0x03,0x30,0x09,0xff,0x00,0x00,0x00, - 0xff,0x00,0x00,0x00,EOT}}, - {0x8, "WDTO#, PLED", - {0x30,0xf5,0xf6,0xf7,EOT}, - {0x00,0x00,0x00,0x00,EOT}}, - {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED", - {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xf0,0xf1,0xf2, - 0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, - {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00, - 0x00,0xff,0x00,0x00,0x00,EOT}}, - {0xa, "ACPI", - {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, - 0xe8,0xf2,0xf3,0xf4,0xf6,0xf7,EOT}, - {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x00,0x00, - RSVD,0x7c,0x00,0x00,0x00,0x00,EOT}}, - {0xb, "Hardware monitor", - {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, - {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}}, - {EOT}}}, {0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */ {EOT}}}, @@ -412,6 +364,61 @@ {0x30,0x60,0x61,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0xff,0x00,0x00,EOT}}, {EOT}}}, + {0x88, "W83627EHF/EF/EHG/EG", { + /* + * As per datasheet the ID should be 0x886? here. + * Not mentioned in the datasheet, but sensors-detect says + * 0x8853 is also possible. Also, the ASUS A8V-E Deluxe + * (W83627EHF) has an ID of 0x8854 (verified on hardware). + * So we now assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG. + */ + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50, + 0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x2, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x3, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}}, + {0x6, "Serial flash interface", + {0x30,0x62,0x63,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x7, "GPIO 1, GPIO 6, game port, MIDI port", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3, + 0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0x02,0x01,0x03,0x30,0x09,0xff,0x00,0x00,0x00, + 0xff,0x00,0x00,0x00,EOT}}, + {0x8, "WDTO#, PLED", + {0x30,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xf0,0xf1,0xf2, + 0xf3,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00, + 0x00,0xff,0x00,0x00,0x00,EOT}}, + {0xa, "ACPI", + {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xf2,0xf3,0xf4,0xf6,0xf7,EOT}, + {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x00,0x00, + RSVD,0x7c,0x00,0x00,0x00,0x00,EOT}}, + {0xb, "Hardware monitor", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}}, + {EOT}}}, /* ID[3..0] */ {0xa, "W83877F", { @@ -450,7 +457,7 @@ rev = regval(port, DEVICE_REV_REG); olddevid = regval(port, DEVICE_ID_REG_OLD) & 0x0f; - if (devid == 0x52 || devid == 0x68) + if (devid == 0x52 || devid == 0x68 || devid == 0x88) id = devid; /* ID only */ else if ((devid == 0x97) && ((rev & 0xf0) == 0x70)) id = (devid << 8) | rev; /* ID and rev */

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r557 - in coreboot-v3: device include/device util/dtc
by svn＠coreboot.org 19 Jan '08

19 Jan '08

Author: rminnich Date: 2008-01-19 07:29:14 +0100 (Sat, 19 Jan 2008) New Revision: 557 Modified: coreboot-v3/device/device.c coreboot-v3/include/device/device.h coreboot-v3/include/device/pci.h coreboot-v3/util/dtc/flattree.c Log: include/device/device.h: Change the ID constants so they are more useful for debugging. Instead of simple 1,2,3 they now are a 4-byte value which can be more useful when looking at memory with a debugger. Lots of variables can be '1', but fewer variables will match to 'PCID'. include/device/pci.h: Include pci_ids.h in pci.h device/device.c: remove silly comment. Change memcpy to struct assign, this makes it possible for the C compiler to do type checking. Add assign for the dev->id. flattree.c: Support the use of 'domainid' and 'pciid' in the per-chip dts. These IDs will be assigned to the static tree device struct. In conjunction with the earlier patch, this change removes the need for users to assign the ops struct member in the dts by hand, as it is done in the qemu port today. The ops struct member will automatically be assigned by the dev_init function, which is run in stage2 before any actual device code is run. (This change to dev_init was in the previous patch). Added two comments that document what is going on. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/device/device.c =================================================================== --- coreboot-v3/device/device.c 2008-01-17 16:32:12 UTC (rev 556) +++ coreboot-v3/device/device.c 2008-01-19 06:29:14 UTC (rev 557) @@ -209,11 +209,12 @@ } dev = new_device(); - if (!dev) /* Please don't do this at home */ + if (!dev) goto out; memset(dev, 0, sizeof(*dev)); - memcpy(&dev->path, path, sizeof(*path)); + dev->path = *path; + dev->id = *devid; /* Initialize the back pointers in the link fields. */ for (link = 0; link < MAX_LINKS; link++) { Modified: coreboot-v3/include/device/device.h =================================================================== --- coreboot-v3/include/device/device.h 2008-01-17 16:32:12 UTC (rev 556) +++ coreboot-v3/include/device/device.h 2008-01-19 06:29:14 UTC (rev 557) @@ -25,18 +25,28 @@ #include <device/resource.h> #include <device/path.h> +/** + * Create a 32-bit value from four characters. This is better + * than the usual enum values when using (JTAG) debuggers. + * It also makes it harder for accidentally assigned type values + * to be mistaken for a real value -- e.g. it is more likely in the event + * of a programming error that a '1' is somehow assigned + * to the type field, whereas these values are more complex. + * Thus errors may be easier to find. + */ +#define TYPENAME(a,b,c,d) ((a<<24)|(b<<16)|(c<<8)|(d)) #define DEVICE_ID_MAX 64 enum device_id_type { - DEVICE_ID_NONE = 0, - DEVICE_ID_ROOT, - DEVICE_ID_PCI, - DEVICE_ID_PNP, - DEVICE_ID_I2C, - DEVICE_ID_APIC, - DEVICE_ID_PCI_DOMAIN, - DEVICE_ID_APIC_CLUSTER, - DEVICE_ID_CPU, - DEVICE_ID_CPU_BUS, + DEVICE_ID_NONE = 0, + DEVICE_ID_ROOT = TYPENAME('R','O','O','T'), + DEVICE_ID_PCI = TYPENAME(' ','P','C','I'), + DEVICE_ID_PNP = TYPENAME(' ','P','N','P'), + DEVICE_ID_I2C = TYPENAME(' ','I','2','C'), + DEVICE_ID_APIC = TYPENAME('A','P','I','C'), + DEVICE_ID_PCI_DOMAIN = TYPENAME('P','C','I','D'), + DEVICE_ID_APIC_CLUSTER = TYPENAME('A','P','C','C'), + DEVICE_ID_CPU = TYPENAME(' ','C','P','U'), + DEVICE_ID_CPU_BUS = TYPENAME(' ','B','U','S'), }; struct device; Modified: coreboot-v3/include/device/pci.h =================================================================== --- coreboot-v3/include/device/pci.h 2008-01-17 16:32:12 UTC (rev 556) +++ coreboot-v3/include/device/pci.h 2008-01-19 06:29:14 UTC (rev 557) @@ -29,6 +29,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <device/pci_rom.h> +#include <device/pci_ids.h> /* * For more information, please consult the following manuals (look at Modified: coreboot-v3/util/dtc/flattree.c =================================================================== --- coreboot-v3/util/dtc/flattree.c 2008-01-17 16:32:12 UTC (rev 556) +++ coreboot-v3/util/dtc/flattree.c 2008-01-19 06:29:14 UTC (rev 557) @@ -532,7 +532,33 @@ if (tree->config){ configname = clean(tree->label, 0); printf("\t.device_configuration = &%s,\n", configname); + /* The config property list for a device is derived from the + * device dts, e.g. northbridge/intel/i440bx/dts, not the + * mainboard dts. + * Almost all of these properties are specific to the device. + * Some, such as the device id, are part of the common + * device struct. Check the config properties and + * pull out those properties that are for the common + * (a.k.a. generic) device struct. + */ + /* get the properties out that are generic device props */ + for_each_config(tree, prop) { + if (streq(prop->name, "domainid")){ + fprintf(f, "\t.id = {.type=DEVICE_ID_PCI_DOMAIN,.u={.pci_domain={ %s }}},\n", + prop->val.val); + } + if (streq(prop->name, "pciid")){ + fprintf(f, "\t.id = {.type=DEVICE_ID_PCI,.u={.pci={ %s }}},\n", + prop->val.val); + } + } } + /* Process the properties specified in the mainboard dts. + * Some of these properties require special initialization + * (e.g. the path); some are flags, i.e. if the property exists + * then a variable is set to 1 (e.g. on_mainboard); + * and some are just set directly into the code (e.g. ops_pci). + */ for_each_property(tree, prop) { if (streq(prop->name, "pcidomain")){ fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = %s }}},\n",

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r3062 build service
by coreboot information 19 Jan '08

19 Jan '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3062 to the coreboot source repository and caused the following changes: Change Log: This patch is for winbond w83627DHG superio support in superiotool. I have test that on my board, it works ;) Signed-off-by: Bingxun Shi <bingxunshi(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3062&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r3061 build service
by coreboot information 19 Jan '08

19 Jan '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3061 to the coreboot source repository and caused the following changes: Change Log: Support SPI flash chips bigger than 512 kByte sitting behind IT8716F Super I/O performing LPC-to-SPI flash translation. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3061&device=serengeti_che… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r3062 - trunk/util/superiotool
by svn＠coreboot.org 19 Jan '08

19 Jan '08

Author: hailfinger Date: 2008-01-19 01:32:07 +0100 (Sat, 19 Jan 2008) New Revision: 3062 Modified: trunk/util/superiotool/winbond.c Log: This patch is for winbond w83627DHG superio support in superiotool. I have test that on my board, it works ;) Signed-off-by: Bingxun Shi <bingxunshi(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/superiotool/winbond.c =================================================================== --- trunk/util/superiotool/winbond.c 2008-01-19 00:04:46 UTC (rev 3061) +++ trunk/util/superiotool/winbond.c 2008-01-19 00:32:07 UTC (rev 3062) @@ -143,6 +143,57 @@ {EOT}}}, #endif {0xa02, "W83627DHG", { + {NOLDN, NULL, + {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, + 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,0xa0,NANA,0xff,0x00,MISC,0x00,MISC,RSVD,0x50, + 0x00,0x00,RSVD,0xe2,0x21,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5, + EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00, + EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}}, + {0x2, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x3, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}}, + {0x6, "Serial peripheral interface", + {0x30,0x62,0x63,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x7, "GPIO 6", + {0x30,0xf4,0xf5,0xf6,0xf7,EOT}, + {0x00,0xff,0x00,0x00,0x00,EOT}}, + {0x8, "WDTO#, PLED", + {0x30,0xf5,0xf6,0xf7,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5", + {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8, + 0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xfe, + EOT}, + {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00, + 0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00, + EOT}}, + {0xa, "ACPI", + {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, + 0xe8,0xe9,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT}, + {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x1c,0x00, + RSVD,RSVD,0x7c,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xb, "Hardware monitor", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x00,0x00,0x81,0x00,0x00,EOT}}, + {0xc, "PECI, SST", + {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe8,0xf1,0xfe,0xff, + EOT}, + {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00, + EOT}}, {EOT}}}, {0x886, "W83627EHF/EF/EHG/EG", { /* sensors-detect: 0x8853 possible */ {NOLDN, NULL,

1 0

r3061 - trunk/util/flashrom
by svn＠coreboot.org 19 Jan '08

19 Jan '08

Author: hailfinger Date: 2008-01-19 01:04:46 +0100 (Sat, 19 Jan 2008) New Revision: 3061 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: Support SPI flash chips bigger than 512 kByte sitting behind IT8716F Super I/O performing LPC-to-SPI flash translation. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2008-01-18 18:04:28 UTC (rev 3060) +++ trunk/util/flashrom/flash.h 2008-01-19 00:04:46 UTC (rev 3061) @@ -234,7 +234,16 @@ #define TI_ID 0x97 /* Texas Instruments */ +/* + * W25X chips are SPI, first byte of device ID is memory type, second + * byte of device ID is related to log(bitsize). + */ #define WINBOND_ID 0xDA /* Winbond */ +#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flash devices */ +#define W_25X10 0x3011 +#define W_25X20 0x3012 +#define W_25X40 0x3013 +#define W_25X80 0x3014 #define W_29C011 0xC1 #define W_29C020C 0x45 #define W_29C040P 0x46 @@ -297,6 +306,7 @@ void generic_spi_write_disable(); int generic_spi_chip_erase_c7(struct flashchip *flash); int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf); +int generic_spi_chip_read(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-01-18 18:04:28 UTC (rev 3060) +++ trunk/util/flashrom/flashchips.c 2008-01-19 00:04:46 UTC (rev 3061) @@ -51,13 +51,13 @@ {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"MX25L8005", MX_ID, MX_25L8005, 1024, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, @@ -122,6 +122,14 @@ probe_jedec, erase_chip_jedec, write_39sf020}, {"W39V080A", WINBOND_ID, W_39V080A, 1024, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020}, + {"W25x10", WINBOND_NEX_ID, W_25X10, 128, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"W25x20", WINBOND_NEX_ID, W_25X20, 256, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"W25x40", WINBOND_NEX_ID, W_25X40, 512, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"W25x80", WINBOND_NEX_ID, W_25X80, 1024, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M29F002B", ST_ID, ST_M29F002B, 256, 64 * 1024, probe_jedec, erase_chip_jedec, write_jedec}, {"M50FW040", ST_ID, ST_M50FW040, 512, 64 * 1024, @@ -151,23 +159,23 @@ {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, {"M25P05-A", ST_ID, ST_M25P05A, 64, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P10-A", ST_ID, ST_M25P10A, 128, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P20", ST_ID, ST_M25P20, 256, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P40", ST_ID, ST_M25P40, 512, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P80", ST_ID, ST_M25P80, 1024, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P16", ST_ID, ST_M25P16, 2048, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P32", ST_ID, ST_M25P32, 4096, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P64", ST_ID, ST_M25P64, 8192, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"M25P128", ST_ID, ST_M25P128, 16384, 256, - probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"82802ab", 137, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"82802ac", 137, 172, 1024, 64 * 1024, Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-01-18 18:04:28 UTC (rev 3060) +++ trunk/util/flashrom/spi.c 2008-01-19 00:04:46 UTC (rev 3061) @@ -1,7 +1,8 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger + * Copyright (C) 2008 Ronald Hoogenboom <ronald(a)zonnet.nl> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,9 +77,27 @@ #define JEDEC_RDSR_INSIZE 0x01 #define JEDEC_RDSR_BIT_WIP (0x01 << 0) +/* Write Status Register */ +#define JEDEC_WRSR 0x01 +#define JEDEC_WRSR_OUTSIZE 0x02 +#define JEDEC_WRSR_INSIZE 0x00 + +/* Read the memory */ +#define JEDEC_READ 0x03 +#define JEDEC_READ_OUTSIZE 0x04 +/* JEDEC_READ_INSIZE : any length */ + +/* Write memory byte */ +#define JEDEC_BYTE_PROGRAM 0x02 +#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 +#define JEDEC_BYTE_PROGRAM_INSIZE 0x00 + uint16_t it8716f_flashport = 0; +/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ +int fast_spi=1; -void generic_spi_prettyprint_status_register(struct flashchip *flash); +void spi_prettyprint_status_register(struct flashchip *flash); +void spi_disable_blockprotect(void); /* Generic Super I/O helper functions */ uint8_t regval(uint16_t port, uint8_t reg) @@ -203,10 +222,11 @@ __FUNCTION__, writecnt); return 1; } - /* Start IO, 33MHz, readcnt input bytes, writecnt output bytes. Note: + /* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes. + * Note: * We can't use writecnt directly, but have to use a strange encoding. */ - outb((0x5 << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); + outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); do { busy = inb(port) & 0x80; } while (busy); @@ -242,7 +262,6 @@ /* Send WREN (Write Enable) */ generic_spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL); - } void generic_spi_write_disable() @@ -267,7 +286,7 @@ /* Print the status register to tell the * user about possible write protection. */ - generic_spi_prettyprint_status_register(flash); + spi_prettyprint_status_register(flash); return 1; } @@ -290,32 +309,62 @@ return readarr[0]; } -/* Prettyprint the status register. Works for - * ST M25P series - * MX MX25L series +/* Prettyprint the status register. Common definitions. */ -void generic_spi_prettyprint_status_register_st_m25p(uint8_t status) +void spi_prettyprint_status_register_common(uint8_t status) { - printf_debug("Chip status register: Status Register Write Disable " - "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); - printf_debug("Chip status register: Bit 6 is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - printf_debug("Chip status register: Bit 5 is " + printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is " "%sset\n", (status & (1 << 5)) ? "" : "not "); - printf_debug("Chip status register: Block Protect 2 (BP2) is " + printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is " "%sset\n", (status & (1 << 4)) ? "" : "not "); - printf_debug("Chip status register: Block Protect 1 (BP1) is " + printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is " "%sset\n", (status & (1 << 3)) ? "" : "not "); - printf_debug("Chip status register: Block Protect 0 (BP0) is " + printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is " "%sset\n", (status & (1 << 2)) ? "" : "not "); printf_debug("Chip status register: Write Enable Latch (WEL) is " "%sset\n", (status & (1 << 1)) ? "" : "not "); - printf_debug("Chip status register: Write In Progress (WIP) is " + printf_debug("Chip status register: Write In Progress (WIP/BUSY) is " "%sset\n", (status & (1 << 0)) ? "" : "not "); } -void generic_spi_prettyprint_status_register(struct flashchip *flash) +/* Prettyprint the status register. Works for + * ST M25P series + * MX MX25L series + */ +void spi_prettyprint_status_register_st_m25p(uint8_t status) { + printf_debug("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + printf_debug("Chip status register: Bit 6 is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_common(status); +} + +/* Prettyprint the status register. Works for + * SST 25VF016 + */ +void spi_prettyprint_status_register_sst25vf016(uint8_t status) +{ + const char *bpt[]={ + "none", + "1F0000H-1FFFFFH", + "1E0000H-1FFFFFH", + "1C0000H-1FFFFFH", + "180000H-1FFFFFH", + "100000H-1FFFFFH", + "all","all" + }; + printf_debug("Chip status register: Block Protect Write Disable " + "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); + printf_debug("Chip status register: Auto Address Increment Programming " + "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_common(status); + printf_debug("Resulting block protection : %s\n", + bpt[(status & 0x1c) >> 2]); +} + +void spi_prettyprint_status_register(struct flashchip *flash) +{ uint8_t status; status = generic_spi_read_status_register(); @@ -324,8 +373,12 @@ case ST_ID: case MX_ID: if ((flash->model_id & 0xff00) == 0x2000) - generic_spi_prettyprint_status_register_st_m25p(status); + spi_prettyprint_status_register_st_m25p(status); break; + case SST_ID: + if (flash->model_id == SST_25VF016B) + spi_prettyprint_status_register_sst25vf016(status); + break; } } @@ -333,6 +386,7 @@ { const unsigned char cmd[] = JEDEC_CE_C7; + spi_disable_blockprotect(); generic_spi_write_enable(); /* Send CE (Chip Erase) */ generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); @@ -392,7 +446,7 @@ generic_spi_write_enable(); outb(0x06 , it8716f_flashport + 1); - outb((3 << 4), it8716f_flashport); + outb(((2+(fast_spi?1:0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } @@ -410,11 +464,113 @@ it8716f_spi_page_program(block, buf, bios); } +/* + * This is according the SST25VF016 datasheet, who knows it is more + * generic that this... + */ +void spi_write_status_register(int status) +{ + const unsigned char cmd[] = {JEDEC_WRSR, (unsigned char)status}; + + /* Send WRSR (Write Status Register) */ + generic_spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL); +} + +void spi_byte_program(int address, uint8_t byte) +{ + const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM, + (address>>16)&0xff, + (address>>8)&0xff, + (address>>0)&0xff, + byte + }; + + /* Send Byte-Program */ + generic_spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL); +} + +void spi_disable_blockprotect(void) +{ + uint8_t status; + + status = generic_spi_read_status_register(); + /* If there is block protection in effect, unprotect it first. */ + if ((status & 0x3c) != 0) { + printf_debug("Some block protection in effect, disabling\n"); + generic_spi_write_enable(); + spi_write_status_register(status & ~0x3c); + } +} + +/* + * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles + * Program chip using firmware cycle byte programming. (SLOW!) + */ +int it8716f_over512k_spi_chip_write(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + fast_spi=0; + + spi_disable_blockprotect(); + for (i=0; i<total_size; i++) { + generic_spi_write_enable(); + spi_byte_program(i,buf[i]); + /* FIXME: We really should read the status register and delay + * accordingly. + */ + //while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + myusec_delay(10); + //if (i%1024==0) fputc('b',stderr); + } + /* resume normal ops... */ + outb(0x20, it8716f_flashport); + return 0; +} + +void spi_3byte_read(int address, uint8_t *bytes, int len) +{ + const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ, + (address>>16)&0xff, + (address>>8)&0xff, + (address>>0)&0xff, + }; + + /* Send Read */ + generic_spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes); +} + +/* + * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles + * Need to read this big flash using firmware cycles 3 byte at a time. + */ +int generic_spi_chip_read(struct flashchip *flash, uint8_t *buf) +{ + int total_size = 1024 * flash->total_size; + int i; + fast_spi=0; + + if (total_size > 512 * 1024) { + for (i = 0; i < total_size; i+=3) { + int toread=3; + if (total_size-i < toread) toread=total_size-i; + spi_3byte_read(i, buf+i, toread); + } + } else { + memcpy(buf, (const char *)flash->virtual_memory, total_size); + } + return 0; +} + int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; int i; - for (i = 0; i < total_size / 256; i++) { - generic_spi_page_program(i, buf, (uint8_t *)flash->virtual_memory); + if (total_size > 512 * 1024) { + it8716f_over512k_spi_chip_write(flash, buf); + } else { + for (i = 0; i < total_size / 256; i++) { + generic_spi_page_program(i, buf, (uint8_t *)flash->virtual_memory); + } } return 0; }

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Re: [coreboot] r3055 - trunk/util/lxbios
by Carl-Daniel Hailfinger 19 Jan '08

19 Jan '08

On 18.01.2008 16:33, svn(a)coreboot.org wrote: > Author: stepan > Date: 2008-01-18 16:33:49 +0100 (Fri, 18 Jan 2008) > New Revision: 3055 > > Modified: > trunk/util/lxbios/ChangeLog > trunk/util/lxbios/DISCLAIMER > trunk/util/lxbios/README > [...] > Log: > rename linuxbios -> coreboot > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> > [...] > Modified: trunk/util/lxbios/reg_expr.h > =================================================================== > --- trunk/util/lxbios/reg_expr.h 2008-01-18 15:33:10 UTC (rev 3054) > +++ trunk/util/lxbios/reg_expr.h 2008-01-18 15:33:49 UTC (rev 3055) > @@ -8,8 +8,8 @@ > * UCRL-CODE-2003-012 > * All rights reserved. > * > - * This file is part of lxbios, a utility for reading/writing LinuxBIOS > - * parameters and displaying information from the LinuxBIOS table. > + * This file is part of lxbios, a utility for reading/writing coreboot > + * parameters and displaying information from the coreboot table. > * For details, see <http://www.llnl.gov/linux/lxbios/>. > * > * Please also read the file DISCLAIMER which is included in this software > The URL mentioned above (and in lots of other files in lxbios) gives me a 404 not found. And while we're doing an unconditional "s/linuxbios/coreboot/" everywhere, it may be good to explain why some things are named "lxbios" when we purge all mentioning of LinuxBIOS. (Some places where LinuxBIOS is mentioned should probably be left unchanged to preserve historic correctness.) Regards, Carl-Daniel

6 10

r3060 build service
by coreboot information 19 Jan '08

19 Jan '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "uwe" checked in revision 3060 to the coreboot source repository and caused the following changes: Change Log: Document the --list-supported option. Various small fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3060&device=serengeti_che… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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