coreboot January 2008

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r3072 - trunk/util/flashrom
by svn＠coreboot.org 22 Jan '08

22 Jan '08

Author: hailfinger Date: 2008-01-22 17:03:19 +0100 (Tue, 22 Jan 2008) New Revision: 3072 Modified: trunk/util/flashrom/flashchips.c Log: Here is just a little and simple patch to get the MX25L3205D working. I've tested and verified the chip myself, and it seems to work everything like supposted, since Carl-Daniel has patched flashrom to use the read funktion on verifying. "benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb Calibrating delay loop... OK. No coreboot table found. Found chipset "NVIDIA MCP55", enabling flash write... OK. Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... Serial flash segment 0xfffe0000-0xffffffff enabled Serial flash segment 0x000e0000-0x000fffff enabled Serial flash segment 0xffee0000-0xffefffff disabled Serial flash segment 0xfff80000-0xfffeffff enabled LPC write to serial flash enabled serial flash pin 29 OK. MX25L3205 found at physical address 0xffc00000. Flash part is MX25L3205 (4096 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED. benchvice flashrom # ls -l test.4mb -rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb Signed-off-by: Harald Gutmann <harald.gutmann(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2008-01-22 16:00:46 UTC (rev 3071) +++ trunk/util/flashrom/flashchips.c 2008-01-22 16:03:19 UTC (rev 3072) @@ -54,6 +54,8 @@ probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"MX25L8005", MX_ID, MX_25L8005, 1024, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, + {"MX25L3205", MX_ID, MX_25L3205, 4096, 256, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"SST25VF040B", SST_ID, SST_25VF040B, 512, 256, probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write, generic_spi_chip_read}, {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,

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r3071 - trunk/coreboot-v2/util
by svn＠coreboot.org 22 Jan '08

22 Jan '08

Author: uwe Date: 2008-01-22 17:00:46 +0100 (Tue, 22 Jan 2008) New Revision: 3071 Modified: trunk/coreboot-v2/util/ Log: Change svn:externals to use new coreboot.org domain (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Property changes on: trunk/coreboot-v2/util ___________________________________________________________________ Name: svn:externals - flashrom svn://linuxbios.org/repos/trunk/util/flashrom lxbios svn://linuxbios.org/repos/trunk/util/lxbios superiotool svn://linuxbios.org/repos/trunk/util/superiotool getpir svn://linuxbios.org/repos/trunk/util/getpir mptable svn://linuxbios.org/repos/trunk/util/mptable + flashrom svn://coreboot.org/repos/trunk/util/flashrom lxbios svn://coreboot.org/repos/trunk/util/lxbios superiotool svn://coreboot.org/repos/trunk/util/superiotool getpir svn://coreboot.org/repos/trunk/util/getpir mptable svn://coreboot.org/repos/trunk/util/mptable

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r3070 - trunk/util/flashrom
by svn＠coreboot.org 22 Jan '08

22 Jan '08

Author: hailfinger Date: 2008-01-22 16:19:01 +0100 (Tue, 22 Jan 2008) New Revision: 3070 Modified: trunk/util/flashrom/flashrom.c Log: Flashrom did not use the read function for verifying, it used direct memory access instead. That fails if the flash chip is not mapped completely. If the read function is set in struct flashchip, use it for verification as well. This fixes verification of all SPI flash chips >512 kByte behind an IT8716F flash translation chip. "MX25L8005 found at physical address 0xfff00000. Flash part is MX25L8005 (1024 KB). Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFIED." Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Harald Gutmann <harald.gutmann(a)gmx.net> Modified: trunk/util/flashrom/flashrom.c =================================================================== --- trunk/util/flashrom/flashrom.c 2008-01-22 14:37:31 UTC (rev 3069) +++ trunk/util/flashrom/flashrom.c 2008-01-22 15:19:01 UTC (rev 3070) @@ -159,7 +159,11 @@ { int idx; int total_size = flash->total_size * 1024; - volatile uint8_t *bios = flash->virtual_memory; + uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char)); + if (flash->read == NULL) + memcpy(buf2, (const char *)flash->virtual_memory, total_size); + else + flash->read(flash, buf2); printf("Verifying flash... "); @@ -170,7 +174,7 @@ if (verbose && ((idx & 0xfff) == 0xfff)) printf("0x%08x", idx); - if (*(bios + idx) != *(buf + idx)) { + if (*(buf2 + idx) != *(buf + idx)) { if (verbose) { printf("0x%08x ", idx); }

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[PATCH] flashrom: W39V040C support (was: contribution to flashrom)
by Uwe Hermann 22 Jan '08

22 Jan '08

Hi Tiago, On Tue, Jan 22, 2008 at 03:21:38AM +0000, Tiago Marques wrote: > Hi! > I have recently tried the flashrom software and it ended up saving my day. > I had a dead board, but with flashrom I managed to hotflash without > having to take that crap from proprietary flash software that it > doesn't let me flash because the bios I want to put there is different > or whatever. > > I managed to successfully flash in a board with a VT8237R, which > wasn't supported, by adding the proper ID. Great to hear. Please post a patch to coreboot(a)coreboot.org with a Signed-off-by line, see http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure > Also I would like to know what can I do to have one of the bios chip I > have here added to the support, which is the W39V04C from winbond. > I didn't find any documentation in how to do that. The datasheet for the chip is here: http://www.winbond.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/Para… If you're lucky it's similar enough to one of the other ones and you only need to add the proper chip ID. If you meant the 'W39V040C' (note the added '0') then please try the attached patch. Note that I didn't carefully check the datasheet, I just blindly added the IDs, so there's no guarantee it'll actually work ;-) The ID is mentioned on page 11 ('Product Identification Registers'). > Is there any kind of ML for flashrom development? Yes, flashrom development happens on the coreboot (previously known as LinuxBIOS) mailing list (CC'd), see http://www.coreboot.org/Mailinglist. I recommend to subscribe to that list. Cheers, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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r3069 - trunk/util/flashrom
by svn＠coreboot.org 22 Jan '08

22 Jan '08

Author: hailfinger Date: 2008-01-22 15:37:31 +0100 (Tue, 22 Jan 2008) New Revision: 3069 Modified: trunk/util/flashrom/spi.c Log: Make sure we delay writing the next byte long enough in SPI byte programming. Minor formatting changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Harald Gutmann <harald.gutmann(a)gmx.net> Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-01-21 23:55:08 UTC (rev 3068) +++ trunk/util/flashrom/spi.c 2008-01-22 14:37:31 UTC (rev 3069) @@ -94,7 +94,7 @@ uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ -int fast_spi=1; +int fast_spi = 1; void spi_prettyprint_status_register(struct flashchip *flash); void spi_disable_blockprotect(void); @@ -155,7 +155,7 @@ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis"); printf("LPC write to serial flash %sabled\n", (tmp & 1 << 4) ? "en" : "dis"); - printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); + printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29); /* LDN 0x7, reg 0x64/0x65 */ regwrite(port, 0x07, 0x7); flashport = regval(port, 0x64) << 8; @@ -348,14 +348,14 @@ */ void spi_prettyprint_status_register_sst25vf016(uint8_t status) { - const char *bpt[]={ + const char *bpt[] = { "none", "1F0000H-1FFFFFH", "1E0000H-1FFFFFH", "1C0000H-1FFFFFH", "180000H-1FFFFFH", "100000H-1FFFFFH", - "all","all" + "all", "all" }; printf_debug("Chip status register: Block Protect Write Disable " "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not "); @@ -449,7 +449,7 @@ generic_spi_write_enable(); outb(0x06 , it8716f_flashport + 1); - outb(((2+(fast_spi?1:0)) << 4), it8716f_flashport); + outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport); for (i = 0; i < 256; i++) { bios[256 * block + i] = buf[256 * block + i]; } @@ -513,18 +513,14 @@ { int total_size = 1024 * flash->total_size; int i; - fast_spi=0; + fast_spi = 0; spi_disable_blockprotect(); - for (i=0; i<total_size; i++) { + for (i = 0; i < total_size; i++) { generic_spi_write_enable(); - spi_byte_program(i,buf[i]); - /* FIXME: We really should read the status register and delay - * accordingly. - */ - //while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - myusec_delay(10); - //if (i%1024==0) fputc('b',stderr); + spi_byte_program(i, buf[i]); + while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + myusec_delay(10); } /* resume normal ops... */ outb(0x20, it8716f_flashport); @@ -534,9 +530,9 @@ void spi_3byte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ, - (address>>16)&0xff, - (address>>8)&0xff, - (address>>0)&0xff, + (address >> 16) & 0xff, + (address >> 8) & 0xff, + (address >> 0) & 0xff, }; /* Send Read */ @@ -551,13 +547,14 @@ { int total_size = 1024 * flash->total_size; int i; - fast_spi=0; + fast_spi = 0; if (total_size > 512 * 1024) { - for (i = 0; i < total_size; i+=3) { - int toread=3; - if (total_size-i < toread) toread=total_size-i; - spi_3byte_read(i, buf+i, toread); + for (i = 0; i < total_size; i += 3) { + int toread = 3; + if (total_size - i < toread) + toread = total_size - i; + spi_3byte_read(i, buf + i, toread); } } else { memcpy(buf, (const char *)flash->virtual_memory, total_size);

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[LinuxBIOS] Intel refactoring and microcode updates
by Corey Osgood 22 Jan '08

22 Jan '08

I've separated this into two patches, one code and one microcode, to improve readability, but they would both have to be committed at once (else things break). These patches eliminate a lot of repeated code, make porting and adding new CPUs easier, add all the latest released microcode updates, and add somewhat experimental support for the latest lga775 cpus, along with various other currently unsupported CPUs. Unfortunately, not everything works quite right yet. Here's the broken stuff: * socket_603: includes all Xeon model f0x, f1x, and f2x cpus. This may be incorrect, but I can't see any easy way to find out. * socket_604: includes all Xeon model f2x, f3x, f4x, and f6x. Same as above, with the added bonus of being too large to fit with any current board. It should also include the socket_603 IDs, since socket 603 CPUs work on socket 604 boards. * socket_775: too large to build with most current ports, but it could probably be broken down into socket_775_pentium and socket_775_core. All fxx IDs are pentium 4/D, and 6xx IDs are Core/Core 2 For now, I've left the current model_fxx and socket_*60*, so nothing breaks, but IMO the socket_603/604 I've added should be made to work. Both patches Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com>

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r3068 - trunk/util/flashrom
by svn＠coreboot.org 22 Jan '08

22 Jan '08

Author: hailfinger Date: 2008-01-22 00:55:08 +0100 (Tue, 22 Jan 2008) New Revision: 3068 Modified: trunk/util/flashrom/spi.c Log: Omitting the wait for SPI ready when there is no data to be read, e.g. readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing programming time for SST25VF016B to 40-45 secs. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2008-01-21 15:24:22 UTC (rev 3067) +++ trunk/util/flashrom/spi.c 2008-01-21 23:55:08 UTC (rev 3068) @@ -227,12 +227,15 @@ * We can't use writecnt directly, but have to use a strange encoding. */ outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), port); - do { - busy = inb(port) & 0x80; - } while (busy); - for (i = 0; i < readcnt; i++) { - readarr[i] = inb(port + 5 + i); + if (readcnt > 0) { + do { + busy = inb(port) & 0x80; + } while (busy); + + for (i = 0; i < readcnt; i++) { + readarr[i] = inb(port + 5 + i); + } } return 0;

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[PATCH] flashrom: less documentation duplication
by Uwe Hermann 21 Jan '08

21 Jan '08

See patch. We keep forgetting to update all the sources of information, let's drop some and only use one location where we document stuff (mostly wiki). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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AMD Geode Porting Guide
by Marc Jones 21 Jan '08

21 Jan '08

I added a porting guide to the wiki. http://www.coreboot.org/AMD_Geode_Porting_Guide Please let me know what is missing or how it can be better. Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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#92: Add --version option
by coreboot 21 Jan '08

21 Jan '08

#92: Add --version option ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Enhance the flashrom utility Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Flashrom should have a --version option too, similar to superiotool (based on svn revision). -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/92> coreboot <http://www.coreboot.org/>

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coreboot January 2008