coreboot August 2007

coreboot@coreboot.org

78 participants
202 discussions

[LinuxBIOS] Is my motherboard supported?...
by Robert Oscilowski 18 Aug '07

18 Aug '07

Hi! I need to know if my motherboard is supported. I'm pretty sure most of its components are at least work-in-progress, but I'm not sure. Here is what I know about my system: CPU: Intel Pentium II 400Mhz -- I'm thinking about upgrading it soon... Northbridge: Intel 82443BX Southbridge: Intel 82371EB Super I/O: SMSC FDC37M707 Mainboard: Intel SE440BX-2 *Flash Chip: Intel... TSOC? It's a pity I can't send pictures; I need help identifying it! lspci output: 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00:0d.0 Multimedia audio controller: Creative Labs SB Live! EMU10k1 (rev 04) 00:0d.1 Input device controller: Creative Labs SB Live! Game Port (rev 01) 00:0e.0 FireWire (IEEE 1394): Agere Systems FW323 (rev 61) 00:10.0 Ethernet controller: D-Link System Inc DL10050 Sundance Ethernet (rev 12) 01:00.0 VGA compatible controller: nVidia Corporation NV4 [RIVA TNT] (rev 04) Thanks! -- robjoski-1

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[LinuxBIOS] VIA CX700 Support
by bari 18 Aug '07

18 Aug '07

Has anyone started on VIA CX700 support? http://www.via.com.tw/en/products/chipsets/c-series/cx700/

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[LinuxBIOS] reset16 vs reset32
by Marc Jones 17 Aug '07

17 Aug '07

I am running into a build problem with a ROM that contains normal, fallback, and failover images. I get the following error. /usr/bin/ld: section .data [00000000fffbfff0 -> 00000000fffc07ff] overlaps section .reset [00000000fffbfff0 -> 00000000fffbffff] /usr/bin/ld: linuxbios: section .data lma 0xfffbfff0 overlaps previous sections Which means that the ldscript calculations is wrong (see attached ldscript.ld). What is the difference between reset16 and reset32? Why does reset32.lds do a calculation? Reset always needs to be at 0xFFFFFFF0. Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors /*ldoptions*/ HAVE_MOVNTI = 1; CONFIG_USE_INIT = 0; HAVE_FALLBACK_BOOT = 1; HAVE_FAILOVER_BOOT = 1; ROM_IMAGE_SIZE = 0x20000; PAYLOAD_SIZE = 0xa0000; _ROMBASE = 0xfffa0000; _RESET = 0xfffa0000; _EXCEPTION_VECTORS = 0xfffa0100; STACK_SIZE = 0x2000; HEAP_SIZE = 0xc0000; _RAMBASE = 0x200000; USE_DCACHE_RAM = 1; CAR_GH = 1; DCACHE_RAM_BASE = 0xc4000; DCACHE_RAM_SIZE = 0xc000; DCACHE_RAM_GLOBAL_VAR_SIZE = 0x4000; CONFIG_AP_CODE_IN_CAR = 0; MEM_TRAIN_SEQ = 2; WAIT_BEFORE_CPUS_INIT = 0; CONFIG_COMPRESS = 1; CONFIG_UNCOMPRESSED = 0; CONFIG_LB_MEM_TOPK = 16384; HAVE_OPTION_TABLE = 1; USE_OPTION_TABLE = 1; LB_CKS_RANGE_START = 49; LB_CKS_RANGE_END = 122; LB_CKS_LOC = 123; DEBUG = 1; CONFIG_CONSOLE_VGA = 1; CONFIG_CONSOLE_VGA_MULTI = 0; CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST = 0; CONFIG_CONSOLE_BTEXT = 0; CONFIG_CONSOLE_LOGBUF = 0; CONFIG_CONSOLE_SROM = 0; CONFIG_CONSOLE_SERIAL8250 = 1; CONFIG_USBDEBUG_DIRECT = 0; DEFAULT_CONSOLE_LOGLEVEL = 8; MAXIMUM_CONSOLE_LOGLEVEL = 8; CONFIG_SERIAL_POST = 0; TTYS0_BASE = 0x3f8; TTYS0_BAUD = 115200; TTYS0_LCS = 0x3; CONFIG_USE_PRINTK_IN_CAR = 1; MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 4130; MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x2b80; CONFIG_SMP = 1; CONFIG_MAX_CPUS = 8; CONFIG_MAX_PHYSICAL_CPUS = 8; CONFIG_LOGICAL_CPUS = 0; SERIAL_CPU_INIT = 1; APIC_ID_OFFSET = 0; ENABLE_APIC_EXT_ID = 1; LIFT_BSP_APIC_ID = 1; CONFIG_IDE_STREAM = 0; CONFIG_ROM_STREAM = 1; CONFIG_ROM_STREAM_START = 0xfff00000; CONFIG_COMPRESSED_ROM_STREAM = 0; CONFIG_COMPRESSED_ROM_STREAM_NRV2B = 0; CONFIG_COMPRESSED_ROM_STREAM_LZMA = 0; CONFIG_PRECOMPRESSED_ROM_STREAM = 0; CONFIG_FS_STREAM = 0; CONFIG_FS_EXT2 = 0; CONFIG_FS_ISO9660 = 0; CONFIG_FS_FAT = 0; AUTOBOOT_DELAY = 2; USE_WATCHDOG_ON_BOOT = 0; CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT = 1; CONFIG_AGP_PLUGIN_SUPPORT = 1; CONFIG_CARDBUS_PLUGIN_SUPPORT = 1; CONFIG_PCIX_PLUGIN_SUPPORT = 1; CONFIG_PCIEXP_PLUGIN_SUPPORT = 1; CONFIG_IDE = 0; IDE_BOOT_DRIVE = 0; IDE_OFFSET = 0; PCI_IO_CFG_EXT = 1; CONFIG_CHIP_NAME = 1; HAVE_INIT_TIMER = 1; MAX_REBOOT_CNT = 3; FAKE_SPDROM = 0; HAVE_ACPI_TABLES = 1; ACPI_SSDTX_NUM = 31; HT_CHAIN_UNITID_BASE = 10; HT_CHAIN_END_UNITID_BASE = 6; SB_HT_CHAIN_UNITID_OFFSET_ONLY = 1; SB_HT_CHAIN_ON_BUS0 = 2; PCI_BUS_SEGN_BITS = 0; MMCONF_SUPPORT = 0; MMCONF_SUPPORT_DEFAULT = 0; HW_MEM_HOLE_SIZEK = 1048576; HW_MEM_HOLE_SIZE_AUTO_INC = 0; CONFIG_VAR_MTRR_HOLE = 1; K8_HT_FREQ_1G_SUPPORT = 0; K8_REV_F_SUPPORT = 0; CBB = 0; CDB = 24; HT3_SUPPORT = 1; EXT_RT_TBL_SUPPORT = 0; EXT_CONF_SUPPORT = 0; DIMM_SUPPORT = 0x104; CPU_SOCKET_TYPE = 16; CPU_ADDR_BITS = 48; CONFIG_PCI_ROM_RUN = 1; CONFIG_PCI_64BIT_PREF_MEM = 0; CONFIG_AGESA = 1; HAVE_MP_TABLE = 1; HAVE_PIRQ_TABLE = 1; USE_FALLBACK_IMAGE = 0; USE_FAILOVER_IMAGE = 0; HAVE_HARD_RESET = 1; IRQ_SLOT_COUNT = 11; CONFIG_IOAPIC = 1; FALLBACK_SIZE = 0x3f000; FAILOVER_SIZE = 0x1000; ROM_SIZE = 0x100000; ROM_SECTION_SIZE = 0xc0000; ROM_SECTION_OFFSET = 0x0; XIP_ROM_SIZE = 0x40000; XIP_ROM_BASE = 0xfff80000; CONFIG_GDB_STUB = 0; CONFIG_UDELAY_IO = 0; CONFIG_UDELAY_TSC = 0; CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 0; AGP_APERTURE_SIZE = 0x4000000; /* /home/marcj/lb2/src/arch/i386/init/ldscript.lb */ /* * Memory map: * * _RAMBASE * : data segment * : bss segment * : heap * : stack * _ROMBASE * : linuxbios text * : readonly text */ /* * Bootstrap code for the STPC Consumer * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. * */ /* * Written by Johan Rydberg, based on work by Daniel Kahlin. * Rewritten by Eric Biederman */ /* * We use ELF as output format. So that we can * debug the code in some form. */ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) /* ENTRY(_start) */ TARGET(binary) INPUT(linuxbios_ram.rom) SECTIONS { . = _ROMBASE; .ram . : { _ram = . ; linuxbios_ram.rom(*) _eram = . ; } /* This section might be better named .setup */ .rom . : { _rom = .; *(.rom.text); *(.rom.data); *(.rom.data.*); . = ALIGN(16); _erom = .; } _lrom = LOADADDR(.rom); _elrom = LOADADDR(.rom) + SIZEOF(.rom); _iseg = _RAMBASE; _eiseg = _iseg + SIZEOF(.ram); _liseg = _ram; _eliseg = _eram; /DISCARD/ : { *(.comment) *(.note) } } /* /home/marcj/lb2/src//cpu/x86/32bit/reset32.lds */ /* * _ROMTOP : The top of the rom used where we * need to put the reset vector. */ SECTIONS { _ROMTOP = _ROMBASE + ROM_IMAGE_SIZE - 0x10; . = _ROMTOP; .reset (.): { *(.reset) . = 15 ; BYTE(0x00); } } /* /home/marcj/lb2/src//arch/i386/lib/id.lds */ SECTIONS { . = (_ROMBASE + ROM_IMAGE_SIZE - 0x10) - (__id_end - __id_start); .id (.): { *(.id) } }

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Re: [LinuxBIOS] I have a push pin flash (Huzzah!) Now to get some more...
by Richard Wilson 17 Aug '07

17 Aug '07

Chris Lingard wrote: > Richard Wilson wrote: >> Having consulted the list and concluded I was unlikely to find a Bios >> Saviour, I went at my chip with a push pin and some superglue. Success! >> Thanks to all who made suggestions. I have two important questions: >> >> I've found a UK ebay item of 6 SST 39SF020A chips, which appear to be >> the ones I want for my EPIA-MII 12000. Am I right, and could I go for a >> 4Meg chip if I wanted? >> >> Additionally, I have next to no coding ability, so I feel it falls to me >> to contribute in some other way. There are 6 currently available in the >> auction, and I feel I need at most 3. Are there any active developers >> who'd like a free 39F020A? I'd quite happily buy the lot and send the >> unneeded ones anywhere in Europe, if it'll do some good to the project. >> Heck I could probably stretch to the US if the postage isn't too hideous. >> >> Any takers? The auction ends in 5 days, but its a buy it now, so if I >> want them all I should probably get them sooner rather than later... >> > > Saw your post on LinuxBios, I am about to start work on it too. > > I have already a Gigabyte M57SLI mother board, and have built the > machine and installed Linux. I am using it right now. > > I am a system programmer but have no knowledge of engineering at all > > I need to buy whatever you solder onto the motherboard, a guy at the > local computer shop can do the actual work. > > I can get the 120K resister, the three pieces of wire and a switch; > after that you may as well speak Ancient Greek to me. > > Can you fix me up with what I need to buy, I can pay, I do not need a > handout. Thanks > > Chris Lingard > I think there might be a bit of confusion here - I'm planning on buying some bios chips and putting push pin knobs on them to make them easier to swap around - I'm not making any custom hardware or the home-brew switcher others have mentioned. The ebay auction I'm looking at is at http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&rd=1&item=280143009151&ssPa… if you want to get some chips yourself. I wasn't suggesting anyone needed handouts, but I do know that there's a few developers on the list who are currently students, and I remember being a bit short of pennies when I was at university myself, not so long ago... Richard W

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[LinuxBIOS] help with bios to GEODE GX
by angelini 17 Aug '07

17 Aug '07

Dear friends, I dont know if is possible or if works in this way, i need make a changes video ram memory sharing in my GEODE GX533@1W bios today they using 8mb of ram to video, and FIC told me that's GX533 is able to using at 64mb, but AMD don't provide BIOS changes to this. Please help me! If is possible! Angelini

1 0

[LinuxBIOS] ICH4 BIOS chip not recognised.
by Raúl Sánchez Siles 16 Aug '07

16 Aug '07

Hello all: I was interested in upgrading my computer BIOS. This is a laptop Dell Inspiron 510m. The mother board is an ICH4, more details on request. So I came across flashroom and I tried to use it, and since the motherboard was recognised, there wasn't that luck with the BIOS chip. After all this I effectively did the upgrade but using the manufacturer recommended biosdisk method (it worked). But after that I wanted to know more and aafter some talk with someone at the channel, he (sorry I can't remember your name) told me to send the flashrom -V report here and here I am: flashrom -V Calibrating delay loop... 376M loops per second. ok No LinuxBIOS table found. Found chipset "ICH4-M": Enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xea, id2 0xf0 Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for At29C040A, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for At29C020, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for Mx29f002, 256 KB probe_29f002: id1 0xea, id2 0xf0 Probing for SST29EE020A, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xea, id2 0xf0 Probing for SST39SF010A, 128 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST39SF020A, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST39SF040, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST39VF020, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF040B, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF040, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF020A, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xea, id2 0xf0 Probing for Pm49FL002, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0xea, id2 0xf0 Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xea, id2 0xf0 Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL004, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W29C011, 128 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W29C020C, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W49F002U, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W49V002A, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W49V002FA, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W39V040FA, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W39V040A, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W39V040B, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for W39V080A, 1024 KB probe_jedec: id1 0xea, id2 0xf0 Probing for M29F002B, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for M29F002T/NT, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0xea, id2 0xf0 Probing for M29F040B, 512 KB probe_29f040b: id1 0xea, id2 0xf0 Probing for 82802ab, 512 KB probe_82802ab: id1 0xea, id2 0xf0 Probing for 82802ac, 1024 KB probe_82802ab: id1 0xea, id2 0xf0 Probing for F49B002UA, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xea, id2 0xf0 Probing for S29C51001T, 128 KB probe_jedec: id1 0xea, id2 0xf0 Probing for S29C51002T, 256 KB probe_jedec: id1 0xea, id2 0xf0 Probing for S29C51004T, 512 KB probe_jedec: id1 0xea, id2 0xf0 Probing for S29C31004T, 512 KB probe_jedec: id1 0xea, id2 0xf0 No EEPROM/flash device found. Regards,

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[LinuxBIOS] test
by Janek Kozicki 16 Aug '07

16 Aug '07

I'm sorry, I had a problem with subscription. I hope it's OK now. -- Janek Kozicki |

3 2

[LinuxBIOS] littler image in bigger rom
by Markus 16 Aug '07

16 Aug '07

Hi Volks, I bought a 4 Mb Rom vor my Epia-v board. Flashrom can handel the chip but it isn't willig to programm the image of the old 2 Mb Chip in the 4 Mb Chip. Any idea's to solve this? Greeding Markus

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[LinuxBIOS] [PATCH] Reimplementation/fixing of CS5530/CS5530A southbridge code
by Uwe Hermann 16 Aug '07

16 Aug '07

See patch. This is also required to make the JUKI-511P code work AFAICT (won't build otherwise). Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] Need help with the VGA bios
by Corey Osgood 16 Aug '07

16 Aug '07

Okay, I know I've been asking for a lot of help lately, and I'm really sorry. This should be the last time, for now ;-) The vga bios on the jetway j7f2we1g is causing errors any time I try to load it, sometimes boot continues anyways but vga never initializes. Attached are 2 patches (one for the vt8237r, the other for everything else, not ready for commit by any means) and a log file, for both vm86.c (hacked up from the epia-m) and x86emu. The VGA rom I've been using I extracted with awardeco and is available for now here: http://rapidshare.com/files/48880059/E14JTWAY.ROM.html (only for testing/inspection purposes, will be removed once this is running or upon request from Via or Jetway). I've tried roms from the original and latest jetway bios (that is from the original), and also one from a via epia-cn, all give the same result. Any help would be greatly appreciated. -Corey

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coreboot August 2007