coreboot August 2007

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78 participants
202 discussions

[LinuxBIOS] VIA K8T890+VT8237 - update of the status
by Rudolf Marek 16 Aug '07

16 Aug '07

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all, I'm typing this message in Thunderbird from LinuxBIOS booted system. Yeah I told this last time, but I have still some issues left. 1) Single channel memory problems I have two 512MB dimms in singe channel, because LinuxBIOS does not handle dualchannel for unbuffered Dimms. However when I'm using 512-1024MB of the RAM systems forces to random reboot when booting kernel or when in X. Booting with mem=512MB works like a charm 2) Reboot does not work. I dont know what I have wrong, but my fallback image just produces the initial string when console is initialized and nothing more. I have no clue what is wrong. I dont know what failover and fallback is precisely... 3) DMA to 0xE0000-0xEFFFF fails This is under investigation. I asked VIA about this. 4) no HPET and no ACPI, no PCI MCONFIG yet 5) I have some issues with LB itself when preparing various init files. The resource system have some serious trouble if I add my file for the PCIe bridge init. If I call the function not from init or enable methods but from general init and via pci_find_device, everything will work again. This seems like some issue with the infrastructure of LB rather than HW problem. I may write more about my issues if only someone is willing to help ;) I can put my code online somewhere. Maybe it would be good to check it in even if the code for NB is a bit of mess. USB/sound/SATA/IDE/PCIe/Network/Serial/Graphics/APIC works do far... Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFGuP3l3J9wPJqZRNURAh9zAJoDQ1pIlVH5ZD0Lg4NdIlp6BlLnTgCfZnOO sj9O/OW5vn8+1PGl8gMLVYA= =i4Xk -----END PGP SIGNATURE-----

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Re: [LinuxBIOS] [PATCH] Initial support for the ASUS A8NE-FM
by Robert Millan 16 Aug '07

16 Aug '07

On my A8N5X, linuxbios gets quite far (it gets to vga initialisation, and then breaks - will write about that later). > Index: src/northbridge/amd/amdk8/raminit.c > =================================================================== > --- src/northbridge/amd/amdk8/raminit.c (Revision 2739) > +++ src/northbridge/amd/amdk8/raminit.c (Arbeitskopie) > @@ -620,7 +620,8 @@ > #warning "FIXME: Implement a better test for Opterons" > uint32_t nbcap; > nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); > - return !!(nbcap & NBCAP_128Bit); > + //// return !!(nbcap & NBCAP_128Bit); > + return 0; > } > > static int is_registered(const struct mem_controller *ctrl) I had to take this part of your patch to fix Opteron miss-detection. Are you checking for the cpu itself? If this is so, I think CPUID would be much more reliable. Would you like a patch for that? -- Robert Millan <GPLv2> I know my rights; I want my phone call! <DRM> What use is a phone call, if you are unable to speak? (as seen on /.)

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[LinuxBIOS] EEPROM/flash device not found error
by pratish ganguly 16 Aug '07

16 Aug '07

Hi I am using flashrom to upgrade the BIOS on AMD Geode db800 motherboard. I am getting the following error EEPROM/flash device not found. Please suggest me some pointers to solve the problem. Regards. Pratish Ganguly

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[LinuxBIOS] lpci_set_subsystem question
by Marc Jones 15 Aug '07

15 Aug '07

I see a couple of different versions of lpci_set_subsystem function and I wonder why. For example: src\southbridge\broadcom\bcm5780\bcm5780_nic.c: static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } src\southbridge\amd\amd8111\amd8111_ide.c: static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x70, ((device & 0xffff) << 16) | (vendor & 0xffff)); } src\southbridge\broadcom\bcm5780\bcm5780_sb_pci_main.c: static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { pci_write_config32(dev, 0x2c, ((device & 0xffff) << 16) | (vendor & 0xffff)); } Shouldn't the PCI config register always be 0x2c (subsystem ID register) like in the last example (bcm5780_sb_pci_main.c)? Should these functions even be there since there is a stock pci_dev_set_subsystem() that seems to be correct? Am I mis-understanding this function? Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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[LinuxBIOS] flashrom geodelx patch
by Ingmar Schraub 15 Aug '07

15 Aug '07

Add support for AMD Geode LX / CS5536 to the flashrom utility. Signed-off-by: Ingmar Schraub <is(a)eseco.de> --- regards, Ingmar

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[LinuxBIOS] where are we on the MSI K9N Neo-F?
by Ward Vandewege 15 Aug '07

15 Aug '07

I'm looking to buy a new desktop machine today or tomorrow. There were several posts last November bout the MSI K9N Neo-F: http://www.openbios.org/pipermail/linuxbios/2006-November/thread.html Where are we with that board? It's cheap and on the face of it should be fairly easy to port - MCP55 chipset, etc. There was some concern about the ehternet card? I think I'll get this board or perhaps one of the Abit KN9 ones that are very similar to the Gigabyte M57SLI-S4. All have a PLCC socket which is a big plus. If anyone has been working on these boards give me a shout - I'd like to put some work into adding support for one of these. Thanks, Ward. -- Ward Vandewege <ward(a)gnu.org>

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[LinuxBIOS] make dependencies and C includes
by Robert Millan 15 Aug '07

15 Aug '07

Hi! I've observed that C #include'd files such as raminit.c aren't represented in make dependencies, resulting in them not being recompiled after a modification. I'm not sure what would be the proper solution: - add the dependency manually in the corresponding Config.lb files? - migrate use of #include to separate compilation and standard linking? - modify util/newconfig/config.g to automatical scan C files and add the dependencies for #includes? -- Robert Millan <GPLv2> I know my rights; I want my phone call! <DRM> What use is a phone call, if you are unable to speak? (as seen on /.)

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[LinuxBIOS] I have a push pin flash (Huzzah!) Now to get some more...
by Richard Wilson 15 Aug '07

15 Aug '07

Having consulted the list and concluded I was unlikely to find a Bios Saviour, I went at my chip with a push pin and some superglue. Success! Thanks to all who made suggestions. I have two important questions: I've found a UK ebay item of 6 SST 39SF020A chips, which appear to be the ones I want for my EPIA-MII 12000. Am I right, and could I go for a 4Meg chip if I wanted? Additionally, I have next to no coding ability, so I feel it falls to me to contribute in some other way. There are 6 currently available in the auction, and I feel I need at most 3. Are there any active developers who'd like a free 39F020A? I'd quite happily buy the lot and send the unneeded ones anywhere in Europe, if it'll do some good to the project. Heck I could probably stretch to the US if the postage isn't too hideous. Any takers? The auction ends in 5 days, but its a buy it now, so if I want them all I should probably get them sooner rather than later... -- Richard 'Dave' Wilson Systems Administrator Senokian Solutions Ltd. Business Innovation Centre, Binley Business Park, Coventry, United Kingdom CV3 2TX T: +44 (0)24 76 233 400 DDI: +44 (0)24 76 233 416 F: +44 (0)24 76 233 401

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[LinuxBIOS] Setting up ethernet - help
by Joseph Smith 15 Aug '07

15 Aug '07

OK I am having a problem setting up my ethernet controller in src/mainboard Config.lb. Quoting from the i82830 Datasheet: Logically, the ICH3-M appears as two PCI devices within a single physical component also residing on PCI bus #0. One of the ICH4 devices residing on PCI Bus #0 is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI bus #0 while the secondary side is the standard PCI expansion bus (PCI0). Also within the ICH3-M is another PCI Device, the LAN Controller, which resides on the standard PCI expansion bus (PCI0) down from the PCI-to-PCI bridge. lspci -n 00:1e.0 0604: 8086:244e (rev 82) 01:08.0 0200: 8086:103a (rev 82) lspci-tvv -[0000:00]-+-1e.0-[0000:01]----08.0 Intel Corporation 82801DB PRO/100 VE (CNR) Ethernet Controller lspci-v 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 82) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: ff700000-ff7fffff 01:08.0 Ethernet controller: Intel Corporation 82801DB PRO/100 VE (CNR) Ethernet Controller (rev 82) Flags: bus master, medium devsel, latency 64, IRQ 11 Memory at ff7ff000 (32-bit, non-prefetchable) [size=4K] I/O ports at dc00 [size=64] Capabilities: [dc] Power Management version 2 How the heck do I set this up in Config.lb? HELP?? Thanks - Joe

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[LinuxBIOS] Any VIA C7 Support?
by bari 15 Aug '07

15 Aug '07

Has anyone started on supporting the VIA C7 cpu's yet? -Bari

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coreboot August 2007