coreboot August 2007

coreboot@coreboot.org

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202 discussions

[LinuxBIOS] r2743 - trunk/util/flashrom
by svn＠openbios.org 11 Aug '07

11 Aug '07

Author: uwe Date: 2007-08-11 18:59:11 +0200 (Sat, 11 Aug 2007) New Revision: 2743 Modified: trunk/util/flashrom/README trunk/util/flashrom/board_enable.c Log: flashrom: Add board enable for the EPoX EP-BX3. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/flashrom/README =================================================================== --- trunk/util/flashrom/README 2007-07-27 03:32:45 UTC (rev 2742) +++ trunk/util/flashrom/README 2007-08-11 16:59:11 UTC (rev 2743) @@ -54,6 +54,7 @@ * Agami Aruma: use -m AGAMI:ARUMA * ASUS P5A: use -m asus:p5a * IBM x3455: use -m ibm:x3455 +* EPoX EP-BX3: use -m epox:ep-bx3 ROM Layout Support Modified: trunk/util/flashrom/board_enable.c =================================================================== --- trunk/util/flashrom/board_enable.c 2007-07-27 03:32:45 UTC (rev 2742) +++ trunk/util/flashrom/board_enable.c 2007-08-11 16:59:11 UTC (rev 2743) @@ -261,6 +261,25 @@ return 0; } +/** + * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. + */ +static int board_epox_ep_bx3(const char *name) +{ + uint8_t tmp; + + /* Raise GPIO22. */ + tmp = inb(0x4036); + outb(tmp, 0xEB); + + tmp |= 0x40; + + outb(tmp, 0x4036); + outb(tmp, 0xEB); + + return 0; +} + /* * We use 2 sets of ids here, you're free to choose which is which. This * to provide a very high degree of certainty when matching a board on @@ -309,6 +328,8 @@ "asus", "p5a", "ASUS P5A", board_asus_p5a}, {0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000, "ibm", "x3455", "IBM x3455", board_ibm_x3455}, + {0x8086, 0x7110, 0x0000, 0x0000, 0x8086, 0x7190, 0x0000, 0x0000, + "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3}, {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */ };

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Re: [LinuxBIOS] RAM detection for Intel 430FX
by popkonserve 11 Aug '07

11 Aug '07

hi, as promised the ram init routine for the intel 430fx chipset. completely untested yet, but seems to compile without errors (at least those i could have typed in ;)) the datasheet for the chipset is here: http://download.intel.com/design/chipsets/datashts/29051801.pdf the routine does the following: 1. disable all caches 2. set ram size to 0 3. take one row and set its ram size to the maximum value and its type to edo 4. write some data in the row 5. enable edo detection 6. read the data back 7. if the data read is the data written it is edo 8. if the data read is NOT the data written, write some more data 9. read the data back (without edo detection) 10. if the data read is the data written it is fpm 11. if the data read is NOT the data written, the row is empty 12. detect the real size of the row and the dram technology (i'll write some more about that tomorrow, sorry, it's late already :)) 13. clear all settings for the current row 14. restart at 3. as long as not all rows have been processed 15. write the size and type (edo/fpm) of all rows 16. turn the caches back on ;) the routine isn't doing any tests on dram timings yet. this COULD be implemented or we should ask the user to enter something useful. upto now the slowest dram timings are used which is not that nice but still it should work. anyway, i could implement some more chipset settings regarding pci performance and behaviour but i guess it doesn't belong in the raminit.c, does it? now have a look at the code and try to understand it ;) Holger /* * This file is part of the LinuxBIOS project. * * Copyright (C) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <delay.h> #include <device/device.h> #include "raminit.h" /*----------------------------------------------------------------------------- Macros and definitions. -----------------------------------------------------------------------------*/ /* Uncomment this to enable debugging output. */ #define DEBUG_RAM_SETUP 1 /* Debugging macros. */ #if defined(DEBUG_RAM_SETUP) #define PRINT_DEBUG(x) print_debug(x) #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else #define PRINT_DEBUG_(x) #define PRINT_DEBUG_HEX8(x) #define PRINT_DEBUG_HEX16(x) #define PRINT_DEBUG_HEX32(x) #define DUMPNORTH() #endif /*----------------------------------------------------------------------------- EDO/FP/SDRAM detection routine. ----------------------------------------------------------------------------*/ /** * Initializes a row before it can be checked for DRAM */ static void initialize_row(const struct mem_controller* ctrl, const uint8_t u8_row) { uint8_t u8_DRAMSize = 0; uint8_t u8_DRAMType = 1; /* Initialize the current row to EDO and 32MB (maximum size) */ u8_DRAMType <<= u8_row; u8_DRAMSize == SIMM_ROW_SIZE_MAX / SIMM_GRANULARITY; pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, u8_DRAMSize); pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_TYPE), u8_DRAMType); } /** * Clears a row after it has been checked for DRAM */ static void clear_row(const struct mem_controller* ctrl, const uint8_t u8_row) { uint8_t u8_DRAMSize = 0; pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, u8_DRAMSize); } /** * Detects the type of RAM in the current row */ static void detect_type(const struct mem_controller* ctrl, uint8_t* pu8_DRAMSize, uint8_t* pu8_DRAMType, const uint8_t u8_row) { uint8_t u8_DRAMC = 0; uint32_t u32_AA0 = 0x0; uint32_t u32_AA8 = 0x8; uint32_t u32_DD1 = 0xAAAAAAAAUL; uint32_t u32_DD2 = 0x55555555UL; uint32_t u32_DD3 = 0; uint32_t u32_DD4 = 0; /* Write some data */ dimm_write32(u32_AA0, u32_DD1); dimm_write32(u32_AA8, u32_DD2); /* Enable EDO detection mode */ u8_DRAMC = pci_read_config8(ctrl->d0, ((uint8_t)e_DRAM_CONTROL)); u8_DRAMC |= ((uint8_t)e_DRAMC_EDO_DETECT); pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_CONTROL), u8_DRAMC); /* Read the data back */ dimm_read32(u32_AA0, u32_DD3); dimm_read32(u32_AA8, u32_DD4); /* Disable EDO detection mode */ u8_DRAMC &= ~((uint8_t)e_DRAMC_EDO_DETECT); pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_CONTROL), u8_DRAMC); if(u32_DD3 != u32_DD1 || u32_DD4 != u32_DD2) { /* No EDO RAM. Test FPM next */ /* Set the current bank to FPM */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_TYPE), 0x00); /* Write some data */ dimm_write32(u32_AA0, u32_DD1); dimm_write32(u32_AA8, u32_DD2); /* Read the data back */ dimm_read32(u32_AA0, u32_DD3); dimm_read32(u32_AA8, u32_DD4); if(u32_DD3 != u32_DD1 || u32_DD4 != u32_DD2) { /* No FPM RAM. No RAM at all! */ *(pu8_DRAMSize) = 0; } else { *(pu8_DRAMType) &= ~(1 << u8_row); } } else { /* EDO found */ *(pu8_DRAMType) |= (1 << u8_row); } } /** * Detects DRAM row size */ static void detect_size(const struct mem_controller* ctrl, uint8_t* au8_DRAMSize, const uint8_t u8_row) { uint32_t u32_AA0 = 0x0; uint32_t u32_AA8 = 1; uint32_t u32_DD1 = 0x55555555UL; uint32_t u32_DD2 = 0xAAAAAAAAUL; uint32_t u32_DD3 = 0xFEDCBA98UL; uint32_t u32_DD4 = 0; uint8_t u8_size_detected = 0; uint8_t u8_type = 0; for(;;) { /* Write some data */ dimm_write32(u32_AA0, u32_DD1); switch (au8_DRAMSize[u8_row]) { case e_4MB : { for(u8_type = 0; u8_type < RCA_8MB_TYPES; u8_type++) { /* Prepare the first address */ u32_AA8 = (1 << s_DRAMT8MB[u8_type].u8_ColumnAddress); /* Write some more data */ dimm_write32(u32_AA8, u32_DD2); /* Write even more data to yet another address for asymetric DRAM */ if(s_DRAMT8MB[u8_type].u8_ColumnAddress != s_DRAMT8MB[u8_type].u8_RowAddress) { /* Prepare the second address */ u32_AA8 = (1 << s_DRAMT8MB[u8_type].u8_RowAddress); /* Write even more data */ dimm_write32(u32_AA8, u32_DD3); } /* Read data back */ dimm_read32(u32_AA0, u32_DD4); if(u32_DD1 == u32_DD4) { /* Found DRAM with correct size and technology */ au8_DRAMSize[u8_row] = ((uint8_t)e_4MB); u8_size_detected = 1; break; } } /* No DRAM was found! */ if(u8_size_detected == 0) { au8_DRAMSize[u8_row] = ((uint8_t)e_EMPTY); /* FIXME: Not sure if this is really needed */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, au8_DRAMSize[u8_row]); } break; } case e_8MB : { for(u8_type = 0; u8_type < RCA_8MB_TYPES; u8_type++) { /* Prepare the first address */ u32_AA8 = (1 << s_DRAMT8MB[u8_type].u8_ColumnAddress); /* Write some more data */ dimm_write32(u32_AA8, u32_DD2); /* Write even more data to yet another address for asymetric DRAM */ if(s_DRAMT8MB[u8_type].u8_ColumnAddress != s_DRAMT8MB[u8_type].u8_RowAddress) { /* Prepare the second address */ u32_AA8 = (1 << s_DRAMT8MB[u8_type].u8_RowAddress); /* Write even more data */ dimm_write32(u32_AA8, u32_DD3); } /* Read data back */ dimm_read32(u32_AA0, u32_DD4); if(u32_DD1 == u32_DD4) { /* Found DRAM with correct size and technology */ au8_DRAMSize[u8_row] = ((uint8_t)e_8MB); u8_size_detected = 1; break; } } /* Test for 4MB next if no 8MB DRAM was found */ if(u8_size_detected == 0) { au8_DRAMSize[u8_row] = ((uint8_t)e_4MB); /* FIXME: Not sure if this is really needed */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, au8_DRAMSize[u8_row]); } break; } case e_16MB : { for(u8_type = 0; u8_type < RCA_16MB_TYPES; u8_type++) { /* Prepare the first address */ u32_AA8 = (1 << s_DRAMT16MB[u8_type].u8_ColumnAddress); /* Write some more data */ dimm_write32(u32_AA8, u32_DD2); /* Write even more data to yet another address for asymetric DRAM */ if(s_DRAMT16MB[u8_type].u8_ColumnAddress != s_DRAMT16MB[u8_type].u8_RowAddress) { /* Prepare the second address */ u32_AA8 = (1 << s_DRAMT16MB[u8_type].u8_RowAddress); /* Write even more data */ dimm_write32(u32_AA8, u32_DD3); } /* Read data back */ dimm_read32(u32_AA0, u32_DD4); if(u32_DD1 == u32_DD4) { /* Found DRAM with correct size and technology */ au8_DRAMSize[u8_row] = ((uint8_t)e_16MB); u8_size_detected = 1; break; } } /* Test for 8MB next if no 16MB DRAM was found */ if(u8_size_detected == 0) { au8_DRAMSize[u8_row] = ((uint8_t)e_8MB); /* FIXME: Not sure if this is really needed */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, au8_DRAMSize[u8_row]); } break; } case e_32MB : { for(u8_type = 0; u8_type < RCA_32MB_TYPES; u8_type++) { /* Prepare the first address */ u32_AA8 = (1 << s_DRAMT32MB[u8_type].u8_ColumnAddress); /* Write some more data */ dimm_write32(u32_AA8, u32_DD2); /* Write even more data to yet another address for asymetric DRAM */ if(s_DRAMT32MB[u8_type].u8_ColumnAddress != s_DRAMT32MB[u8_type].u8_RowAddress) { /* Prepare the second address */ u32_AA8 = (1 << s_DRAMT32MB[u8_type].u8_RowAddress); /* Write even more data */ dimm_write32(u32_AA8, u32_DD3); } /* Read data back */ dimm_read32(u32_AA0, u32_DD4); if(u32_DD1 == u32_DD4) { /* Found DRAM with correct size and technology */ au8_DRAMSize[u8_row] = ((uint8_t)e_32MB); u8_size_detected = 1; break; } } /* Test for 16MB next if no 32MB DRAM was found */ if(u8_size_detected == 0) { au8_DRAMSize[u8_row] = ((uint8_t)e_16MB); /* FIXME: Not sure if this is really needed */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, au8_DRAMSize[u8_row]); } break; } default : { /* Unknown DRAM size */ au8_DRAMSize[u8_row] = ((uint8_t)e_EMPTY); /* FIXME: Not sure if this is really needed */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, au8_DRAMSize[u8_row]); break; } } /* Quit if the size of the current row was detected or an error occured */ if((u8_size_detected != 0) || au8_DRAMSize[u8_row] == ((uint8_t)e_EMPTY)){ break; } } } static void ram_detection(const struct mem_controller* ctrl) { uint8_t u8_row = 0; uint8_t au8_DRAMSize[SIMM_SOCKETS]; uint8_t u8_DRAMType = 0; uint8_t u8_DRAMBoundary = 0; uint8_t u8_CacheControl = 0; uint8_t u8_CacheOff = 0; /* Turn off cache (L1 & L2) */ u8_CacheControl = pci_read_config8(ctrl->d0, ((uint8_t)e_CACHE_CONTROL)); u8_CacheOff = u8_CacheControl & (~(e_CC_FIRST_CACHE_ENABLE) & ~(e_CC_SECONDARY_CACHE_SIZE) & ~(e_CC_SECONDARY_CACHE_MISS)); pci_write_config8(ctrl->d0, ((uint8_t)e_CACHE_CONTROL), u8_CacheOff); /* Set size of DRAM to 0 for all rows */ for(u8_row = 0; u8_row < SIMM_SOCKETS; u8_row++) { au8_DRAMSize[u8_row] = 0; pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, au8_DRAMSize); } /* Detect RAM presence and type in all rows */ for(u8_row = 0; u8_row < SIMM_SOCKETS; u8_row++) { /* Start of DRAM type detection */ /* Initialize the current row */ initialize_row(ctrl, u8_row); /* Detect type of ram in the current row */ detect_type(ctrl, au8_DRAMSize, &u8_DRAMType, u8_row); /* Check if any DRAM was found in this row */ if(au8_DRAMSize[u8_row] == 0) { /* No DRAM found. Skip the rest. */ continue; } /* Detect column address type and the size of the current row */ detect_size(ctrl, au8_DRAMSize, u8_row); /* Clear all settings made for the current row */ clear_row(ctrl, u8_row); } /* Turn L1 and L2 caches back on */ pci_write_config8(ctrl->d0, ((uint8_t)e_CACHE_CONTROL), u8_CacheControl); /* Set the type of all detected DRAM rows */ pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_TYPE), u8_DRAMType); /* Set the DRAM row boundaries */ for(u8_row = 0; u8_row < SIMM_SOCKETS; u8_row++) { u8_DRAMBoundary += au8_DRAMSize[u8_row]; pci_write_config8(ctrl->d0, ((uint8_t)e_DRAM_ROW_BOUNDARY_BASE) + u8_row, u8_DRAMBoundary); } } /* * This file is part of the LinuxBIOS project. * * Copyright (C) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #ifndef RAMINIT_H #define RAMINIT_H #define SIMM_SOCKETS 5 #define SIMM_ROW_SIZE_MAX 32 #define SIMM_GRANULARITY 4 enum E_DRAM_SIZE { e_EMPTY = 0, e_4MB = 1, e_8MB = 2, e_16MB = 4, e_32MB = 8 }; enum E_REGISTERS { e_CACHE_CONTROL = 0x52, e_DRAM_CONTROL = 0x57, e_DRAM_ROW_BOUNDARY_BASE = 0x60, e_DRAM_ROW_TYPE = 0x68 }; enum E_CACHE_CONTROL_MASKS { e_CC_SECONDARY_CACHE_SIZE = 0xC0, e_CC_SRAM_TYPE = 0x30, e_CC_NA_DISABLE = 0x04, e_CC_SECONDARY_CACHE_MISS = 0x02, e_CC_FIRST_CACHE_ENABLE = 0x01 }; enum E_DRAM_CONTROL_MASKS { e_DRAMC_HOLE_ENABLE = 0xC0, e_DRAMC_EDO_DETECT = 0x08, e_DRAMC_HOST_BUS_FREQUENCY = 0x07 }; enum E_DRAM_ROW_BOUNDARY_MASKS { e_DRB_ROW_BOUNDARY = 0x2F }; enum E_DRAM_ROW_TYPE_MASKS { e_DRT_ROW_TYPE = 0x1F }; #define RCA_32MB_TYPES 2 #define RCA_16MB_TYPES 1 #define RCA_8MB_TYPES 1 #define RCA_4MB_TYPES 1 struct S_DRAMTechnology { uint8_t u8_RowAddress; uint8_t u8_ColumnAddress; }; /** * row x col - DRAM size * 12 x 10 - 32MB * 11 x 11 - 32MB */ static struct S_DRAMTechnology s_DRAMT32MB[] = { {24, 22}, {23, 24} }; /** * row x col - DRAM size * 11 x 10 - 16MB */ struct S_DRAMTechnology s_DRAMT16MB[] = { {23, 22} }; /** * row x col - DRAM size * 10 x 10 - 8MB */ struct S_DRAMTechnology s_DRAMT8MB[] = { {21, 22} }; /** * row x col - DRAM size * 10 x 9 - 4MB */ struct S_DRAMTechnology s_DRAMT4MB[] = { {21, 11} }; struct mem_controller { device_t d0; uint16_t channel0[SIMM_SOCKETS]; }; #endif /* RAMINIT_H */

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Re: [LinuxBIOS] ICH4 BIOS chip not recognised.
by Dieter Bloms 11 Aug '07

11 Aug '07

Hi, On Sun, Aug 05, Raúl Sánchez Siles wrote: > I'm sorry but I've been unable to get that info from the Dell flash > utility. When loaded it's no chance to get any info like that. The only > option I'm given is to reflash the BIOS again. > > I would be glad to test any other tool/method you propose to get the info. I use uniflash from: http://www.uniflash.org/ it tells you that info. -- Gruß Dieter -- I do not get viruses because I do not use MS software. If you use Outlook then please do not put my email address in your address-book so that WHEN you get a virus it won't use my address in the From field.

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[LinuxBIOS] dump spd??
by Joseph Smith 11 Aug '07

11 Aug '07

Isn't there a function to dump the spd data? Thanks - Joe

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[LinuxBIOS] strange build error
by Joseph Smith 10 Aug '07

10 Aug '07

Getting this strange build error of the latest v2 snapshot, any clues?? ------------------------------------------------- Configuring DIR /cpu/intel/microcode/Config.lb Trying to find END on line 188: > > ^ List of nearby tokens: (@5326) HEX_NUM = '6' (@5328) ON = 'on' (@5331) END = 'end' (@5374) END = 'end' (@5380) END = 'end' (@5386) CHIP = 'chip' (@5391) PATH = 'cpu/intel/socket_PGA370' (@5417) END = 'end' (@5422) END = 'end' (@5429) EOF = '' ===> ERROR: Could not parse file rca/rm4100/Config.lb:0 mainboard/rca/rm4100/Config.lb:0 ---------------------------------------------------------- Thanks - Joe

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[LinuxBIOS] r465 - LinuxBIOSv3/util/x86emu/include/x86emu
by svn＠openbios.org 10 Aug '07

10 Aug '07

Author: stepan Date: 2007-08-10 15:48:59 +0200 (Fri, 10 Aug 2007) New Revision: 465 Modified: LinuxBIOSv3/util/x86emu/include/x86emu/types.h Log: trivial: explicitly make signed types signed as ommiting the "signed" keyword might not do what we want. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/util/x86emu/include/x86emu/types.h =================================================================== --- LinuxBIOSv3/util/x86emu/include/x86emu/types.h 2007-07-23 23:18:41 UTC (rev 464) +++ LinuxBIOSv3/util/x86emu/include/x86emu/types.h 2007-08-10 13:48:59 UTC (rev 465) @@ -74,15 +74,15 @@ typedef unsigned long long u64; #endif -typedef char s8; -typedef short s16; -typedef int s32; +typedef signed char s8; +typedef signed short s16; +typedef signed int s32; #ifdef __HAS_LONG_LONG__ -typedef long long s64; +typedef signed long long s64; #endif -typedef unsigned int uint; -typedef int sint; +typedef unsigned int uint; +typedef signed int sint; typedef u16 X86EMU_pioAddr;

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[LinuxBIOS] LBv3 under Bochs
by Carl-Daniel Hailfinger 09 Aug '07

09 Aug '07

Hi, since Qemu can't boot Windows Vista reliably and Bochs can, I wondered whether Bochs can run LinuxBIOS v3. Patrick Georgi tried it and even got to the GRUB2 welcome screen, where it crashed with a triple fault. This is what Patrick wrote in IRC: > http://openbios.org/~oxygene/lbv3.bochs is the config I used (to be > started from lbv3's root directory) > it's configured to send serial0 to /dev/stdout > I get "Welcome to GRUB!" now, but then it crashes on a triple fault :) > http://pastebin.com/m749c3e36 bochs output Will we try to get LBv3 running in Bochs? Benefits would be: * One more soft hardware platform to test code with (although the emulated hardware is very similar to that of Qemu) * Bochs seems to support Vista and we may have success running Vista with LBv3 in Bochs Regards, Carl-Daniel

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[LinuxBIOS] KVM over IP, fully embedded in LinuxBIOS?
by Adam Talbot 09 Aug '07

09 Aug '07

An idea that I wanted to bounce around. KVM over IP, fully embedded in LinuxBIOS? In a production class server room, there are mainly two ways to gain video console on a server. Crash cart, or a KVM over IP solution. It has been proven that LinuxBIOS can do console over IP... How much of a stretch would it be to implant something like VNC server into LinuxBIOS? Just a crazy idea, what up/downs do you see? -Adam

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[LinuxBIOS] Install bios in Asus A6T.
by frederic＠placenet.org 09 Aug '07

09 Aug '07

i do not see anything in wiki. somebody has experience about: laptop Asus A6T. chipset : C51MV(C61)+MCP51 flashrom give: Calibrating delay loop... ok No LinuxBIOS table found. Enabling flash write on NVidia MCP51...OK Pm49FL004 found at physical address: 0xfff80000 Flash part is Pm49FL004 (512 KB) OK, only ENABLING flash write, but NOT FLASHING. lshw give: description: Notebook product: A6T vendor: ASUSTeK Computer INC. version: 1.0 serial: NB-XXXXXXXX width: 32 bits capabilities: smbios-2.4 dmi-2.4 configuration: boot=normal chassis=notebook uuid=00020003-0004-0005-0006-000700080009 *-core description: Motherboard product: A6T vendor: ASUSTeK Computer INC. physical id: 0 version: 1.00 serial: NB-0123456789 slot: To Be Filled By O.E.M. *-firmware description: BIOS vendor: American Megatrends Inc. physical id: 0 version: 080012 (08/09/2006) size: 64KB capacity: 448KB capabilities: isa pci pcmcia pnp apm upgrade shadowing escd cdboot bootselect socketedrom edd int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification *-cpu:0 description: CPU product: AMD Turion(tm) 64 X2 Mobile Technology TL-52 vendor: Advanced Micro Devices [AMD] physical id: 1 bus info: cpu@0 version: AMD Turion(tm) 64 X2 Mobile Technology TL-52 serial: To Be Filled By O.E.M. slot: CPU 1 size: 1600MHz capacity: 1600MHz width: 64 bits clock: 200MHz capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp x86-64 3dnowext 3dnow pni cx16 lahf_lm cmp_legacy svm cr8_legacy cpufreq *-cache:0 description: L1 cache physical id: 5 slot: L1-Cache size: 128KB capacity: 128KB capabilities: pipeline-burst internal varies data *-cache:1 description: L2 cache physical id: 6 slot: L2-Cache size: 1MB capacity: 1MB capabilities: pipeline-burst internal varies unified *-cache:2 DISABLED description: L3 cache physical id: 7 slot: L3-Cache capabilities: internal *-cpu:1 description: CPU product: (To Be Filled By O.E.M.) physical id: 8 bus info: cpu@1 serial: To Be Filled By O.E.M. slot: CPU 2 size: 1600MHz capacity: 2GHz capabilities: cpufreq *-cache:0 DISABLED description: L1 cache physical id: 9 slot: L1-Cache capabilities: internal *-cache:1 DISABLED description: L2 cache physical id: a slot: L2-Cache capabilities: internal *-cache:2 DISABLED description: L3 cache physical id: b slot: L3-Cache capabilities: internal *-memory:0 description: System Memory physical id: 2d slot: System board or motherboard size: 2GB *-bank:0 description: DIMM Synchronous 333 MHz (3.0 ns) product: PartNum0 vendor: Manufacturer0 physical id: 0 serial: SerNum0 slot: DIMM0 size: 1GB width: 64 bits clock: 333MHz (3.0ns) *-bank:1 description: DIMM Synchronous 333 MHz (3.0 ns) product: PartNum1 vendor: Manufacturer1 physical id: 1 serial: SerNum1 slot: DIMM1 size: 1GB width: 64 bits clock: 333MHz (3.0ns) *-memory:1 UNCLAIMED description: RAM memory product: C51 Host Bridge vendor: nVidia Corporation physical id: 2 bus info: pci@00:00.0 version: a2 width: 32 bits clock: 66MHz (15.2ns) capabilities: bus_master cap_list configuration: latency=0 *-memory:2 UNCLAIMED description: RAM memory product: C51 Memory Controller 0 vendor: nVidia Corporation physical id: 0.1 bus info: pci@00:00.1 version: a2 width: 32 bits clock: 66MHz (15.2ns) configuration: latency=0 *-memory:3 UNCLAIMED description: RAM memory product: C51 Memory Controller 1 vendor: nVidia Corporation physical id: 0.2 bus info: pci@00:00.2 version: a2 width: 32 bits clock: 66MHz (15.2ns) configuration: latency=0 *-memory:4 UNCLAIMED description: RAM memory product: C51 Memory Controller 5 vendor: nVidia Corporation physical id: 0.3 bus info: pci@00:00.3 version: a2 width: 32 bits clock: 66MHz (15.2ns) configuration: latency=0 *-memory:5 UNCLAIMED description: RAM memory product: C51 Memory Controller 4 vendor: nVidia Corporation physical id: 0.4 bus info: pci@00:00.4 version: a2 width: 32 bits clock: 66MHz (15.2ns) capabilities: bus_master configuration: latency=0 *-memory:6 UNCLAIMED description: RAM memory product: C51 Host Bridge vendor: nVidia Corporation physical id: 0.5 bus info: pci@00:00.5 version: a2 width: 32 bits clock: 66MHz (15.2ns) capabilities: bus_master cap_list configuration: latency=0 *-memory:7 UNCLAIMED description: RAM memory product: C51 Memory Controller 3 vendor: nVidia Corporation physical id: 0.6 bus info: pci@00:00.6 version: a2 width: 32 bits clock: 66MHz (15.2ns) configuration: latency=0 *-memory:8 UNCLAIMED description: RAM memory product: C51 Memory Controller 2 vendor: nVidia Corporation physical id: 0.7 bus info: pci@00:00.7 version: a2 width: 32 bits clock: 66MHz (15.2ns) configuration: latency=0 *-pci:0 description: PCI bridge product: C51 PCI Express Bridge vendor: nVidia Corporation physical id: 3 bus info: pci@00:03.0 version: a1 width: 32 bits clock: 33MHz capabilities: pci normal_decode bus_master cap_list configuration: driver=pcieport-driver *-network description: Ethernet interface product: RTL8111/8168B PCI Express Gigabit Ethernet controller vendor: Realtek Semiconductor Co., Ltd. physical id: 0 bus info: pci@01:00.0 logical name: eth0 version: 01 serial: 00:18:f3:XX:XX:XX size: 1GB/s capacity: 1GB/s width: 64 bits clock: 33MHz capabilities: bus_master cap_list ethernet physical tp 10bt 10bt-fd 100bt 100bt-fd 1000bt-fd autonegotiation configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=2.2LK duplex=full ip=XX.XX.1.199 latency=0 link=yes multicast=yes port=twisted pair speed=1GB/s resources: ioport:c800-c8ff iomemory:dcfff000-dcffffff irq:11 *-pci:1 description: PCI bridge product: C51 PCI Express Bridge vendor: nVidia Corporation physical id: 100 bus info: pci@00:04.0 version: a1 width: 32 bits clock: 33MHz capabilities: pci normal_decode bus_master cap_list configuration: driver=pcieport-driver *-display description: VGA compatible controller product: G70 [GeForce Go 7600] vendor: nVidia Corporation physical id: 0 bus info: pci@02:00.0 version: a1 size: 256MB width: 64 bits clock: 33MHz capabilities: vga bus_master cap_list configuration: driver=nvidia latency=0 resources: iomemory:de000000-deffffff iomemory:c0000000-cfffffff iomemory:dd000000-ddffffff ioport:dc00-dc7f irq:11 *-memory:9 UNCLAIMED description: RAM memory product: MCP51 Host Bridge vendor: nVidia Corporation physical id: 9 bus info: pci@00:09.0 version: a2 width: 32 bits clock: 66MHz (15.2ns) capabilities: bus_master cap_list configuration: latency=0 *-isa description: ISA bridge product: MCP51 LPC Bridge vendor: nVidia Corporation physical id: a bus info: pci@00:0a.0 version: a3 width: 32 bits clock: 66MHz capabilities: isa bus_master configuration: latency=0 *-serial description: SMBus product: MCP51 SMBus vendor: nVidia Corporation physical id: a.1 bus info: pci@00:0a.1 version: a3 width: 32 bits clock: 66MHz capabilities: cap_list configuration: driver=nForce2_smbus latency=0 resources: ioport:600-63f ioport:700-73f irq:5 *-processor UNCLAIMED description: Co-processor product: MCP51 PMU vendor: nVidia Corporation physical id: a.3 bus info: pci@00:0a.3 version: a3 width: 32 bits clock: 66MHz capabilities: bus_master configuration: latency=0 maxlatency=1 mingnt=3 resources: iomemory:dcec0000-dcefffff irq:10 *-usb:0 description: USB Controller product: MCP51 USB Controller vendor: nVidia Corporation physical id: b bus info: pci@00:0b.0 version: a3 width: 32 bits clock: 66MHz capabilities: ohci bus_master cap_list configuration: driver=ohci_hcd latency=0 maxlatency=1 mingnt=3 resources: iomemory:dcebe000-dcebefff irq:11 *-usbhost product: OHCI Host Controller vendor: Linux 2.6.20-16-generic ohci_hcd physical id: 1 bus info: usb@1 logical name: usb1 version: 2.06 capabilities: usb-1.10 configuration: driver=hub maxpower=0mA slots=8 speed=12.0MB/s *-usb:0 description: Mouse product: Optical USB Mouse vendor: Logitech physical id: 2 bus info: usb@1:2 version: 3.40 capabilities: usb-2.00 configuration: driver=usbhid maxpower=100mA speed=1.5MB/s *-usb:1 description: Bluetooth wireless interface physical id: 7 bus info: usb@1:7 version: 19.15 serial: 0194E8-5B-0002 capabilities: bluetooth usb-2.00 configuration: driver=hci_usb maxpower=0mA speed=12.0MB/s *-usb:1 description: USB Controller product: MCP51 USB Controller vendor: nVidia Corporation physical id: b.1 bus info: pci@00:0b.1 version: a3 width: 32 bits clock: 66MHz capabilities: ehci bus_master cap_list configuration: driver=ehci_hcd latency=0 maxlatency=1 mingnt=3 resources: iomemory:dcebfc00-dcebfcff irq:7 *-usbhost product: EHCI Host Controller vendor: Linux 2.6.20-16-generic ehci_hcd physical id: 1 bus info: usb@2 logical name: usb2 version: 2.06 capabilities: usb-2.00 configuration: driver=hub maxpower=0mA slots=8 speed=480.0MB/s *-usb UNCLAIMED description: Generic USB device product: USB2.0 vendor: Syntek physical id: 5 bus info: usb@2:5 version: 0.05 capabilities: usb-2.00 configuration: maxpower=500mA speed=480.0MB/s *-ide description: IDE interface product: MCP51 IDE vendor: nVidia Corporation physical id: d bus info: pci@00:0d.0 version: a1 width: 32 bits clock: 66MHz capabilities: ide bus_master cap_list configuration: driver=AMD_IDE latency=0 maxlatency=1 mingnt=3 resources: iomemory:1f0-1f7 iomemory:3f0-3ef iomemory:170-177 iomemory:370-36f ioport:ffa0-ffaf *-ide:0 description: IDE Channel 0 physical id: 0 bus info: ide@0 logical name: ide0 clock: 66MHz *-cdrom description: DVD-RAM writer product: HL-DT-ST DVDRAM GSA-T10N physical id: 0 bus info: ide(a)0.0 logical name: /dev/hda version: PR03 serial: K0F697A2022 capabilities: packet atapi cdrom removable nonmagnetic dma lba iordy pm audio cd-r cd-rw dvd dvd-r dvd-ram configuration: mode=udma2 *-disc physical id: 0 logical name: /dev/hda *-ide:1 description: IDE Channel 1 physical id: 1 bus info: ide@1 logical name: ide1 clock: 66MHz *-disk description: ATA Disk product: Hitachi HTS541212H9AT00 vendor: Hitachi physical id: 0 bus info: ide(a)1.0 logical name: /dev/hdc version: HP4OA23C serial: HP0400BEG0P32A size: 111GB capacity: 111GB capabilities: ata dma lba iordy smart security pm apm partitioned partitioned:dos configuration: apm=off mode=udma5 smart=on *-volume:0 description: Linux filesystem partition physical id: 1 bus info: ide(a)1.0,1 logical name: /dev/hdc1 capacity: 486MB capabilities: primary bootable *-volume:1 description: Linux swap / Solaris partition physical id: 2 bus info: ide(a)1.0,2 logical name: /dev/hdc2 capacity: 3812MB capabilities: primary nofs *-volume:2 description: Linux filesystem partition physical id: 3 bus info: ide(a)1.0,3 logical name: /dev/hdc3 capacity: 14GB capabilities: primary *-volume:3 description: Extended partition physical id: 4 bus info: ide(a)1.0,4 logical name: /dev/hdc4 size: 93GB capacity: 93GB capabilities: primary extended partitioned partitioned:extended *-logicalvolume:0 description: Linux filesystem partition physical id: 5 logical name: /dev/hdc5 capacity: 37GB *-logicalvolume:1 description: Linux filesystem partition physical id: 6 logical name: /dev/hdc6 capacity: 54GB *-logicalvolume:2 description: Linux filesystem partition physical id: 7 logical name: /dev/hdc7 capacity: 1937MB *-pci:2 description: PCI bridge product: MCP51 PCI Bridge vendor: nVidia Corporation physical id: 10 bus info: pci@00:10.0 version: a2 width: 32 bits clock: 66MHz capabilities: pci subtractive_decode bus_master cap_list *-pcmcia description: CardBus bridge product: RL5c476 II vendor: Ricoh Co Ltd physical id: 1 bus info: pci@03:01.0 version: b3 width: 64 bits clock: 33MHz capabilities: pcmcia bus_master cap_list configuration: driver=yenta_cardbus latency=176 maxlatency=5 mingnt=131 resources: iomemory:df800000-df800fff iomemory:b00704030-b0070402f irq:11 *-firewire description: FireWire (IEEE 1394) product: R5C552 IEEE 1394 Controller vendor: Ricoh Co Ltd physical id: 1.1 bus info: pci@03:01.1 version: 08 width: 32 bits clock: 33MHz capabilities: ohci bus_master cap_list configuration: driver=ohci1394 latency=64 maxlatency=4 mingnt=2 resources: iomemory:df7ff000-df7ff7ff irq:5 *-system:0 description: Generic system peripheral product: R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter vendor: Ricoh Co Ltd physical id: 1.2 bus info: pci@03:01.2 version: 17 width: 32 bits clock: 33MHz capabilities: bus_master cap_list configuration: driver=sdhci latency=64 resources: iomemory:df7ff800-df7ff8ff irq:5 *-system:1 UNCLAIMED description: System peripheral product: R5C592 Memory Stick Bus Host Adapter vendor: Ricoh Co Ltd physical id: 1.3 bus info: pci@03:01.3 version: 08 width: 32 bits clock: 33MHz capabilities: cap_list configuration: latency=0 resources: iomemory:df7ffc00-df7ffcff irq:5 *-network description: Wireless interface product: BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller vendor: Broadcom Corporation physical id: 3 bus info: pci@03:03.0 logical name: eth1 version: 02 serial: 00:18:f3:ab:e7:42 width: 32 bits clock: 33MHz capabilities: bus_master ethernet physical wireless configuration: broadcast=yes driver=bcm43xx driverversion=2.6.20-16-generic latency=64 link=no multicast=yes wireless=IEEE 802.11b/g resources: iomemory:df7fc000-df7fdfff irq:11 *-multimedia description: Audio device product: MCP51 High Definition Audio vendor: nVidia Corporation physical id: 10.1 bus info: pci@00:10.1 version: a2 width: 32 bits clock: 66MHz capabilities: bus_master cap_list configuration: driver=HDA Intel latency=0 maxlatency=5 mingnt=2 resources: iomemory:dceb8000-dcebbfff irq:10 *-pci:3 description: Host bridge product: K8 [Athlon64/Opteron] HyperTransport Technology Configuration vendor: Advanced Micro Devices [AMD] physical id: 101 bus info: pci@00:18.0 version: 00 width: 32 bits clock: 33MHz *-pci:4 description: Host bridge product: K8 [Athlon64/Opteron] Address Map vendor: Advanced Micro Devices [AMD] physical id: 102 bus info: pci@00:18.1 version: 00 width: 32 bits clock: 33MHz *-pci:5 description: Host bridge product: K8 [Athlon64/Opteron] DRAM Controller vendor: Advanced Micro Devices [AMD] physical id: 103 bus info: pci@00:18.2 version: 00 width: 32 bits clock: 33MHz *-pci:6 description: Host bridge product: K8 [Athlon64/Opteron] Miscellaneous Control vendor: Advanced Micro Devices [AMD] physical id: 104 bus info: pci@00:18.3 version: 00 width: 32 bits clock: 33MHz bst regards. Frederic

2 1

[LinuxBIOS] Help Debugging Windows VISTA - GSoC
by Augusto Pedroza 09 Aug '07

09 Aug '07

<#>Hi guys, I have tried in the last few days to debug windows VISTA installation process in different ways. All my tests have been doing using qemu. At first I tried to debug windows vista using WinGdb, but it seems to work only when windows is already installed since it requires some modifications in the boot.ini file. So was unable to connect wingdb to qemu through a pipe. My second option was to try to use windows debug mode when pressing F8 during the beginning of the installation process but the only info I found was this: Debugging Mode: This option turns on debug mode in Windows. Debugging information can be sent across a serial cable to another computer that is running a debugger. This mode is configured to use COM2. Does anyone knows how to capture COM2 output when using qemu? Maybe using a real hardware makes it easier since I can use a different computer connected to the guest through a NULL cable. Since I have gotten some random results when using qemu with its original bios, I have been unable to install windows vista on a hard disk image. Yesterday i almost got it but i created a image file too small, Vista requires at least 6Gb. I guess if I get that i'll be able to use wingdb more easily. Thanks, -- Augusto Pedroza

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coreboot August 2007