coreboot May 2007

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[LinuxBIOS] [PATCH] i82371eb: Make all BIOS/ROM areas accessible (or: 440BX boots FILO)
by Uwe Hermann 27 May '07

27 May '07

See patch. This was the last missing piece to make the 440BX work so far that it boots a payload. I have successfully booted into FILO and memtest with this patch on my Tyan S1846. Also, a full memtest run worked just fine, so RAM init is ok (but still hardcoded to the S1846 for now). Bootlog and patch are attached. I'm now working on the southbridge code, PCI and IDE init are almost done, expect a patch soon. This should make booting a kernel possible... Other entries on the 440BX TODO list are: - Make RAM init generic, not hardcoded to the S1846 - Fix up all kinds of stupid hacks and bugs in the code - Implement all of the i82371eb southbridge features - Fix up Tyan S1846 and ASUS P2B so they actually work - This is going to be quite some work, think PIRQ tables and whatnot - Port all 440BX boards to Cache as RAM - Port lots of other 440BX boards Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2700 - trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb
by svn＠openbios.org 27 May '07

27 May '07

Author: uwe Date: 2007-05-27 23:43:58 +0200 (Sun, 27 May 2007) New Revision: 2700 Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h Log: Init for the Intel 82371EB southbridge: make all ROM/BIOS regions accessible (but not writable), so that reading/loading a payload from that area can work (for instance). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c 2007-05-26 13:56:34 UTC (rev 2699) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c 2007-05-27 21:43:58 UTC (rev 2700) @@ -18,12 +18,42 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* Datasheet: + * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) + * - URL: http://www.intel.com/design/intarch/datashts/290562.htm + * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf + * - Order Number: 290562-001 + */ + +#include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include "i82371eb.h" +/** + * Enable access to all BIOS regions. Do not enable write access to the ROM. + * + * @param dev TODO + */ void i82371eb_enable(device_t dev) { - /* TODO. */ + uint16_t reg; + + /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to + * FFF00000-FFF7FFFF are forwarded to ISA). + * Set bit 7: Extended BIOS Enable (PCI master accesses to + * FFF80000-FFFDFFFF are forwarded to ISA). + * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to + * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top + * of 1 Mbyte, or the aliases at the top of 4 Gbyte + * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. + * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. + * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). + */ + + reg = pci_read_config16(dev, XBCS); + reg |= 0x2c0; + pci_write_config16(dev, XBCS, reg); } struct chip_operations southbridge_intel_i82371eb_ops = { Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-05-26 13:56:34 UTC (rev 2699) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-05-27 21:43:58 UTC (rev 2700) @@ -25,6 +25,8 @@ #include "chip.h" +#define XBCS 0x4e /* X-Bus Chip Select register */ + void i82371eb_enable(device_t dev); #endif

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[LinuxBIOS] Epia V
by Markus Boas 27 May '07

27 May '07

Hi I have littel trouble with this mainboard. First: Is this normal? <shnip> Capability: 0x10 @ 0x80 PCI: 00:01.0 [1106/8601] enabled PCI: devfn 0x10, bad id 0xffffffff PCI: devfn 0x18, bad id 0xffffffff PCI: devfn 0x20, bad id 0xffffffff PCI: devfn 0x28, bad id 0xffffffff PCI: devfn 0x30, bad id 0xffffffff PCI: devfn 0x38, bad id 0xffffffff PCI: devfn 0x40, bad id 0xffffffff PCI: devfn 0x48, bad id 0xffffffff PCI: devfn 0x50, bad id 0xffffffff PCI: devfn 0x58, bad id 0xffffffff PCI: devfn 0x60, bad id 0xffffffff PCI: devfn 0x68, bad id 0xffffffff PCI: devfn 0x70, bad id 0xffffffff PCI: devfn 0x78, bad id 0xffffffff PCI: devfn 0x80, bad id 0xffffffff PCI: 00:11.0 [1106/8231] bus ops PCI: 00:11.0 [1106/8231] enabled PCI: 00:11.1 [1106/0571] ops PCI: 00:11.1 [1106/0571] enabled PCI: 00:11.2 [1106/3038] disabled PCI: 00:11.3 [1106/3038] disabled PCI: 00:11.4 [1106/8235] ops <snap> I'm worry about the bad id. Second: I used etherboot as payload, but it didn't came up. The last output from the serial communcation: <shnip> LinuxBIOS-2.0.0.0Fallback Sun May 27 20:19:19 UTC 2007 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM <snap> On screen runs a defect ascii-output throu Markus

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[LinuxBIOS] [PATCH] Add Intel i810, i82801aa (ICH) and Asus MEW-VM support
by Corey Osgood 27 May '07

27 May '07

See attached patch. There's still some work to be done on this, but my laptop's out of commission for a week or so, so I figure I'll let anyone who's bored do some hacking. As is, it does boot a payload, and probably would do a kernel with either acpi or irq tables, but should be considered a WIP. Feedback and comments are appreciated! Also, the i82801aa is almost completely copy and pasted from the i82801ca, with the device IDs swapped over (bad practice, I know, but if ain't broke don't fix it). I haven't updated any of the license headers to be GPLv2 ones, mainly because I don't want to make a bad assumption. Not quite sure what to do with them... -Corey

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Re: [LinuxBIOS] new Target ASUS A8NE
by Philipp Degler 27 May '07

27 May '07

On Saturday 19 May 2007 19:17:18 Uwe Hermann wrote: > On Sat, May 19, 2007 at 09:55:03AM -0700, yhlu wrote: > > > > > + /* Initialize interrupt mapping */ > > > > > + //dword = 0x0000d218; > > > > > + dword = 0x01200000; //a8ne > > > > > + pci_write_config32(dev, 0x7c, dword); > > > > > + > > > > > + //dword = 0x12008a00; > > > > > + dword = 0x12008009; //a8ne > > > > > + pci_write_config32(dev, 0x80, dword); > > > > > + > > > > > + //dword = 0x0000007d; > > > > > + dword = 0x0002010d; //a8ne > > > > > + pci_write_config32(dev, 0x84, dword); > > > > > > > > What are the commented values? Not for the A8N-E? Then we should > > > > probably drop them. > > > > > > yes they are a remainder of s2891 :). i will drop them. > > > > No, you can not. try to see what happen. > > Ah, I meant the comments only: > > > > > + //dword = 0x0000d218; > > > > > + //dword = 0x12008a00; > > > > > + //dword = 0x0000007d; > > The other code must remain, of course. modified code as proposed by uwe, see patch changes were tested on hardware and with abuild. (see attached lspci for further info of the hardware that was used for the tests) Did send other 2 patches separately as proposed. Signed-off-by: Philipp Degler <pdegler(a)rumms.uni-mannheim.de> --- phil

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[LinuxBIOS] LinuxTag Berlin 29/5-2/6
by Peter Stuge 27 May '07

27 May '07

Just a quick note to confirm that LinuxBIOS will be present at the LinuxTag expo next week. We'll show some systems with LB and we're doing an EPIA/-M/-MII workshop on Saturday 2/6 for people who want to get started using LinuxBIOS quickly. Bring your board! :) I've put a news item up on the wiki and added a separate page for the workshop details. //Peter

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[LinuxBIOS] Wiki license tags
by Uwe Hermann 27 May '07

27 May '07

Hi, could everyone who submitted stuff into the wiki please tag it with a license (preferrably something free-ish, otherwise we'll probably have to drop the content ;-) This should be done for all texts (mostly the port guides and tutorials), all images and photos, and all other PDFs, DOCs and whatnot... I've added templates for the following licenses. You can use them in the wiki simply by writing (e.g.) {{GPL}} and saving the page. If you need more/other licenses, please let us know, we can add more templates. For now we have: - {{GPL}} -- GPLv2 or later - {{GPLv2}} -- GPLv2 - {{Cc-by-2.5}} -- Creative Commons Attribution 2.5 - {{Cc-by-sa-2.5}} -- Creative Commons Attribution ShareAlike 2.5 - {{Cc-by-sa-3.0}} -- Creative Commons Attribution ShareAlike 3.0 - {{{PD-self}} -- Stuff you created and released into the public domain Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] ASUS A8N-SLI Premium (K8, CK804, IT8712)
by David M Barr 26 May '07

26 May '07

Hi, Attached are dmidecode and lspci -t/n/v output for my system, which has the same MB as Adrian's. Since he has the tools, can anyone provide tips on how to get started? Regards, David M. Barr On 19/03/2007 12:06:43 am, Adrian-Ken Rueegsegger wrote: Hi David, Thanks for the info! I did find out that all chipsets are supported. I bought myself a Bios saviour and I have all the other hardware one needs. I just had little time playing around with it the last two weeks but I want to start looking into it again, that's why I wanted to ask if you had made some progress. I am not quite sure where to start but I found a motherboard [1] that is quite "similar" to ours: Sun Ultra40. It has the same North- and Southbridge; SuperIO is different though. Would you know where to go from here? Cheers, Adrian

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[LinuxBIOS] r2699 build service
by LinuxBIOS information 26 May '07

26 May '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2699 to the LinuxBIOS source repository and caused the following changes: Change Log: This patch fixes the processor name string for Rev F. CPUs. It moves the complete naming functionality to src/cpu/amd/model_fxx/processor_name.c. The current code sets the processor name string twice for Rev. F CPUs. In src/cpu/amd/model_fxx/model_fxx_init.c the function amd_set_name_string_f is called first. Several lines later init_processor_name is called which doesn't recognize newer CPUs and actually programs incorrect values, thus overwriting the previously set CPU name. For example, this resulted in identifying an Opteron 2218 as a Turion processor. This patch removes the amd_set_name_string_f function from src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs to src/cpu/amd/model_fxx/processor_name.c as described in the Revision Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00, October 2006. Signed-off-by: Sven Kapferer <skapfere(a)rumms.uni-mannheim.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2699&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2699&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2699&device=e326&vendor=i… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2699&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2699&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] [Patch] Fix processor name string for Rev. F CPUs
by Sven Kapferer 26 May '07

26 May '07

This patch fixes the processor name string for Rev F. CPUs. It moves the complete naming functionality to src/cpu/amd/model_fxx/processor_name.c Signed-off-by: Sven Kapferer <skapfere(a)rumms.uni-mannheim.de> --- The current code sets the processor name string twice for Rev. F CPUs. In src/cpu/amd/model_fxx/model_fxx_init.c the function amd_set_name_string_f is called first. Several lines later init_processor_name is called which doesn't recognize newer CPUs and actually programs incorrect values, thus overwriting the previously set CPU name. For example, this resulted in identifying an Opteron 2218 as a Turion processor. This patch removes the amd_set_name_string_f function from src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs to src/cpu/amd/model_fxx/processor_name.c as described in the Revision Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00, October 2006. Regards, - Sven -- Sven Kapferer University of Mannheim - Computer Architecture Group Address : B6 26, 68131 Mannheim, Germany Web : http://ra.ti.uni-mannheim.de Email : skapfere(a)rumms.uni-mannheim.de Phone : +49 621 181 2720 Fax: +49 621 181 2713 Index: src/cpu/amd/model_fxx/processor_name.c =================================================================== --- src/cpu/amd/model_fxx/processor_name.c (revision 2627) +++ src/cpu/amd/model_fxx/processor_name.c (working copy) @@ -9,6 +9,10 @@ * * (C) 2006 by coresystems GmbH <info(a)coresystems.de> * + * Updated by Sven Kapferer <skapfere(a)rumms.uni-mannheim.de> using + * the Revision Guide for AMD NPT Family 0Fh Processors + * Document ID 33610 Rev 3.00, October 2006 (Public Version) + * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this * archive for more details. @@ -25,6 +29,7 @@ * your mainboard will not be posted on the AMD Recommended Motherboard Website */ +#if K8_REV_F_SUPPORT == 0 static char *processor_names[]={ /* 0x00 */ "AMD Engineering Sample", /* 0x01-0x03 */ NULL, NULL, NULL, @@ -80,6 +85,7 @@ /* 0x3A */ "Dual Core AMD Opteron(tm) Processor 8RR" #define MAX_CPU_NUMBER 0x3A }; +#endif /* wrmsr_amd() is from yhlu's changes to model_fxx_init.c */ @@ -92,6 +98,17 @@ ); } +static inline unsigned int cpuid_eax(unsigned int op) +{ + unsigned int eax; + + __asm__("cpuid" + : "=a" (eax) + : "0" (op) + : "ebx", "ecx", "edx"); + return eax; +} + static inline unsigned int cpuid_ebx(unsigned int op) { unsigned int eax, ebx; @@ -103,6 +120,17 @@ return ebx; } +static inline unsigned int cpuid_ecx(unsigned int op) +{ + unsigned int eax, ecx; + + __asm__("cpuid" + : "=a" (eax), "=c" (ecx) + : "0" (op) + : "ebx", "edx" ); + return ecx; +} + static inline void strcpy(char *dst, char *src) { while (*src) *dst++ = *src++; @@ -123,6 +151,7 @@ char program_string[48]; unsigned int *program_values = (unsigned int *)program_string; +#if K8_REV_F_SUPPORT == 0 /* Find out which CPU brand it is */ EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; @@ -144,7 +173,104 @@ if (!processor_name_string) processor_name_string = "AMD Processor model unknown"; +#endif +#if K8_REV_F_SUPPORT == 1 + u32 Socket; + u32 CmpCap; + u32 PwrLmt; + + BrandId = cpuid_ebx(0x80000001) & 0xffff; + Socket = (cpuid_eax(0x80000001) & 0x00000030) >> 4; // 00b = S1g1, 01b = F (1207), 11b = AM2 + CmpCap = cpuid_ecx(0x80000008) & 0x03; // Number of CPU cores + + PwrLmt = ((BrandId >> 14) & 0x01) | ((BrandId >> 5) & 0x0e); // BrandId[8:6,14] + BrandTableIndex = (BrandId >> 9) & 0x1f; // BrandId[13:9] + NN = ((BrandId >> 15) & 0x01) | (BrandId & 0x3f); // BrandId[15,5:0] + + if (((BrandTableIndex == 0) && (PwrLmt == 0)) || (NN == 0)) { + processor_name_string = "AMD Engineering Sample"; + } else { + /* Use all fields to identify CPU */ + switch ((Socket << 16) | (CmpCap << 12) | (BrandTableIndex << 4) + | PwrLmt) { + /* Socket F */ + case 0x11016: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 22RR HE"; + break; + case 0x1101a: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 22RR"; + break; + case 0x1101c: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 22RR SE"; + break; + case 0x11046: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 82RR HE"; + break; + case 0x1104a: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 82RR"; + break; + case 0x1104c: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 82RR SE"; + break; + /* Socket AM2 */ + case 0x30044: + processor_name_string = + "AMD Athlon(tm) 64 Processor TT00+"; + break; + case 0x30048: + processor_name_string = + "AMD Athlon(tm) 64 Processor TT00+"; + break; + case 0x30064: + processor_name_string = + "AMD Sempron(tm) Processor TT00+"; + break; + case 0x30068: + processor_name_string = + "AMD Sempron(tm) Processor TT00+"; + break; + case 0x3101a: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 12RR"; + break; + case 0x3101c: + processor_name_string = + "Dual-Core AMD Opteron(tm) Processor 12RR SE"; + break; + case 0x31042: + processor_name_string = + "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; + break; + case 0x31046: + processor_name_string = + "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; + break; + case 0x31048: + processor_name_string = + "AMD Athlon(tm) 64 X2 Dual Core Processor TT00+"; + break; + case 0x3105c: + processor_name_string = + "AMD Athlon(tm) 64 FX-ZZ Dual Core Processor"; + break; + /* Socket S1g1 */ + case 0x0102c: + processor_name_string = + "AMD Turion(tm) 64 X2 Mobile Technology TL-YY"; + break; + default: + processor_name_string = "AMD Processor model unknown"; + } + } +#endif + memset(program_string, 0, 48); strcpy(program_string, processor_name_string); @@ -156,12 +282,22 @@ for (i=0; i<47; i++) { // 48 -1 if(program_string[i] == program_string[i+1]) { switch (program_string[i]) { +#if K8_REV_F_SUPPORT == 0 case 'X': ModelNumber = 22+ NN; break; case 'Y': ModelNumber = 38 + (2*NN); break; case 'Z': case 'T': ModelNumber = 24 + NN; break; case 'R': ModelNumber = 45 + (5*NN); break; case 'V': ModelNumber = 9 + NN; break; +#endif + +#if K8_REV_F_SUPPORT == 1 + case 'R': ModelNumber = NN - 1; break; + case 'P': ModelNumber = 26 + NN; break; + case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break; + case 'Z': ModelNumber = 57 + NN; break; + case 'Y': ModelNumber = 29 + NN; break; +#endif } if(ModelNumber && ModelNumber < 100) { Index: src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- src/cpu/amd/model_fxx/model_fxx_init.c (revision 2627) +++ src/cpu/amd/model_fxx/model_fxx_init.c (working copy) @@ -462,87 +462,6 @@ } -#if K8_REV_F_SUPPORT == 1 -static void amd_set_name_string_f(device_t dev) -{ - unsigned socket; - unsigned cmpCap; - unsigned pwrLmt; - unsigned brandId; - unsigned brandTableIndex; - unsigned nN; - unsigned unknown = 1; - - uint8_t str[48]; - uint32_t *p; - - msr_t msr; - unsigned i; - - brandId = cpuid_ebx(0x80000001) & 0xffff; - - printk_debug("brandId=%04x\n", brandId); - pwrLmt = ((brandId>>14) & 1) | ((brandId>>5) & 0x0e); - brandTableIndex = (brandId>>9) & 0x1f; - nN = (brandId & 0x3f) | ((brandId>>(15-6)) &(1<<6)); - - socket = (dev->device >> 4) & 0x3; - - cmpCap = cpuid_ecx(0x80000008) & 0xff; - - - if((brandTableIndex == 0) && (pwrLmt == 0)) { - memset(str, 0, 48); - sprintf(str, "AMD Engineering Sample"); - unknown = 0; - } else { - - memset(str, 0, 48); - sprintf(str, "AMD Processor model unknown"); - - #if CPU_SOCKET_TYPE == 0x10 - if(socket == 0x01) { // socket F - if ((cmpCap == 1) && ((brandTableIndex==0) ||(brandTableIndex ==1) ||(brandTableIndex == 4)) ) { - uint8_t pc[2]; - unknown = 0; - switch (pwrLmt) { - case 2: pc[0]= 'E'; pc[1] = 'E'; break; - case 6: pc[0]= 'H'; pc[1] = 'E'; break; - case 0xa: pc[0]= ' '; pc[1] = ' '; break; - case 0xc: pc[0]= 'S'; pc[1] = 'E'; break; - default: unknown = 1; - - } - if(!unknown) { - memset(str, 0, 48); - sprintf(str, "Dual-Core AMD Opteron(tm) Processor %1d2%2d %c%c", brandTableIndex<<1, (nN-1)&0x3f, pc[0], pc[1]); - } - } - } - #else - #if CPU_SOCKET_TYPE == 0x11 - if(socket == 0x00) { // socket AM2 - if(cmpCap == 0) { - sprintf(str, "Athlon 64"); - } else { - sprintf(str, "Athlon 64 Dual Core"); - } - - } - #endif - #endif - } - - p = str; - for(i=0;i<6;i++) { - msr.lo = *p; p++; msr.hi = *p; p++; - wrmsr(0xc0010030+i, msr); - } - - -} -#endif - extern void model_fxx_update_microcode(unsigned cpu_deviceid); int init_processor_name(void); @@ -561,10 +480,6 @@ struct cpuinfo_x86 c; get_fms(&c, dev->device); - - if((c.x86_model & 0xf0) == 0x40) { - amd_set_name_string_f(dev); - } #endif #if CONFIG_USBDEBUG_DIRECT

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coreboot May 2007