coreboot May 2007

coreboot@coreboot.org

98 participants
436 discussions

[LinuxBIOS] Setup CAR on Geode GX1 processor
by Juergen Beisert 28 May '07

28 May '07

Hi, find below my CAR implementation for the Geode GX1 processor. Tested on my Geode GX1 system. Comments are welcome. Juergen /* * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /** * This function pins the cache to a fixed address, to be used as an SRAM * until system memory is available. It will be done with the help of the * cache debug and test registers tr3, tr4 and tr5 * * Your hardware must fulfil these qualifications: * - support of the tr3, tr4 and tr5 registers * - size of one cache line must be 16 bytes * - your CAR area must be pinned to an address space where it * also would work in a regular way (do not pin it to an I/O space) * * Mapping of the cache happens from _sstage0_1 as startaddress up to * (_sstage0_1 + _car_size) as endaddress * * Note: This function uses some symbols created by the linker withing the * linker script file. This ensures future compatibility and keeps all layout * configuring into the linker script file. * * _sstage0_1: * contains the physical start address of the CAR area * _car_size: * size of the whole CAR area (in bytes) -> means cache size */ .code32 .section ".bright_side", "ax" .extern pre_c_stage .extern _sstage0_1 .extern _car_size .globl CacheAsRam CacheAsRam: /* Save the BIST value */ movl %eax, %ebp movl $_sstage0_1, %edi movl $_car_size, %ecx next_cache_line: movl $0xdeadbeef, %eax /* value for each byte in the CAR */ /* Fill up cache fill buffer (one cache line = 16 bytes) */ xorl %ebx, %ebx /* entry 0 */ movl %ebx, %tr5 movl %eax, %tr3 /* value for entry 0 */ addl $0x04, %ebx /* entry 1 (at offset 4) */ movl %ebx, %tr5 movl %eax, %tr3 /* value for entry 1 */ addl $0x04, %ebx /* entry 2 (at offset 8) */ movl %ebx, %tr5 movl %eax, %tr3 /* value for entry 2 */ addl $0x04, %ebx /* entry 3 (at offset 12) */ movl %ebx, %tr5 movl %eax, %tr3 /* value for entry 3 */ /* pin this cache line to a fixed address */ movl %edi, %eax andl $0xFFFFF000, %eax /* upper 20 bit of the physical address */ orl $0x00000400, %eax /* mark this entry valid */ movl %eax, %tr4 /* setup correct cache set and cache line */ movl %edi, %eax andl $0x00000FF0, %eax /* calculate cache line from physical address bit [11:4] */ movl %edi, %ebx andl $0x00003000, %ebx /* calculate cache set from physical address bit [13:12] */ shrl $0xA, %ebx orl %ebx, %eax orl $0x01, %eax /* add write buffer command */ movl %eax, %tr5 /* do it */ /* loop until full cache is mapped */ addl $0x10, %edi subl $0x10, %ecx jnz next_cache_line /* Restore the BIST value to %eax */ movl %ebp, %eax /* prepare to run C code */ jmp pre_c_stage

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[LinuxBIOS] EPIA CL
by Markus Boas 28 May '07

28 May '07

So I testet a Epia CL with the Epia M file, as payload etherboot. Output: 0 LinuxBIOS-2.0.0.0-Fallback Mon May 28 08:12:52 UTC 2007 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting <nothing more> The interessting thing is that the Flashrom tool dedectet a Epia M/MII Board

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[LinuxBIOS] Anybody working on a CK804 / MCP55 board?
by Uwe Hermann 28 May '07

28 May '07

Hi, there's been lots of talk about support for a modern and/or cheap desktop board in the past. I think our best bet at the moment is to support many K8+CK804 and K8+MCP55 boards. Is anybody out there already (or still) working on such a mainboard at the moment? Any preliminary patches? I'm thinking about getting one such board, but I don't want to duplicate any work someone else might already have put into writing code... Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 6

[LinuxBIOS] tyan s3970
by Savchenko Mikhail 28 May '07

28 May '07

Hi, I need an asistants to made this board work with LinuxBios. Can anybody help?

2 1

[LinuxBIOS] r2702 - trunk/LinuxBIOSv2/src/northbridge/intel/i440bx
by svn＠openbios.org 28 May '07

28 May '07

Author: uwe Date: 2007-05-28 16:37:06 +0200 (Mon, 28 May 2007) New Revision: 2702 Modified: trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c Log: Lower the RAM init delays we use on the Intel 440BX. As per JEDEC, we should wait 200us until voltages and clocks are stable. Then apply NOPs for 200 clock cycles (for simplicity we use 200us here). All other delays are so low that we get away with just waiting 1us. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c 2007-05-27 23:31:31 UTC (rev 2701) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c 2007-05-28 14:37:06 UTC (rev 2702) @@ -509,44 +509,41 @@ { int i; - /* TODO: Use a delay here? Needed? */ - mdelay(200); + /* 0. Wait until power/voltages and clocks are stable (200us). */ + udelay(200); - /* TODO: How long should the delays be? Fix later. */ - - /* 1. Apply NOP. */ + /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); do_ram_command(ctrl, RAM_COMMAND_NOP, 0); - mdelay(10); + udelay(200); /* 2. Precharge all. Wait tRP. */ PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0); - mdelay(10); + udelay(1); /* 3. Perform 8 refresh cycles. Wait tRC each time. */ PRINT_DEBUG("RAM Enable 3: CBR\r\n"); for (i = 0; i < 8; i++) { do_ram_command(ctrl, RAM_COMMAND_CBR, 0); - mdelay(10); + udelay(1); } /* 4. Mode register set. Wait two memory cycles. */ PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0); - mdelay(10); - mdelay(10); + udelay(2); /* 5. Normal operation. */ PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0); - mdelay(10); + udelay(1); /* 6. Finally enable refresh. */ PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); // pci_write_config8(ctrl->d0, PMCR, 0x10); spd_enable_refresh(ctrl); - mdelay(10); + udelay(1); PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); DUMPNORTH();

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[LinuxBIOS] r338 - LinuxBIOSv3/lib
by svn＠openbios.org 28 May '07

28 May '07

Author: uwe Date: 2007-05-28 16:34:05 +0200 (Mon, 28 May 2007) New Revision: 338 Added: LinuxBIOSv3/lib/ram.c Log: Initial version of a generic RAM initialization framework. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: LinuxBIOSv3/lib/ram.c =================================================================== --- LinuxBIOSv3/lib/ram.c (rev 0) +++ LinuxBIOSv3/lib/ram.c 2007-05-28 14:34:05 UTC (rev 338) @@ -0,0 +1,74 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <hlt.h> + +/** + * Print an error message which says why the RAM initialization failed, + * then halt the processor(s). + * + * @param why The reason why the RAM initialization failed. + */ +void ram_failure(const char *why) +{ + printk(BIOS_EMERG, "RAM failure: %s: Halting\n", why); + hlt(); +} + +/** + * ram_initialize() is is the main RAM init function. + * + * It sets basic registers that can not be detected, then does the SPD step. + * Mainboards and other code can skip one of these steps by the expedient + * of making it an empty function. + * + * @param controllers How many memory controllers there are. + * @param ctrl Pointer to the mem control structure. + * @param sysinfo Not used on all targets. NULL if not used. This function + * does nothing with sysinfo but pass it on. + */ +void ram_initialize(int controllers, const struct mem_controller *ctrl, + void *sysinfo) +{ + int i; + + /* Set the registers we can set once to reasonable values. */ + for (i = 0; i < controllers; i++) { + printk(BIOS_INFO, + "Setting registers of RAM controller %d\n", i); + ram_set_registers(ctrl + i, sysinfo); + } + + /* Now setup those things we can auto detect. */ + for (i = 0; i < controllers; i++) { + printk(BIOS_INFO, + "Setting SPD based registers of RAM controller %d\n", i); + ram_set_spd_registers(ctrl + i, sysinfo); + } + + /* Now that everything is setup enable the RAM. Some chipsets do + * the work for us while on others we need to it by hand. + */ + printk(BIOS_DEBUG, "Enabling RAM\n"); + ram_enable(controllers, ctrl, sysinfo); + + /* RAM initialization is done. */ + printk(BIOS_DEBUG, "RAM enabled successfully\n"); +}

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[LinuxBIOS] r337 - LinuxBIOSv3/doc/design
by svn＠openbios.org 28 May '07

28 May '07

Author: uwe Date: 2007-05-28 16:30:53 +0200 (Mon, 28 May 2007) New Revision: 337 Modified: LinuxBIOSv3/doc/design/newboot.lyx Log: Correct minor spelling and formatting mistakes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: LinuxBIOSv3/doc/design/newboot.lyx =================================================================== --- LinuxBIOSv3/doc/design/newboot.lyx 2007-05-24 23:44:56 UTC (rev 336) +++ LinuxBIOSv3/doc/design/newboot.lyx 2007-05-28 14:30:53 UTC (rev 337) @@ -252,7 +252,7 @@ present (e.g. a 2-cpu system might have only one CPU installed). Also, hardware that can be probed, and that does not need any special configura -tion, can be left out of the configurtation file and left to be discovered +tion, can be left out of the configuration file and left to be discovered dynamically, even if it is known to be on the board. At run time, the software must determine what hardware exists, and modify the tree to accord to reality. @@ -290,9 +290,9 @@ \emph default , which define an address range that is picked up by default if no other resource claims it. - S + \emph on -ubtractive address ranges + Subtractive address ranges \emph default are typically used for legacy PC address ranges. @@ -319,7 +319,7 @@ This tree defines the hardware that is known to exist on the mainboard. At run time, the static tree is elided with dynamically determined information, and can even be restructured to some extent (e.g., the static tree has a - device at 0:4.0; if a dynamic device is found at 0:3.0, it will be place + device at 0:4.0; if a dynamic device is found at 0:3.0, it will be placed in the tree \begin_inset Quotes eld \end_inset @@ -386,12 +386,12 @@ \begin_layout Standard Devices, in some cases, have special control registers that need to be set. - in a few cases, generic code can handle these operiations: see device/pci_devic -e.c. + In a few cases, generic code can handle these operations: see device/pci_device. +c. Device-specific functions for controlling the device and its settings are found in the device-specific directory. All the configuration variables for controlling a device must be defined - in a single structure; to reiterate,that structure is defined in the file + in a single structure; to reiterate, that structure is defined in the file config.h. It is one structure, instead of a set of variables, because it must be instantiated and initialized by the device tree compiler (dtc), and a pointer @@ -644,7 +644,7 @@ \end_layout \begin_layout Standard -The dynamic constructor is part fo the device tree code. +The dynamic constructor is part of the device tree code. There is a set of default constructors, but each device can have its own private constructors if needed. The constructor structure is simple: it is a standard device id, and a @@ -669,7 +669,7 @@ components. Unlike V2, we are not using ld scripts to glue these components together, since the overall bugginess of the various tools (as and ld in particular) - made use of ldscripts very hard to mainbain. + made use of ldscripts very hard to maintain. \end_layout

1 0

[LinuxBIOS] IRQ problem
by Thomas Ekstrand 28 May '07

28 May '07

2007/5/24, Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: > On 24.05.2007 17:17, Thomas Ekstrand wrote: > > 2007/5/24, Jeremy Jackson <jerj(a)coplanar.net>: > >> On Thu, 2007-05-24 at 15:31 +0200, Thomas Ekstrand wrote: > >> > >> Each bridge must have a Hypertransport MSI Mapping configured. Linux > >> will complain about them being missing for some devices. If you can > >> look at the output of dmesg and maybe attach it here, there should be > >> some information that can help like this: > > > > It's attached! although not as nice as yours! :) I can't make out much :/ > > > > > > dmesg > > 6> MEM window: fc000000-fc0fffff > > PREFETCH window: 88000000-880fffff > > PCI: Bridge: 0000:00:06.0 > > IO window: disabled. > > MEM window: disabled. > > PREFETCH window: disabled. > > [...] > > The beginning of dmesg seems to have been snipped. Try setting > CONFIG_LOG_BUF_SHIFT=17 (or greater in your kernel config). > And use "dmesg -s131072". That should give you the full boot log. oh! Sorry! here it is. > > > bruf: module license 'Proprietary' taints kernel. > > bruf_init: module version 0.14 > > bruf_init: registered bruf with Major Number = 0x7f > > Interesting. I have never heard of that module. > > Regards, > Carl-Daniel > -- > http://www.hailfinger.org/ > setting "HAVE_MPTABLE=0" in mainboard Conif.lb makes the system halt at: "... Searching for server (DHCP)...\ Me: 192.168.0.8, DHCP: 192.168.0.1, TFTP: 192.168.0.1 Loading 192.168.0.1:linux2.elf (ELF)... done Firmware type: LinuxBIOS" Displaying postcode 0xd0. any suggestions? Are there more settings that needs to be enabled/disabled in order to deactivate the mptable? Is there some example to look at for doing acpi tables? Thanks Thomas

1 1

[LinuxBIOS] r2701 - in trunk/LinuxBIOSv2: src/mainboard/tyan/s1846 src/northbridge/intel/i440bx targets/tyan/s1846
by svn＠openbios.org 28 May '07

28 May '07

Author: uwe Date: 2007-05-28 01:31:31 +0200 (Mon, 28 May 2007) New Revision: 2701 Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/northbridge.c trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb Log: Various 440BX and Tyan S1846 related minor changes and fixes (trivial): - Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's available on all boards, regardless of what DIMMs you use. Tested on the Tyan S1846, works fine. - Properly set the PAM registers to allow the region from 768 KB - 1 MB to be used as normal RAM (required for the above). - Document all of this properly. Add/improve other documentation, too. - Simplify and document code in northbridge.c. - Cosmetics and coding style. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb 2007-05-27 21:43:58 UTC (rev 2700) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Options.lb 2007-05-27 23:31:31 UTC (rev 2701) @@ -60,7 +60,6 @@ ## default HAVE_PIRQ_TABLE=0 default IRQ_SLOT_COUNT=4 -#object irq_tables.o ## ## Build code to export a CMOS option table Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-05-27 21:43:58 UTC (rev 2700) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-05-27 23:31:31 UTC (rev 2701) @@ -31,7 +31,7 @@ #include "ram/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" -#include "mainboard/bitworks/ims/debug.c" // FIXME +#include "mainboard/bitworks/ims/debug.c" // FIXME #include "pc80/udelay_io.c" #include "lib/delay.c" #include "superio/nsc/pc87309/pc87309_early_serial.c" @@ -51,10 +51,8 @@ static void enable_mainboard_devices(void) { - device_t dev; + device_t dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0); - dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0); - if (dev == PCI_DEV_INVALID) { die("Southbridge not found!\n"); } else { @@ -66,13 +64,8 @@ { static const struct mem_controller memctrl[] = { { - .d0 = PCI_DEV(0, 0, 0), - .channel0 = { - (0xa << 3) | 0, - (0xa << 3) | 1, - (0xa << 3) | 2, - (0xa << 3) | 3, - }, + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, }, }; @@ -98,17 +91,22 @@ /* Check whether RAM is working. * - * Do _not_ check the area from 640 KB - 1 MB, as that's not really - * RAM, but rather reserved for various other things: + * Do _not_ check the area from 640 KB - 768 KB, as that's not really + * RAM, but rather reserved for the 'Video Buffer Area'. * + * Other stuff in the range from 640 KB - 1 MB: + * * - 640 KB - 768 KB: Video Buffer Area * - 768 KB - 896 KB: Expansion Area * - 896 KB - 960 KB: Extended System BIOS Area * - 960 KB - 1 MB: Memory (BIOS Area) - System BIOS Area * - * Trying to check these areas will fail. + * Trying to check these areas will usually fail, too. However, you + * probably can set the PAM registers of the northbridge to map + * those areas to RAM (read/write). In that case you can use the + * range from 768 KB - 1 MB as normal RAM, and thus check it here. */ - /* TODO: This is currently hardcoded to check 64 MB. */ ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ - ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ + ram_check(0x000c0000, 0x00100000); /* 768 KB - 1 MB */ + // ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ } Modified: trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/northbridge.c 2007-05-27 21:43:58 UTC (rev 2700) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/northbridge.c 2007-05-27 23:31:31 UTC (rev 2701) @@ -92,44 +92,41 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; - uint32_t pci_tolm; + uint32_t pci_tolm; - pci_tolm = find_pci_tolm(&dev->link[0]); + pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; if (mc_dev) { - /* Figure out which areas are/should be occupied by RAM. - * This is all computed in kilobytes and converted to/from - * the memory controller right at the edges. - * Having different variables in different units is - * too confusing to get right. Kilobytes are good up to - * 4 Terabytes of RAM... - */ uint16_t tolm_r; unsigned long tomk, tolmk; int idx; - /* Get the value of the highest DRB. This tells the end of - * the physical memory. The units are ticks of 8MB - * i.e. 1 means 8MB. + /* Figure out which areas are/should be occupied by RAM. The + * value of the highest DRB denotes the end of the physical + * memory (in units of 8MB). */ - tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)) << 13; - printk_debug("Setting RAM size to %d MB\n", tomk >> 10); + tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)); - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; + /* Convert to KB. */ + tomk *= (8 * 1024); + + printk_debug("Setting RAM size to %d MB\n", tomk / 1024); + + /* Compute the top of low memory. */ + tolmk = pci_tolm / 1024; + if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. - */ + /* The PCI hole does does not overlap the memory. */ tolmk = tomk; } - /* Report the memory regions */ + /* Report the memory regions. */ idx = 10; ram_resource(dev, idx++, 0, 640); - // ram_resource(dev, idx++, 768, tolmk - 768); - ram_resource(dev, idx++, 1024, tolmk - 1024); + ram_resource(dev, idx++, 768, tolmk - 768); } + assign_resources(&dev->link[0]); } @@ -179,6 +176,6 @@ } struct chip_operations northbridge_intel_i440bx_ops = { - CHIP_NAME("Intel 440BX Northbridge") + CHIP_NAME("Intel 82443BX (440BX) Northbridge") .enable_dev = enable_dev, }; Modified: trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c 2007-05-27 21:43:58 UTC (rev 2700) +++ trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c 2007-05-27 23:31:31 UTC (rev 2701) @@ -69,7 +69,7 @@ /* Table format: register, bitmask, value. */ static const long register_values[] = { /* NBXCFG - NBX Configuration Register - * 0x50 + * 0x50 - 0x53 * * [31:24] SDRAM Row Without ECC * 0 = ECC components are populated in this row @@ -158,6 +158,7 @@ /* * PAM[6:0] - Programmable Attribute Map Registers + * 0x59 - 0x5f * * 0x59 [3:0] Reserved * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area @@ -181,13 +182,13 @@ * 11 = Read/Write (all access goes to DRAM) */ // TODO - PAM0, 0x00000000, 0x00, - PAM1, 0x00000000, 0x00, - PAM2, 0x00000000, 0x00, - PAM3, 0x00000000, 0x00, - PAM4, 0x00000000, 0x00, - PAM5, 0x00000000, 0x00, - PAM6, 0x00000000, 0x00, + PAM0, 0x00, 0x00, + PAM1, 0x00, 0x00, + PAM2, 0x00, 0x00, + PAM3, 0x00, 0x00, + PAM4, 0x00, 0x00, + PAM5, 0x00, 0x00, + PAM6, 0x00, 0x00, /* DRB[0:7] - DRAM Row Boundary Registers * 0x60 - 0x67 @@ -204,7 +205,7 @@ * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB) * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) */ - // TODO + /* Set the DRBs to zero for now, this will be fixed later. */ DRB0, 0x00, 0x00, DRB1, 0x00, 0x00, DRB2, 0x00, 0x00, @@ -424,7 +425,7 @@ max = sizeof(register_values) / sizeof(register_values[0]); - /* Set registers as specified in the register_values array. */ + /* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { reg = pci_read_config32(ctrl->d0, register_values[i]); reg &= register_values[i + 1]; @@ -448,7 +449,21 @@ { /* TODO: Don't hardcode the values here, get info via SPD. */ + /* Map all legacy regions to RAM (read/write). This is required if + * you want to use the RAM area from 768 KB - 1 MB. If the PAM + * registers are not set here appropriately, the RAM in that region + * will not be accessible, thus a RAM check of it will also fail. + */ + pci_write_config8(ctrl->d0, PAM0, 0x30); + pci_write_config8(ctrl->d0, PAM1, 0x33); + pci_write_config8(ctrl->d0, PAM2, 0x33); + pci_write_config8(ctrl->d0, PAM3, 0x33); + pci_write_config8(ctrl->d0, PAM4, 0x33); + pci_write_config8(ctrl->d0, PAM5, 0x33); + pci_write_config8(ctrl->d0, PAM6, 0x33); + /* TODO: Set DRB0-DRB7. */ + /* Currently this is hardcoded to one 64 MB DIMM in slot 0. */ pci_write_config8(ctrl->d0, DRB0, 0x08); pci_write_config8(ctrl->d0, DRB1, 0x08); pci_write_config8(ctrl->d0, DRB2, 0x08); Modified: trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-05-27 21:43:58 UTC (rev 2700) +++ trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-05-27 23:31:31 UTC (rev 2701) @@ -22,10 +22,11 @@ mainboard tyan/s1846 option ROM_SIZE = 256 * 1024 +# option FALLBACK_SIZE = 256 * 1024 romimage "normal" option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE=0x0e000 + option ROM_IMAGE_SIZE = 56 * 1024 option LINUXBIOS_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf # payload /tmp/memtest @@ -33,7 +34,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE=0x0e000 + option ROM_IMAGE_SIZE = 56 * 1024 option LINUXBIOS_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf # payload /tmp/memtest

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[LinuxBIOS] r2700 build service
by LinuxBIOS information 28 May '07

28 May '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2700 to the LinuxBIOS source repository and caused the following changes: Change Log: Init for the Intel 82371EB southbridge: make all ROM/BIOS regions accessible (but not writable), so that reading/loading a payload from that area can work (for instance). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2700&device=hdama&vendor=… Configuration of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2700&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2700&device=e326&vendor=i… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2700&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2700&device=dk8x&vendor=i… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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coreboot May 2007