coreboot May 2007

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98 participants
436 discussions

[LinuxBIOS] WARNING: flashrom coding style fixes ahead
by Uwe Hermann 05 May '07

05 May '07

I'm going to run indent over all of the flashrom code today or tomorrow to fix it once and for all. Are there any pending patches which might be broken by this? If so, please speak up now! Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] patch: digital logic msm800 sev support
by ron minnich 05 May '07

05 May '07

This modifies the latest tree for digital logic msm 800 sev. Unfortunately, it is locking up at post code 88, with this: Initializing devices... Root Device init MSM800SEV ENTER init MSM800SEV EXIT init PCI: 00:01.0 init >> Entering northbridge.c: northbridge_init PCI: 00:01.1 init PCI: 00:0f.0 init cs5536: southbridge_init RTC Init GPIO_ADDR: 00001000 This is not the behaviour seen on the private tree I got from AMD, and patched, so I need to figure out what is up. This patch includes: changes to mainboard/digitallogic/msm800sev, targets/digitallogic/msm800sev It includes one label added to the lx cache_as_ram.inc, because once ram is turned on, the return from function cache_as_main in mainboard/digitallogic/msm800sev/cache_as_ram_auto.c fails. Please see the patch for details. This is not quite there, but I wanted to start getting the changes in. It builds, but does not work completely. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>

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[LinuxBIOS] r2635 - trunk/LinuxBIOSv2/src/mainboard/amd/norwich
by svn＠openbios.org 04 May '07

04 May '07

Author: uwe Date: 2007-05-04 23:52:18 +0200 (Fri, 04 May 2007) New Revision: 2635 Removed: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/debug.c Log: Drop src/mainboard/amd/norwich/debug.c as it is not used. I'm self-acking as this is pretty trivial. I tested both a normal build and an abuild-run, and nothing breaks. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/debug.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/debug.c 2007-05-04 21:33:40 UTC (rev 2634) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/debug.c 2007-05-04 21:52:18 UTC (rev 2635) @@ -1,65 +0,0 @@ -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} - -static void print_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - print_debug_pci_dev(dev); - print_debug("\r\n"); - } -} - -static void dump_pci_device(unsigned dev) -{ - int i; - print_debug_pci_dev(dev); - print_debug("\r\n"); - - for(i = 0; i <= 255; i++) { - unsigned char val; - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - val = pci_read_config8(dev, i); - print_debug_char(' '); - print_debug_hex8(val); - if ((i & 0x0f) == 0x0f) { - print_debug("\r\n"); - } - } -} - -static void dump_pci_devices(void) -{ - device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; - id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { - continue; - } - dump_pci_device(dev); - } -}

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[LinuxBIOS] [MERGE] AMD Geode LX support for LinuxBIOS
by Stefan Reinauer 04 May '07

04 May '07

Hi. I think the code is all in, except patch [05/10] which did not seem to apply (header change) What else is missing? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/

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[LinuxBIOS] [PATCH] Minor ITE IT8716F fixes
by Uwe Hermann 04 May '07

04 May '07

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] r2634 - trunk/LinuxBIOSv2/src/superio/ite/it8716f
by svn＠openbios.org 04 May '07

04 May '07

Author: uwe Date: 2007-05-04 23:33:40 +0200 (Fri, 04 May 2007) New Revision: 2634 Modified: trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c Log: Some minor fixes in it8716f/superio.c: - Add Ward Vandewege <ward(a)gnu.org> as copyright holder. - Use explicit 'uint16_t' instead of 'unsigned long'. - Minor cosmetics. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c 2007-05-04 19:43:57 UTC (rev 2633) +++ trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c 2007-05-04 21:33:40 UTC (rev 2634) @@ -2,9 +2,9 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * (Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD) + * Copyright (C) 2007 Ward Vandewege <ward(a)gnu.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,9 +26,9 @@ #include <console/console.h> #include <uart8250.h> #include <pc80/keyboard.h> +#include <arch/io.h> #include "chip.h" #include "it8716f.h" -#include <arch/io.h> /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ @@ -50,29 +50,32 @@ pnp_write_config(dev, 0x02, 0x02); } -static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) +static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value) { outb(reg, port_base); outb(value, port_base + 1); } -static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) +static uint8_t pnp_read_index(uint16_t port_base, uint8_t reg) { outb(reg, port_base); return inb(port_base + 1); } -static void init_ec(unsigned long base) +static void init_ec(uint16_t base) { uint8_t value; - // Read out current value of FAN_CTL Control register (0x14) + /* Read out current value of FAN_CTL control register (0x14). */ value = pnp_read_index(base, 0x14); - printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",base + 0x14, value); - - // Set FAN_CTL Control register (0x14) polarity to High, and activate fans 1, 2 and 3 + printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n", + base + 0x14, value); + + /* Set FAN_CTL control register (0x14) polarity to high, and + activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); - printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",base + 0x14, value | 0x87); + printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", + base + 0x14, value | 0x87); } static void it8716f_init(device_t dev) @@ -140,27 +143,28 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, IT8716F_KBCM, PNP_IRQ0, }, + {&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + {&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, + {&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, + {0x7f8, 0x4},}, + {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, + {0x7ff, 0x4},}, + {&ops, IT8716F_KBCM, PNP_IRQ0,}, // No 7 { 0,}, - { &ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4}, }, - { &ops, IT8716F_GAME, PNP_IO0, { 0x7ff, 0 }, }, - { &ops, IT8716F_IR, }, + {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, + {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, + {&ops, IT8716F_IR,}, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, - sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); + sizeof(pnp_dev_info) / sizeof(pnp_dev_info[0]), pnp_dev_info); } struct chip_operations superio_ite_it8716f_ops = { CHIP_NAME("ITE IT8716F Super I/O") .enable_dev = enable_dev, }; -

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[LinuxBIOS] r2630 build service
by LinuxBIOS information 04 May '07

04 May '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2630 to the LinuxBIOS source repository and caused the following changes: Change Log: This patch adds support for the northbridge integrated into the AMD Geode LX platform, including memory and graphics. (rediffed for whitespace) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:norwich is still broken Compilation of amd:rumba is still broken Compilation of arima:hdama is still broken Compilation of artecgroup:dbe61 is still broken Compilation of digitallogic:msm800sev is still broken Compilation of ibm:e325 is still broken Compilation of ibm:e326 is still broken Compilation of iwill:dk8s2 is still broken Compilation of iwill:dk8x is still broken Compilation of lippert:frontrunner is still broken Compilation of olpc:btest is still broken Compilation of olpc:rev_a is still broken If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2629 build service
by LinuxBIOS information 04 May '07

04 May '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2629 to the LinuxBIOS source repository and caused the following changes: Change Log: This patch adds support for the AMD Norwich development platform based on the Geode LX processor. The Norwich is the canonical Geode reference, and will server as a good basis for other Geode based platforms. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:norwich is still broken Compilation of amd:rumba is still broken Compilation of arima:hdama is still broken Compilation of artecgroup:dbe61 is still broken Compilation of digitallogic:msm800sev is still broken Compilation of ibm:e325 is still broken Compilation of ibm:e326 is still broken Compilation of iwill:dk8s2 is still broken Compilation of iwill:dk8x is still broken Compilation of lippert:frontrunner is still broken Compilation of olpc:btest is still broken Compilation of olpc:rev_a is still broken If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] EPIA patch to fix non working IDE, with sigin off
by Ben Hewson 04 May '07

04 May '07

patch to fix the IDE configuration on EPIA boards. At some point this broke and stopped FILO from being able to boot. The fix is a simple one line change plus a comment to src/mainboard/via/epia/auto.c to write to the IDE configuration register 0x42 . This has always been done here, however at some point something broke it. The same register was also being set correctly in ide_init(), however for some reason this does not work. Possibly the register needs to be set before the IDE peripheral is enabled or maybe it is a timing issue. The section of code in ide_init() ( src/southbridge/via/vt8231/vt8231_ide.c ) that does write to register 0x42 has been commented out as it is superfluous and I have added a comment to indicate the reason, should someone at a future date wonder why. I have also changed the default COM speed from 19200 to 115200 in src/mainboard/via/epia/Options.lb There has been mention before about the EPIA board not being able to use 115200 but I have seen no such problems with my board. Signed-off-by: Ben Hewson <ben(a)hewson-venieri.com> -------------------------------------------------------------------------------------------------------------------------------- Index: src/mainboard/via/epia/auto.c =================================================================== --- src/mainboard/via/epia/auto.c (revision 2621) +++ src/mainboard/via/epia/auto.c (working copy) @@ -66,8 +66,16 @@ /* we do this here as in V2, we can not yet do raw operations * to pci! */ - dev += 0x100; /* ICKY */ - + + /* changed this to work correctly on later revisions of LB. + * The original dev += 0x100; stopped working. It also appears + * that if this is not set here, but in ide_init() only, the IDE + * does not work at all. I assume it needs to be set before something else, + * possibly before enabling the IDE peripheral, or it is a timing issue. + * Ben Hewson 29 Apr 2007. + */ + + dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0); pci_write_config8(dev, 0x42, 0); } Index: src/southbridge/via/vt8231/vt8231_ide.c =================================================================== --- src/southbridge/via/vt8231/vt8231_ide.c (revision 2621) +++ src/southbridge/via/vt8231/vt8231_ide.c (working copy) @@ -15,6 +15,12 @@ // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI // interrupts. Using PCI ints confuses linux for some reason. + /* Setting reg 0x42 here does not work. It is set in mainboard/auto.c + * It probably can only be changed while the IDE is disabled + * or it is possibly a timing issue. Ben Hewson 29 Apr 2007. + */ + + /* printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__); enables = pci_read_config8(dev, 0x42); printk_debug("enables in reg 0x42 0x%x\n", enables); @@ -22,6 +28,8 @@ pci_write_config8(dev, 0x42, enables); enables = pci_read_config8(dev, 0x42); printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + */ + } enables = pci_read_config8(dev, 0x40); Index: src/mainboard/via/epia/Options.lb =================================================================== --- src/mainboard/via/epia/Options.lb (revision 2621) +++ src/mainboard/via/epia/Options.lb (working copy) @@ -51,7 +51,7 @@ default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=19200 +default TTYS0_BAUD=115200 # Select the serial console base port default TTYS0_BASE=0x3f8

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[LinuxBIOS] r2633 - in trunk/LinuxBIOSv2/src: mainboard/via/epia southbridge/via/vt8231
by svn＠openbios.org 04 May '07

04 May '07

Author: rminnich Date: 2007-05-04 21:43:57 +0200 (Fri, 04 May 2007) New Revision: 2633 Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb trunk/LinuxBIOSv2/src/mainboard/via/epia/auto.c trunk/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c Log: patch to fix the IDE configuration on EPIA boards. At some point this broke and stopped FILO from being able to boot. The fix is a simple one line change plus a comment to src/mainboard/via/epia/auto.c to write to the IDE configuration register 0x42 . This has always been done here, however at some point something broke it. The same register was also being set correctly in ide_init(), however for some reason this does not work. Possibly the register needs to be set before the IDE peripheral is enabled or maybe it is a timing issue. The section of code in ide_init() ( src/southbridge/via/vt8231/vt8231_ide.c ) that does write to register 0x42 has been commented out as it is superfluous and I have added a comment to indicate the reason, should someone at a future date wonder why. I have also changed the default COM speed from 19200 to 115200 in src/mainboard/via/epia/Options.lb There has been mention before about the EPIA board not being able to use 115200 but I have seen no such problems with my board. Signed-off-by: Ben Hewson <ben(a)hewson-venieri.com> This patch worked for me and allowed me to boot Debian kernel 2.5.16-4-486 on an epia 800 mhz system. It is able to consistently get through the initialization and start init now. However, after that it crashes at various points in the boot process. Acked-by: Alex Mauer <hawke(a)hawkesnest.net> Note from comitter: I am commiting this, although: 1. it's not the exact right way to fix it up, the chip.h for the sb should change 2. Alex reports problems, which are almost certainly memory issues. But it is as close as we've gotten. I can't test it. Ron Minnich Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb 2007-05-04 19:09:01 UTC (rev 2632) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia/Options.lb 2007-05-04 19:43:57 UTC (rev 2633) @@ -51,7 +51,7 @@ default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=19200 +default TTYS0_BAUD=115200 # Select the serial console base port default TTYS0_BASE=0x3f8 Modified: trunk/LinuxBIOSv2/src/mainboard/via/epia/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/via/epia/auto.c 2007-05-04 19:09:01 UTC (rev 2632) +++ trunk/LinuxBIOSv2/src/mainboard/via/epia/auto.c 2007-05-04 19:43:57 UTC (rev 2633) @@ -66,8 +66,15 @@ /* we do this here as in V2, we can not yet do raw operations * to pci! */ - dev += 0x100; /* ICKY */ + /* changed this to work correctly on later revisions of LB. + * The original dev += 0x100; stopped working. It also appears + * that if this is not set here, but in ide_init() only, the IDE + * does not work at all. I assume it needs to be set before something else, + * possibly before enabling the IDE peripheral, or it is a timing issue. + * Ben Hewson 29 Apr 2007. + */ + dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0); pci_write_config8(dev, 0x42, 0); } Modified: trunk/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c 2007-05-04 19:09:01 UTC (rev 2632) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c 2007-05-04 19:43:57 UTC (rev 2633) @@ -14,7 +14,12 @@ if (!conf->enable_native_ide) { // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI // interrupts. Using PCI ints confuses linux for some reason. - + /* Setting reg 0x42 here does not work. It is set in mainboard/auto.c + * It probably can only be changed while the IDE is disabled + * or it is possibly a timing issue. Ben Hewson 29 Apr 2007. + */ + + /* printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__); enables = pci_read_config8(dev, 0x42); printk_debug("enables in reg 0x42 0x%x\n", enables); @@ -22,6 +27,7 @@ pci_write_config8(dev, 0x42, enables); enables = pci_read_config8(dev, 0x42); printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + */ } enables = pci_read_config8(dev, 0x40);

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coreboot May 2007