coreboot May 2007

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[LinuxBIOS] r2639 build service
by LinuxBIOS information 07 May '07

07 May '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2639 to the LinuxBIOS source repository and caused the following changes: Change Log: Add missing licenses to several of the files. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken Compilation of artecgroup:dbe61 is still broken Compilation of ibm:e325 is still broken Compilation of ibm:e326 is still broken Compilation of iwill:dk8s2 is still broken Compilation of iwill:dk8x is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] r2639 - trunk/LinuxBIOSv2/src/mainboard/amd/norwich
by svn＠openbios.org 07 May '07

07 May '07

Author: uwe Date: 2007-05-08 00:26:46 +0200 (Tue, 08 May 2007) New Revision: 2639 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/auto.c trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c trunk/LinuxBIOSv2/src/mainboard/amd/norwich/chip.h Log: Add missing licenses to several of the files. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/auto.c 2007-05-05 03:54:13 UTC (rev 2638) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/auto.c 2007-05-07 22:26:46 UTC (rev 2639) @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #define ASSEMBLY 1 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-05 03:54:13 UTC (rev 2638) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/cache_as_ram_auto.c 2007-05-07 22:26:46 UTC (rev 2639) @@ -1,8 +1,22 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* -*/ + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #define ASSEMBLY 1 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/norwich/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/amd/norwich/chip.h 2007-05-05 03:54:13 UTC (rev 2638) +++ trunk/LinuxBIOSv2/src/mainboard/amd/norwich/chip.h 2007-05-07 22:26:46 UTC (rev 2639) @@ -1,10 +1,23 @@ /* -* -* Copyright (C) 2007 Advanced Micro Devices -* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ -*/ - extern struct chip_operations mainboard_amd_norwich_ops; struct mainboard_amd_norwich_config {

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[LinuxBIOS] ECS top hat flash - dual-bios-circuit useable elsewhere ?
by Quux 07 May '07

07 May '07

I just managed to get my hands on a top hat flash. it is an empty plcc32 socket to flip over an soldered in flash chip. attached to the socket is a secondary flash mem and some circuitry to handle the "chip enable" signal, i.e. pull down the primary one and daisy chain the data/addr bus. now I wonder, whether it is risky to use it on a non Elitegroup mainboard and it might brick a mobo with no matching circuitry. Ideally, I hope it works on a Gigabyte M57. should I give it a go ? --Q

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[LinuxBIOS] [patch 00/10] Geode LX (round 2)
by Marc Jones 07 May '07

07 May '07

Hi - Here is a refresh of the Geode LX patches based on the comments from the list. This set also includes the patches to add the GPL licenses to some of the files that Jordan posted. This should be ready for commit. Marc

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[LinuxBIOS] Is my hardware supported - p4p800e
by N. Gey 07 May '07

07 May '07

[I'm sorry if this is a double post! I was greatly confused through my different emailadresses. I hope this is the only mail you'll get from me] Dear mailinglist people. I want to use linuxbios but I'm not sure if its possible. Following your wiki I want to kindly ask you if my hardware is compatible. I'm running Ubuntu 7.04 Feisty Fawn -Step 1: A very brief description of your system: CPU, northbridge, southbridge, mainboard and optionally other important details. CPU: Intel P4 3000 with Hyperthreading. capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe cid xtpr Mainboard: Asus p4p800-e deluxe Northbridge: Intel 865PE MCH Southbridge: 82801EB/ER (ICH5/ICH5R) Graphic Cards is ATI Radeon 9800 pro AGP Step 2: Linux lspci output for your system, generated by booting Linux via the original BIOS and runnning lspci. lspci 00:00.0 Host bridge: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface (rev 02) 00:01.0 PCI bridge: Intel Corporation 82865G/PE/P PCI to AGP Controller (rev 02) 00:1d.0 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 (rev 02) 00:1d.1 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 (rev 02) 00:1d.2 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 (rev 02) 00:1d.3 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 (rev 02) 00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev c2) 00:1f.0 ISA bridge: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller (rev 02) 01:00.0 VGA compatible controller: ATI Technologies Inc Radeon R350 [Radeon 9800 Pro] 01:00.1 Display controller: ATI Technologies Inc Radeon R350 [Radeon 9800 Pro] (Secondary) 02:03.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 80) 02:04.0 RAID bus controller: Promise Technology, Inc. PDC20378 (FastTrak 378/SATA 378) (rev 02) 02:05.0 Ethernet controller: Marvell Technology Group Ltd. 88E8001 Gigabit Ethernet Controller (rev 13) 02:0a.0 Multimedia audio controller: VIA Technologies Inc. ICE1712 [Envy24] PCI Multi-Channel I/O Controller (rev 02) Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip) Winbond W83627THF-A 411G7D2402564QUA Step 4: Type of BIOS device. PLCC / QJF Step 5: URL to the mainboard specifications page (optional). * http://www.asus.de/products.aspx?l1=3&l2=12&l3=31&l4=0&model=178&modelmenu=2 Step 6: Any other relevant information you can provide. Nothing Special. It's an few years old standard system with 1 GB RAM and an additional PCI Soundcard M-Audi 2469 running Ubuntu Linux 2469. I'm using SATA drives.

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[LinuxBIOS] top hat flash : /OE rewiring
by Quux 07 May '07

07 May '07

yo ! for mainboards with soldered-on plcc32 flashroms it should be possible to use DIY secondary bioses. ECS Elitegroup ship many of their boards with what they call "top hat flash". This is comprised of two adjacent plcc32 sockets with just a minor rewiring: on the replacement socket, /OE (*out enable, active low*) is hardwired to /reset, thus activating the secondary chip. on the pcb-side (the empty socket to flip over the pcb-soldered chip) /OE is wired to an upper NC pin 26 (not connected). *All other pins are wired 1:1* , both chips are in parallel. LPC is designed as a bus (mind the 3 ID pins). the top hat flash is populated with a W39V040AP FWH ( Winbond firmware hub). I used to think that there might be some resistor or sth. to pull the pcb chip's */OE-/Init* high (= inactive) while the ECS mainboard would have like a voltage divider feeding */OE-/Init* to allow this. I do not quite get the idea why the pcb-bios does disable it outputs (if it does) when it is possible that both chips have /OE active (but the spare chip earlier in sync with /reset). any clue? anyway, this type of circuit should work with most plcc32 FWH's . But use it at your own risk. --Quux

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[LinuxBIOS] Question About Filo fail
by AlexHuang 07 May '07

07 May '07

Hi all, I let my platform can do filo booting now. But there are some message listed as follow. It said that "No drive detected on IDE channel 0", but I really have a disk on IDE Channel0. Does somebody can help me to solve this problem? Thanks a lot Alex Jumping to boot code at 0x10dacc FILO version 0.5 (alexjoy(a)cvs.sis.com) Mon May 7 10:31:19 CST 2007 menu: hda1:/boot/grub/menu.lst Detected floating bus No drive detected on IDE channel 0 Press any key to continue.

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[LinuxBIOS] intel 945gm chipset
by Riccardo Sala 07 May '07

07 May '07

Hi everyone, I'm new to this mailing list and to linux bios. I have an intel 945GM board development kit, is it possible to boot windows XP, with some work, with linux bios? Or this chipset is so far to be supported and this task is quite impossible? Thanks for yours answers! Riccardo -- Ing. Riccardo Sala R&D Engineer M31 s.r.l. 35129, Via Croce Rossa 112 Padova (PD), Italy Phone: +39 0498697508 Mobile: +39 349678877

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[LinuxBIOS] [patch 0/4] AMD Geode LX support for LinuxBIOS
by Marc Jones 07 May '07

07 May '07

Hello LinuxBIOS Community, My name is Marc Jones and I work for the AMD embedded group. Jordan Crouse and I have been working with Ron Minnich on a Geode LX LinuxBIOS implementation for the AMD Norwich development platform. The Norwich platform should be a good starting point for all current and future Geode LX platforms. Our implementation has been split into four patches: cpu, northbridge, southbridge, and mainboard. All four are required to build the Norwich platform. Ron and I expect this to break the current OLPC mainboards. We will work on fixing then soon (Note that OLPC went from GX to LX so an update was required regardless). In addition to the patches you will need the Geode LX VSA binary that is located here: http://www.amd.com/files/connectivitysolutions/geode/geode_lx/lx_vsa.36k.bi… You might find it helpful to use BuildROM to build the Norwich platform. BuildROM builds LinuxBIOS, builds a payload (etherboot, filo, or memtest), and bundles in the LX VSA to make one ROM image. Jordan Crouse will be sending out patches and instructions for buildROM soon. I look forward to working with you all. Marc

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[LinuxBIOS] Televideo TC7020 successfully booted with LinuxBiosV2
by Kenji Noguchi 06 May '07

06 May '07

Hi, I bought a TC7020, Windows CE.NET based thin client terminal for $10 about a week ago, and wanted to make it a car-puter. http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm The box uses NS Geode GX1 CPU, PC97317 Super I/O, CS5530A south bridge, DP83815 NIC, and SST 29EE020 BIOS chip. I noticed the system configuration is very similiar to eaglelion/5bcm, and wanted to see how far it goes with unmodified configuration. I chosed Etherboot as payload, it just booted as if the 5bcm and TC7020 was identical box. Thank you for the great software! Kenji Noguchi

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coreboot May 2007