[LinuxBIOS] patch: digital logic msm800 sev support

[ron minnich]

This modifies the latest tree for digital logic msm 800 sev.
Unfortunately, it is locking up at post code 88, with this:
Initializing devices...
Root Device init
MSM800SEV ENTER init
MSM800SEV EXIT init
PCI: 00:01.0 init
> > Entering northbridge.c: northbridge_init

PCI: 00:01.1 init
PCI: 00:0f.0 init
cs5536: southbridge_init
RTC Init
GPIO_ADDR: 00001000

This is not the behaviour seen on the private tree I got from AMD, and
patched, so I need to figure out what is up.

This patch includes:
changes to mainboard/digitallogic/msm800sev, targets/digitallogic/msm800sev
It includes one label added to the lx cache_as_ram.inc, because once
ram is turned on, the return from function cache_as_main in
mainboard/digitallogic/msm800sev/cache_as_ram_auto.c fails. Please see
the patch for details.

This is not quite there, but I wanted to start getting the changes in.
It builds, but does not work completely.

Signed-off-by: Ronald G. Minnich

[Uwe Hermann]

On Fri, May 04, 2007 at 02:01:42PM -0700, ron minnich wrote:
> This modifies the latest tree for digital logic msm 800 sev.

I think the patch is missing.

Uwe.

[ron minnich]

it's really here this time!

On 5/4/07, ron minnich  wrote:
> This modifies the latest tree for digital logic msm 800 sev.
> Unfortunately, it is locking up at post code 88, with this:
> Initializing devices...
> Root Device init
> MSM800SEV ENTER init
> MSM800SEV EXIT init
> PCI: 00:01.0 init
> > > Entering northbridge.c: northbridge_init
>
> PCI: 00:01.1 init
> PCI: 00:0f.0 init
> cs5536: southbridge_init
> RTC Init
> GPIO_ADDR: 00001000
>
> This is not the behaviour seen on the private tree I got from AMD, and
> patched, so I need to figure out what is up.
>
> This patch includes:
> changes to mainboard/digitallogic/msm800sev, targets/digitallogic/msm800sev
> It includes one label added to the lx cache_as_ram.inc, because once
> ram is turned on, the return from function cache_as_main in
> mainboard/digitallogic/msm800sev/cache_as_ram_auto.c fails. Please see
> the patch for details.
>
> This is not quite there, but I wanted to start getting the changes in.
> It builds, but does not work completely.
>
> Signed-off-by: Ronald G. Minnich

[Uwe Hermann]

NAK, doesn't build for me:

make[1]: Entering directory `/tmp/v2/targets/digitallogic/msm800sev/msm800sev/fallback'
cp /tmp/v2/src/arch/i386/init/crt0.S.lb crt0.S
make[1]: *** No rule to make target `/tmp/v2/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c', needed by `cache_as_ram_auto.inc'.  Stop.
make[1]: Leaving directory `/tmp/v2/targets/digitallogic/msm800sev/msm800sev/fallback'
make: *** [fallback/linuxbios.rom] Error 1

On Fri, May 04, 2007 at 02:41:56PM -0700, ron minnich wrote:
> Index: src/mainboard/digitallogic/msm800sev/Config.lb
>
> --- src/mainboard/digitallogic/msm800sev/Config.lb	(revision 2632)
> +++ src/mainboard/digitallogic/msm800sev/Config.lb	(working copy)
> @@ -15,12 +15,12 @@
>  ## The linuxBIOS bootloader.
>  ##
>  default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
> -default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
> +default PAYLOAD_SIZE			= ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )

No whitespace breakage, please.
> ##
>  ## Compute where this copy of linuxBIOS will start in the boot rom
>  ##
> -default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
> +default _ROMBASE	  = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )

Ditto.

(and many other places)
> ### Should this be in the northbridge code?
> -mainboardinit arch/i386/lib/cpu_reset.inc
> +#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc

?
> struct chip_operations mainboard_digitallogic_msm800sev_ops = {
> CHIP_NAME("DIGITAL-LOGIC MSM800SEV Mainboard")
> CHIP_NAME("digitallogip msm800sev mainboard ")
>     .enable_dev = enable_dev,

Nope, please drop this hunk.

Uwe.