coreboot May 2007

coreboot@coreboot.org

98 participants
436 discussions

[LinuxBIOS] Support for some more SuperIOs/old Chipsets
by popkonserve 03 May '07

03 May '07

hi, i just subscribed to the mailing list and i need a speedup on the development of LinuxBIOSv2 as i want to contribute some code. I thought of some SuperIO chips i still have docs for, maybe completing some of the code already written (there are a lot of TODOs in the code). Finally i'm thinking of contributing code for some older chipsets (ALi socket7, VIA socket7, intel socket7) and maybe cpus (cyrix 6x86 family, amd k6 familiy, intel pentium (mmx)) as i think those boards deserve a fast booting bios without too much useless stuff in there. i didn't took a deep look into the api yet. so i still have a lot of questions: where should i start? Chipsets and CPUs or rather some SuperIO stuff? and what i really need to know is: where is the configuration done? let's say ram timings (no spd on edo/fpm), superIO settings, etc. (there are a lot other chipset tweaks that could be applied). btw. currently i'm working as a developer for embedded automotive systems, so i hope i can help with some code.

2 1

[LinuxBIOS] r2624 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 03 May '07

03 May '07

Author: uwe Date: 2007-05-03 12:09:23 +0200 (Thu, 03 May 2007) New Revision: 2624 Modified: trunk/LinuxBIOSv2/util/flashrom/README trunk/LinuxBIOSv2/util/flashrom/board_enable.c Log: Enable flashing on the IWILL DK8-HTX board by configuring the Super I/O to set the right GPIO pins, so write protection is disabled. Signed-off-by: Mondrian Nuessle <nuessle(a)uni-mannheim.de> Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/util/flashrom/README =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/README 2007-05-03 08:50:37 UTC (rev 2623) +++ trunk/LinuxBIOSv2/util/flashrom/README 2007-05-03 10:09:23 UTC (rev 2624) @@ -47,7 +47,13 @@ flashrom -w --mainboard ISLAND:ARUMA island_aruma.rom +The following boards require the specification of the board name, if +no LinuxBIOS table is found: +* IWILL DK8-HTX: use -m iwill:dk8_htx +* agami Aruma: use -m AGAMI:ARUMA + + ROM Layout Support ------------------ Modified: trunk/LinuxBIOSv2/util/flashrom/board_enable.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/board_enable.c 2007-05-03 08:50:37 UTC (rev 2623) +++ trunk/LinuxBIOSv2/util/flashrom/board_enable.c 2007-05-03 10:09:23 UTC (rev 2624) @@ -23,6 +23,56 @@ #include "flash.h" #include "debug.h" +static int board_iwill_dk8_htx(const char *name) +{ + /* Extended function index register, either 0x2e or 0x4e. */ +#define EFIR 0x2e + /* Extended function data register, one plus the index reg. */ +#define EFDR EFIR + 1 + char b; + + /* Disable the flash write protect (which is connected to the + * Winbond W83627HF GPIOs). + */ + outb(0x87, EFIR); /* Sequence to unlock extended functions */ + outb(0x87, EFIR); + + /* Activate logical device. */ + outb(0x7, EFIR); + outb(8, EFDR); + + /* Set GPIO regs. */ + outb(0x2b, EFIR); /* GPIO multiplexed pin reg. */ + b = inb(EFDR) | 0xd0; + outb(0x2b, EFIR); + outb(b, EFDR); + + outb(0x30, EFIR); /* GPIO2 */ + b = inb(EFDR) | 0x01; + outb(0x30, EFIR); + outb(b, EFDR); + + outb(0xf0, EFIR); /* IO sel */ + b = inb(EFDR) | 0xef; + outb(0xf0, EFIR); + outb(b, EFDR); + + outb(0xf1, EFIR); /* GPIO data reg */ + b = inb(EFDR) | 0x16; + outb(0xf1, EFIR); + outb(b, EFDR); + + outb(0xf2, EFIR); /* GPIO inversion reg */ + b = inb(EFDR) | 0x00; + outb(0xf2, EFIR); + outb(b, EFDR); + + /* Lock extended functions again. */ + outb(0xaa, EFIR); /* Command to exit extended functions */ + + return 0; +} + /* * Match on pci-ids, no report received, just data from the mainboard * specific code: @@ -195,14 +245,16 @@ }; struct board_pciid_enable board_pciid_enables[] = { - { 0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000, - "AGAMI", "ARUMA", "Agami Aruma", board_agami_aruma }, - { 0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, + { 0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000, + "AGAMI", "ARUMA", "agami Aruma", board_agami_aruma }, + { 0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m }, - { 0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, - NULL, NULL, "Asus A7V8-MX SE", board_asus_a7v8x_mx }, + { 0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, + NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx }, + { 0x1022, 0x7468, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + "iwill", "dk8_htx", "IWILL DK8-HTX", board_iwill_dk8_htx }, + { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL } /* Keep this */ - }; /*

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[LinuxBIOS] r2623 build service
by LinuxBIOS information 03 May '07

03 May '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2623 to the LinuxBIOS source repository and caused the following changes: Change Log: Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB, as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken Compilation of ibm:e325 is still broken Compilation of ibm:e326 is still broken Compilation of iwill:dk8s2 is still broken Compilation of iwill:dk8x is still broken If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

1 0

[LinuxBIOS] [PATCH] Some more 440BX progress
by Uwe Hermann 03 May '07

03 May '07

Hi, here's a first patch for the 440BX code and the Tyan S1846 and the 82371EB southbridge which gets my Tyan S1846 a lot further in the boot process. However, it cannot boot a payload, yet. It seems the major problem was that I did ram_check() on the whole range from 0 - 64 MB (in my case; I use a 64 MB DIMM for testing). This cannot work of course, as the range from 640 KB - 1 MB is _not_ RAM but rather reserved for all kinds of other stuff (thanks Stefan for pointing this out!). Leaving out that range, but checking the rest of RAM, I get a "DRAM range verified", so it seems RAM init _does_ work after all. (it's hardcoded to my board and setup of course, but that'll be fixed) I've tried setting up the PCI devices correctly in Config.lb, but I'm absolutely not sure that I got it all right. Can somebody please check this and let me know of any stupid errors I made? Here's the lspci output from the Tyan S1846: 00:00.0 0600: 8086:7190 (rev 03) 00:01.0 0604: 8086:7191 (rev 03) 00:07.0 0601: 8086:7110 (rev 02) 00:07.1 0101: 8086:7111 (rev 01) 00:07.2 0c03: 8086:7112 (rev 01) 00:07.3 0680: 8086:7113 (rev 02) 00:10.0 0300: 5333:5631 (rev 06) 00:11.0 0200: 10ec:8029 00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03) 00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03) 00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02) 00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01) 00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01) 00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00:10.0 VGA compatible controller: S3 Inc. 86c325 [ViRGE] (rev 06) 00:11.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8029(AS) -[0000:00]-+-00.0 Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge +-01.0-[0000:01]-- +-07.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA +-07.1 Intel Corporation 82371AB/EB/MB PIIX4 IDE +-07.2 Intel Corporation 82371AB/EB/MB PIIX4 USB +-07.3 Intel Corporation 82371AB/EB/MB PIIX4 ACPI +-10.0 S3 Inc. 86c325 [ViRGE] \-11.0 Realtek Semiconductor Co., Ltd. RTL-8029(AS) (5333:5631 and 10ec:8029 are add-on cards -- VGA and Ethernet) And this is my current try to setup Config.lb: chip northbridge/intel/i440bx # Northbridge device pci_domain 0 on device pci 0.0 on end # Host bridge device pci 1.0 off end # PCI bridge TODO: AGP bridge? # device pci 7.0 on end # ISA bridge chip southbridge/intel/i82371eb # Southbridge device pci 7.0 on # ISA bridge ??? chip superio/nsc/pc87309 # Super I/O device pnp 2e.0 on end # Floppy device pnp 2e.1 on end # Parallel port device pnp 2e.2 on end # Com2 device pnp 2e.3 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.4 on end # Power mgmt. device pnp 2e.5 on end # Mouse device pnp 2e.6 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 # ??? end end device pci 7.1 on end # IDE device pci 7.2 on end # USB device pci 7.3 on end # ACPI end end end chip cpu/intel/slot_2 end end Does that look correct? Also, a full boot log is attached. The PCI init _seems_ to work, at least partially. The current end of the story is that elfboot cannot find the payload, not sure why. Wrong PCI init? Wrong RAM init? Wrong payload location? Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

3 8

[LinuxBIOS] r2623 - in trunk/LinuxBIOSv2: src/mainboard/tyan/s1846 src/southbridge/intel/i82371eb targets/tyan/s1846
by svn＠openbios.org 03 May '07

03 May '07

Author: uwe Date: 2007-05-03 10:50:37 +0200 (Thu, 03 May 2007) New Revision: 2623 Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb Log: Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB, as that is not RAM but used for other stuff. First try at PCI init added to src/mainboard/tyan/s1846/Config.lb. Use a real payload (FILO) per default now. Note: this cannot boot a payload, yet, but it gets a lot further now. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-04-30 23:27:27 UTC (rev 2622) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-05-03 08:50:37 UTC (rev 2623) @@ -126,10 +126,37 @@ config chip.h # TODO. -chip northbridge/intel/i440bx - device pci_domain 0 on - end - chip cpu/intel/slot_2 - end +chip northbridge/intel/i440bx # Northbridge + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 off end # PCI bridge TODO: AGP bridge? + # device pci 7.0 on end # ISA bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge ??? + chip superio/nsc/pc87309 # Super I/O + device pnp 2e.0 on end # Floppy + device pnp 2e.1 on end # Parallel port + device pnp 2e.2 on end # Com2 + device pnp 2e.3 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on end # Power mgmt. + device pnp 2e.5 on end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 # ??? + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + end + end + end + chip cpu/intel/slot_2 + end end Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-04-30 23:27:27 UTC (rev 2622) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/auto.c 2007-05-03 08:50:37 UTC (rev 2623) @@ -49,6 +49,19 @@ #include "northbridge/intel/i440bx/debug.c" #include "sdram/generic_sdram.c" +static void enable_mainboard_devices(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0); + + if (dev == PCI_DEV_INVALID) { + die("Southbridge not found!\n"); + } else { + print_debug("Southbridge found!\n"); + } +} + static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { @@ -75,12 +88,27 @@ /* Halt if there was a built in self test failure. */ report_bist_failure(bist); + enable_mainboard_devices(); + enable_smbus(); dump_spd_registers(&memctrl[0]); sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); - /* Check 64 MB of RAM. */ - ram_check(0x00000000, 0x04000000); + /* Check whether RAM is working. + * + * Do _not_ check the area from 640 KB - 1 MB, as that's not really + * RAM, but rather reserved for various other things: + * + * - 640 KB 768 KB: Video Buffer Area + * - 768 KB 896 KB: Expansion Area + * - 896 KB 960 KB: Extended System BIOS Area + * - 960 KB 1 MB: Memory (BIOS Area) - System BIOS Area + * + * Trying to check these areas will fail. + */ + /* TODO: This is currently hardcoded to check 64 MB. */ + ram_check(0x00000000, 0x0009ffff); /* 0 - 640 KB */ + ram_check(0x00100000, 0x007c0000); /* 1 MB - 64 MB */ } Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb 2007-05-03 08:50:37 UTC (rev 2623) @@ -0,0 +1,25 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h + +driver i82371eb.o +driver i82371eb_smbus.o + Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c 2007-05-03 08:50:37 UTC (rev 2623) @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "i82371eb.h" + +void i82371eb_enable(device_t dev) +{ + /* TODO. */ +} + +struct chip_operations southbridge_intel_i82371eb_ops = { + CHIP_NAME("Intel 82371EB Southbridge") + .enable_dev = i82371eb_enable, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-05-03 08:50:37 UTC (rev 2623) @@ -0,0 +1,32 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef I82371EB_H +#define I82371EB_H + +#ifndef __ROMCC__ + +#include "chip.h" + +void i82371eb_enable(device_t dev); + +#endif + +#endif /* I82371EB_H */ Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2007-04-30 23:27:27 UTC (rev 2622) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2007-05-03 08:50:37 UTC (rev 2623) @@ -39,5 +39,5 @@ static struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_INTEL_440BX_SMB, + .device = 0x7111, // FIXME? }; Modified: trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-04-30 23:27:27 UTC (rev 2622) +++ trunk/LinuxBIOSv2/targets/tyan/s1846/Config.lb 2007-05-03 08:50:37 UTC (rev 2623) @@ -25,14 +25,19 @@ romimage "normal" option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE=0x0e000 option LINUXBIOS_EXTRA_VERSION = ".0Normal" - payload /etc/hosts # TODO + payload /tmp/filo.elf + # payload /tmp/memtest end romimage "fallback" option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE=0x0e000 option LINUXBIOS_EXTRA_VERSION = ".0Fallback" - payload /etc/hosts # TODO + payload /tmp/filo.elf + # payload /tmp/memtest end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" +# buildrom ./linuxbios.rom ROM_SIZE "fallback"

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Re: [LinuxBIOS] Iwill DK8-HTX now runs under LinuxBIOS r2587 (Thanks)
by Ning (Michael) Qu 03 May '07

03 May '07

Hi, Alexei, Thanks for your posts on DK8-HTX. I am just starting working on this mainboard these two days. From what you said in your email, you modify several things I think, and most of them must be modified by lxbios, I try to summarize your work: 1 serial console baud_rate -> 115200 2 max_mem_clock -> 400MHz 3 boot_first ("HDD"), boot_second and boot_third ("Fallback_HDD"). I am not sure how to achieve the third one. Is it also in cmos? And another question is that I don't know how to dd a 36K Video ROM as you said. Do you just enlarge the size of dd? such as this? dd if=/dev/mem of=vgabios.bin skip=1536 count=72 Is that all the things you make LinuxBIOS run on DK8-HTX? Thanks for your help! Best Ning On Sat, Apr 21, 2007 at 03:33:30PM +0400, Alexei I. Adamovich wrote: > Looking at the serial console output after changing the boot_option > value to "Normal" and the debug_level value to "Spew" in the CMOS, > I've found that the system hangs near the very begining of load > process after trying to find some memory (dram0). Forgot to mention that to see the serial console output I also changed the baud_rate CMOS value to "115200"--since just this value was defined in the LinuxBios Config-s and I had set my serial console client (kermit) to wait connection just on this rate. Alexei I. Adamovich

2 4

[LinuxBIOS] Gigabyte M575SLI
by Kevin Adler 03 May '07

03 May '07

Hi, I've been watching this mailing list for a long time mostly to see the progress on the Gigabyte M575SLI and things seem to be looking very nice. I have 2 questions: how easy is it to build the LinuxBIOS and flash it without bricking it? (I've been looking at the sideproject here about using the extra bios socket, but my soldering skills are not very good and I don't have much in the way of decent soldering tools) and also, how easy is it to set what would be normal BIOS settings like voltage, cpu multipliers, etc... (For say overclocking a system) I've heard about a Google SoC project to get some sort of CMOS setup like interface after it is booted, but it seems you have to hard code these values in to the option file before you build the BIOS. Am I correct? And if so, what are all the options you can set? Many thanks Kevin

10 19

[LinuxBIOS] V-Link docs, datasheets, explanations, etc
by Corey Osgood 02 May '07

02 May '07

I've been Googling for anything relating to V-Link, either as a standard (preferably Via's version, if one exists) or some sort of explanation on setting it up. I've found nothing, in 18 pages, except lots of chipset feature pages and some MIDI info. Can anyone point me somewhere in the right direction? Basically, I just need to know if there's any need for any setup/calibration needed for V-Link to work, and if so, what the steps are (is it just setting the correct northbridge registers?). -Corey

1 0

[LinuxBIOS] Via EPIA-MII 12000 questions
by Martin Portmann 02 May '07

02 May '07

I am developing software for a VIA-EPIA-MII 12000 used in a CarPC project. At the moment I am using Fedora as operating system, directfb to access the screen and some self developed applications for audio, video and mapping. The actual boot-up times are about 20 seconds from the 2.5'' IDE drive. I would like to boot from a CompactFlash card in order to speed up the boot process and get a robuster sytem. So I as a newie I have some questions: [1] What are the tipical boot up times I can expect (striped down linux kernel, minimal startup scripts, no X11)? [2] If sombody from the community that has the same board (but possibly another revision) and gives me an working image to try how likely do I end up with a brick? [3] Any helps, tips, references to help me (I tried to google but did not find a lot, the actual documentation on LinuxBIOS is also quite confusing)? Best regards - Martin Portmann

2 1

Re: [LinuxBIOS] License header for src/cpu/amd/model_lx/syspreinit.c
by Jordan Crouse 02 May '07

02 May '07

This patch adds the common license header to src/cpu/amd/model_lx/syspreinit.c. The original authors are CCed, I would appreciate it if they would respond to this email with their agreement. Jordan -- Jordan Crouse Senior Linux Engineer Advanced Micro Devices, Inc. <www.amd.com/embeddedprocessors> Index: LinuxBIOSv2/src/cpu/amd/model_lx/syspreinit.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/syspreinit.c 2007-05-01 17:54:50.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/syspreinit.c 2007-05-01 17:55:32.000000000 -0600 @@ -1,3 +1,27 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Indrek Kruusa, indrek.kruusa(a)artecdesign.ee + * Ronald Minnich + * Copyright (C) 2007, Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* ***************************************************************************/ + /* ***************************************************************************/ /* **/ /* * StartTimer1*/

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coreboot May 2007