coreboot May 2007

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436 discussions

[LinuxBIOS] EPIA fix for non working IDE
by Ben Hewson 11 May '07

11 May '07

Hi all There has been a bug in the EPIA build which at some point stopped FILO being able to boot from an IDE drive. After much digging I have found the problem and have changed the following two files. LinuxBIOSv2/src/mainboard/via/epia/auto.c LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c I have also changed the default COM speed from 19200 to 115200. This is a personal thing but every time I update LB I forget to change it back. Leave it out if you wish. LinuxBIOSv2/src/mainboard/via/epia/Options.lb I have attached a patch file. Can someone please see about checking & adding the fixes to the repository. There is still an issue with the board sometimes hanging on boot. So I would not class this as fully working just yet. Regards Ben Hewson Index: /home/ben/sw/LinuxBIOSv2/src/mainboard/via/epia/auto.c =================================================================== --- /home/ben/sw/LinuxBIOSv2/src/mainboard/via/epia/auto.c (revision 2621) +++ /home/ben/sw/LinuxBIOSv2/src/mainboard/via/epia/auto.c (working copy) @@ -66,8 +66,16 @@ /* we do this here as in V2, we can not yet do raw operations * to pci! */ - dev += 0x100; /* ICKY */ - + + /* changed this to work correctly on later revisions of LB. + * The original dev += 0x100; stopped working. It also appears + * that if this is not set here, but in ide_init() only, the IDE + * does not work at all. I assume it needs to be set before something else, + * possibly before enabling the IDE peripheral, or it is a timing issue. + * Ben Hewson 29 Apr 2007. + */ + + dev = pci_locate_device(PCI_ID(0x1106,0x0571), 0); pci_write_config8(dev, 0x42, 0); } Index: /home/ben/sw/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c =================================================================== --- /home/ben/sw/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c (revision 2621) +++ /home/ben/sw/LinuxBIOSv2/src/southbridge/via/vt8231/vt8231_ide.c (working copy) @@ -15,6 +15,12 @@ // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI // interrupts. Using PCI ints confuses linux for some reason. + /* Setting reg 0x42 here does not work. It is set in mainboard/auto.c + * It probably can only be changed while the IDE is disabled + * or it is possibly a timing issue. Ben Hewson29 Apr 2007. + */ + + /* printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__); enables = pci_read_config8(dev, 0x42); printk_debug("enables in reg 0x42 0x%x\n", enables); @@ -22,6 +28,8 @@ pci_write_config8(dev, 0x42, enables); enables = pci_read_config8(dev, 0x42); printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + */ + } enables = pci_read_config8(dev, 0x40); Index: /home/ben/sw/LinuxBIOSv2/src/mainboard/via/epia/Options.lb =================================================================== --- /home/ben/sw/LinuxBIOSv2/src/mainboard/via/epia/Options.lb (revision 2621) +++ /home/ben/sw/LinuxBIOSv2/src/mainboard/via/epia/Options.lb (working copy) @@ -51,7 +51,7 @@ default CONFIG_CONSOLE_SERIAL8250=1 ## Select the serial console baud rate -default TTYS0_BAUD=19200 +default TTYS0_BAUD=115200 # Select the serial console base port default TTYS0_BASE=0x3f8

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[LinuxBIOS] [PATCH 1/3] Geode file updates based on code review comments
by Marc Jones 11 May '07

11 May '07

This patch cleans up and clarifies Geode source code comments. Signed-off-by: Marc Jones <marc.jones(a)amd.com> -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Index: LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/cpureginit.c 2007-05-10 16:06:07.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c 2007-05-10 15:09:12.000000000 -0600 @@ -101,11 +101,6 @@ ;1 16 400MHz 0x82*10055 0x56960004 4 ; ;2 4,4 400MHz 0x82710000 0x56960004 4 -;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -; -;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** ; ;1 4 <=333MHz 0x83*100FF 0x56960004 3 ;1 8 <=333MHz 0x83*100AA 0x56960004 3 @@ -114,9 +109,6 @@ ;2 4,4 <=333MHz 0x837100A5 0x56960004 3 ;2 8,8 <=333MHz 0x937100A5 0x56960004 3 ; -;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** ;========================================================================= ;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0, ; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1. @@ -130,9 +122,9 @@ ; DIMM Max MBUS ;DIMMs devices Frequency MCP 0x4C00000F Setting ;----- ------- --------- ---------------------- -;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa. -;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change, -;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side. +;1 4 400MHz 0xF2F100FF 0x56960004 4 The No VTT changes improve timing. +;1 8 400MHz 0xF2F100FF 0x56960004 4 +;1 4 <=333MHz 0xF2F100FF 0x56960004 3 ;1 8 <=333MHz 0xF2F100FF 0x56960004 3 ;1 16 <=333MHz 0xF2F100FF 0x56960004 3 */ @@ -233,8 +225,8 @@ wrmsr(msrnum, msr); /* - ; Castle performance setting. - ; Enable Quack for fewer re-RAS on the MC + * LX performance setting. + * Enable Quack for fewer re-RAS on the MC */ msrnum = GLIU0_ARB; msr = rdmsr(msrnum); Index: LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c =================================================================== --- LinuxBIOSv2.orig/src/cpu/amd/model_lx/vsmsetup.c 2007-05-10 16:09:35.000000000 -0600 +++ LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 2007-05-10 15:30:05.000000000 -0600 @@ -142,7 +142,8 @@ /* save the stack */ " mov %%esp, __stack \n" " jmp 1f \n" - "__stack: .long 0 \n" "1:\n" + "__stack: .long 0 \n" + "1:\n" /* get devfn into %%ecx */ " movl %%esp, %%ebp \n" #if 0 @@ -289,8 +290,7 @@ /* this is the base of rom on the LX at present. At some point, this has to be * much better parameterized */ - /* the VSA starts at the base of rom - 64 */ - //rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); + //VSA is cat onto the end after LB builds rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024); buf = (unsigned char *)VSA2_BUFFER; @@ -389,7 +389,8 @@ "callbiosint16: \n" " push %ds \n" " push %es \n" - " push %fs \n" " push %gs \n" + " push %fs \n" + " push %gs \n" // clean up the int #. To save space we put it in the lower // byte. But the top 24 bits are junk. " andl $0xff, %eax\n" @@ -464,7 +465,8 @@ " pop %ds \n" " popal \n" " iret \n" - " .code32 \n"); + " .code32 \n" + ); } enum { @@ -510,7 +512,7 @@ // cases in a good compiler are just as good as your own tables. switch (intnumber) { - case 0...15: + case 0 ... 15: // These are not BIOS service, but the CPU-generated exceptions printk_info("biosint: Oops, exception %u\n", intnumber); if (esp < 0x1000) { Index: LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h =================================================================== --- LinuxBIOSv2.orig/src/include/cpu/amd/geode_post_code.h 2007-05-10 16:11:00.000000000 -0600 +++ LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h 2007-05-10 15:14:52.000000000 -0600 @@ -19,178 +19,178 @@ /* standard AMD post definitions -- might as well use them. */ #define POST_Output_Port (0x080) /* port to write post codes to*/ -#define POST_preSioInit (0x000) /* geode.asm*/ -#define POST_clockInit (0x001) /* geode.asm*/ -#define POST_CPURegInit (0x002) /* geode.asm*/ -#define POST_UNREAL (0x003) /* geode.asm*/ -#define POST_CPUMemRegInit (0x004) /* geode.asm*/ -#define POST_CPUTest (0x005) /* geode.asm*/ -#define POST_memSetup (0x006) /* geode.asm*/ -#define POST_memSetUpStack (0x007) /* geode.asm*/ -#define POST_memTest (0x008) /* geode.asm*/ -#define POST_shadowRom (0x009) /* geode.asm*/ -#define POST_memRAMoptimize (0x00A) /* geode.asm*/ -#define POST_cacheInit (0x00B) /* geode.asm*/ -#define POST_northBridgeInit (0x00C) /* geode.asm*/ -#define POST_chipsetInit (0x00D) /* geode.asm*/ -#define POST_sioTest (0x00E) /* geode.asm*/ -#define POST_pcATjunk (0x00F) /* geode.asm*/ - - -#define POST_intTable (0x010) /* geode.asm*/ -#define POST_memInfo (0x011) /* geode.asm*/ -#define POST_romCopy (0x012) /* geode.asm*/ -#define POST_PLLCheck (0x013) /* geode.asm*/ -#define POST_keyboardInit (0x014) /* geode.asm*/ -#define POST_cpuCacheOff (0x015) /* geode.asm*/ -#define POST_BDAInit (0x016) /* geode.asm*/ -#define POST_pciScan (0x017) /* geode.asm*/ -#define POST_optionRomInit (0x018) /* geode.asm*/ -#define POST_ResetLimits (0x019) /* geode.asm*/ -#define POST_summary_screen (0x01A) /* geode.asm*/ -#define POST_Boot (0x01B) /* geode.asm*/ -#define POST_SystemPreInit (0x01C) /* geode.asm*/ -#define POST_ClearRebootFlag (0x01D) /* geode.asm*/ -#define POST_GLIUInit (0x01E) /* geode.asm*/ -#define POST_BootFailed (0x01F) /* geode.asm*/ - - -#define POST_CPU_ID (0x020) /* cpucpuid.asm*/ -#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ -#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ -#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ -#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ -#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ -#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ -#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ -#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ -#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ -#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ -#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ -#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ -#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ -#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ -#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ +#define POST_preSioInit (0x000) +#define POST_clockInit (0x001) +#define POST_CPURegInit (0x002) +#define POST_UNREAL (0x003) +#define POST_CPUMemRegInit (0x004) +#define POST_CPUTest (0x005) +#define POST_memSetup (0x006) +#define POST_memSetUpStack (0x007) +#define POST_memTest (0x008) +#define POST_shadowRom (0x009) +#define POST_memRAMoptimize (0x00A) +#define POST_cacheInit (0x00B) +#define POST_northBridgeInit (0x00C) +#define POST_chipsetInit (0x00D) +#define POST_sioTest (0x00E) +#define POST_pcATjunk (0x00F) + + +#define POST_intTable (0x010) +#define POST_memInfo (0x011) +#define POST_romCopy (0x012) +#define POST_PLLCheck (0x013) +#define POST_keyboardInit (0x014) +#define POST_cpuCacheOff (0x015) +#define POST_BDAInit (0x016) +#define POST_pciScan (0x017) +#define POST_optionRomInit (0x018) +#define POST_ResetLimits (0x019) +#define POST_summary_screen (0x01A) +#define POST_Boot (0x01B) +#define POST_SystemPreInit (0x01C) +#define POST_ClearRebootFlag (0x01D) +#define POST_GLIUInit (0x01E) +#define POST_BootFailed (0x01F) + + +#define POST_CPU_ID (0x020) +#define POST_COUNTERBROKEN (0x021) +#define POST_DIFF_DIMMS (0x022) +#define POST_WIGGLE_MEM_LINES (0x023) +#define POST_NO_GLIU_DESC (0x024) +#define POST_CPU_LCD_CHECK (0x025) +#define POST_CPU_LCD_PASS (0x026) +#define POST_CPU_LCD_FAIL (0x027) +#define POST_CPU_STEPPING (0x028) +#define POST_CPU_DM_BIST_FAILURE (0x029) +#define POST_CPU_FLAGS (0x02A) +#define POST_CHIPSET_ID (0x02b) +#define POST_CHIPSET_ID_PASS (0x02c) +#define POST_CHIPSET_ID_FAIL (0x02d) +#define POST_CPU_ID_GOOD (0x02E) +#define POST_CPU_ID_FAIL (0x02F) /* PCI config*/ -#define P80_PCICFG (0x030) /* pcispace.asm*/ +#define P80_PCICFG (0x030) /* PCI io*/ -#define P80_PCIIO (0x040) /* pcispace.asm*/ +#define P80_PCIIO (0x040) /* PCI memory*/ -#define P80_PCIMEM (0x050) /* pcispace.asm*/ +#define P80_PCIMEM (0x050) /* SIO*/ -#define P80_SIO (0x060) /* *sio.asm*/ +#define P80_SIO (0x060) /* Memory Setp*/ -#define P80_MEM_SETUP (0x070) /* docboot meminit*/ -#define POST_MEM_SETUP (0x070) /* memsize.asm*/ -#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ -#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ -#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ -#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ -#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ -#define POST_MEM_ENABLE (0x076) /* memsize.asm*/ -#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ -#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ -#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ -#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ -#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ -#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ -#define ERROR_BANK_SET (0x07d) /* memsize.asm*/ -#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ -#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ - - -#define POST_UserPreInit (0x080) /* geode.asm*/ -#define POST_UserPostInit (0x081) /* geode.asm*/ -#define POST_Equipment_check (0x082) /* geode.asm*/ -#define POST_InitNVRAMBX (0x083) /* geode.asm*/ -#define POST_NoPIRTable (0x084) /* pci.asm*/ -#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ -#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ -#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ -#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ -#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ -#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ -#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ - - -#define POST_STACK_SETUP (0x090) /* memstack.asm*/ -#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ -#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ -#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ -#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ -#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ -#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ -#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ -#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ - - -#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ -#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ -#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ -#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ -#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ -#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ -#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ - - -#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ -#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ -#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ -#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ -#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ -#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ -#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ - - -#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ -#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ -#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ -#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ -#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ - -#define POST_RCONFInitError (0x0CE) /* cache.asm*/ -#define POST_CacheInitError (0x0CF) /* cache.asm*/ - - -#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ -#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ -#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ -#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ -#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ -#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ -#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ -#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ -#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ -#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ +#define P80_MEM_SETUP (0x070) +#define POST_MEM_SETUP (0x070) +#define ERROR_32BIT_DIMMS (0x071) +#define POST_MEM_SETUP2 (0x072) +#define POST_MEM_SETUP3 (0x073) +#define POST_MEM_SETUP4 (0x074) +#define POST_MEM_SETUP5 (0x075) +#define POST_MEM_ENABLE (0x076) +#define ERROR_NO_DIMMS (0x077) +#define ERROR_DIFF_DIMMS (0x078) +#define ERROR_BAD_LATENCY (0x079) +#define ERROR_SET_PAGE (0x07a) +#define ERROR_DENSITY_DIMM (0x07b) +#define ERROR_UNSUPPORTED_DIMM (0x07c) +#define ERROR_BANK_SET (0x07d) +#define POST_MEM_SETUP_GOOD (0x07E) +#define POST_MEM_SETUP_FAIL (0x07F) + + +#define POST_UserPreInit (0x080) +#define POST_UserPostInit (0x081) +#define POST_Equipment_check (0x082) +#define POST_InitNVRAMBX (0x083) +#define POST_NoPIRTable (0x084) +#define POST_ChipsetFingerPrintPass (0x085) +#define POST_ChipsetFingerPrintFail (0x086) +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) +#define POST_CPU_FPU_BIST_FAILURE (0x089) +#define POST_CPU_BTB_BIST_FAILURE (0x08a) +#define POST_CPU_EX_BIST_FAILURE (0x08b) +#define POST_Chipset_PI_Test_Fail (0x08c) +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) +#define POST_BIT_CLK_Fail (0x08e) + + +#define POST_STACK_SETUP (0x090) +#define POST_CPU_PF_BIST_FAILURE (0x091) +#define POST_CPU_L2_BIST_FAILURE (0x092) +#define POST_CPU_GLCP_BIST_FAILURE (0x093) +#define POST_CPU_DF_BIST_FAILURE (0x094) +#define POST_CPU_VG_BIST_FAILURE (0x095) +#define POST_CPU_VIP_BIST_FAILURE (0x096) +#define POST_STACK_SETUP_PASS (0x09E) +#define POST_STACK_SETUP_FAIL (0x09F) + + +#define POST_PLL_INIT (0x0A0) +#define POST_PLL_MANUAL (0x0A1) +#define POST_PLL_STRAP (0x0A2) +#define POST_PLL_RESET_FAIL (0x0A3) +#define POST_PLL_PCI_FAIL (0x0A4) +#define POST_PLL_MEM_FAIL (0x0A5) +#define POST_PLL_CPU_VER_FAIL (0x0A6) + + +#define POST_MEM_TESTMEM (0x0B0) +#define POST_MEM_TESTMEM1 (0x0B1) +#define POST_MEM_TESTMEM2 (0x0B2) +#define POST_MEM_TESTMEM3 (0x0B3) +#define POST_MEM_TESTMEM4 (0x0B4) +#define POST_MEM_TESTMEM_PASS (0x0BE) +#define POST_MEM_TESTMEM_FAIL (0x0BF) + + +#define POST_SECUROM_SECBOOT_START (0x0C0) +#define POST_SECUROM_BOOTSRCSETUP (0x0C1) +#define POST_SECUROM_REMAP_FAIL (0x0C2) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_DCACHESETUP (0x0C4) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_ICACHESETUP (0x0C6) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_PLATFORMSETUP (0x0C9) +#define POST_SECUROM_SIGCHECKBIOS (0x0CA) +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) +#define POST_SECUROM_PASS (0x0CC) +#define POST_SECUROM_FAIL (0x0CD) + +#define POST_RCONFInitError (0x0CE) +#define POST_CacheInitError (0x0CF) + + +#define POST_ROM_PREUNCOMPRESS (0x0D0) +#define POST_ROM_UNCOMPRESS (0x0D1) +#define POST_ROM_SMM_INIT (0x0D2) +#define POST_ROM_VID_BIOS (0x0D3) +#define POST_ROM_LCDINIT (0x0D4) +#define POST_ROM_SPLASH (0x0D5) +#define POST_ROM_HDDINIT (0x0D6) +#define POST_ROM_SYS_INIT (0x0D7) +#define POST_ROM_DMM_INIT (0x0D8) +#define POST_ROM_TVINIT (0x0D9) #define POST_ROM_POSTUNCOMPRESS (0x0DE) -#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ -#define POST_PreChipsetInit (0x0E1) /* geode.asm*/ -#define POST_LateChipsetInit (0x0E2) /* geode.asm*/ -#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ +#define P80_CHIPSET_INIT (0x0E0) +#define POST_PreChipsetInit (0x0E1) +#define POST_LateChipsetInit (0x0E2) +#define POST_NORTHB_INIT (0x0E8) -#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ +#define POST_INTR_SEG_JUMP (0x0F0) Index: LinuxBIOSv2/src/include/cpu/amd/vr.h =================================================================== --- LinuxBIOSv2.orig/src/include/cpu/amd/vr.h 2007-05-10 16:11:46.000000000 -0600 +++ LinuxBIOSv2/src/include/cpu/amd/vr.h 2007-05-10 15:16:22.000000000 -0600 @@ -476,8 +476,6 @@ /* * Write to a Virtual Register - * AX = Class/Index - * CX = data to write */ static inline void vrWrite(uint16_t wClassIndex, uint16_t wData) { @@ -487,7 +485,6 @@ /* * Read from a Virtual Register - * AX = Class/Index * Returns a 16-bit word of data */ static inline uint16_t vrRead(uint16_t wClassIndex) Index: LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/northbridge.c 2007-05-10 16:13:06.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-10 15:18:39.000000000 -0600 @@ -127,6 +127,7 @@ int sizem = 0; unsigned short dimm; + /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ msr = rdmsr(MC_CF07_DATA); printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); @@ -134,14 +135,14 @@ dimm = msr.hi; /* installed? */ if ((dimm & 7) != 7) { - sizem = 4 << ((dimm >> 12) & 0x0F); + sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ } /* dimm 1 */ dimm = msr.hi >> 16; /* installed? */ if ((dimm & 7) != 7) { - sizem += 4 << ((dimm >> 12) & 0x0F); + sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ } printk_debug("sizeram: sizem 0x%xMB\n", sizem); Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536.c 2007-05-10 16:15:32.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 2007-05-10 15:20:21.000000000 -0600 @@ -131,14 +131,12 @@ /* PM_SED */ port = (PMS_IO_BASE + 0x014); -/* mov eax, 0x057642 ; 100ms, works*/ - val = 0x04601; /* 5ms */ + val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */ outl(val, port); /* PM_SIDD */ port = (PMS_IO_BASE + 0x020); -/* mov eax, 0x0AEC84 ; 200ms, works*/ - val = 0x08C02; /* 10ms */ + val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */ outl(val, port); } Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_early_setup.c 2007-05-10 16:16:53.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 2007-05-10 15:32:40.000000000 -0600 @@ -97,10 +97,10 @@ /* Power Button Setup */ outl(0x40020000, PMS_IO_BASE + 0x40); - /* setup GPIO24, it is the external signal for 5536 vsb_work_aux - * which controls all voltage rails except Vstandby & Vmem. + /* setup WORK_AUX/GPIO24, it is the external signal for 5536 + * vsb_work_aux controls all voltage rails except Vstandby & Vmem. * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. - * If GPIO24 is not enabled then soft-off will not work. + * If WORK_AUX/GPIO24 is not enabled then soft-off will not work. */ outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); @@ -127,7 +127,7 @@ { msr_t msr; /* The UARTs default to enabled. - * Disable and reset them and configure them later. (SIO init) + * Disable and reset them and configure them later. (SIO init) */ msr = rdmsr(MDD_UART1_CONF); msr.lo = 1; // reset

2 2

[LinuxBIOS] r2658 - in trunk/LinuxBIOSv2/src: cpu/amd/model_lx include/cpu/amd northbridge/amd/lx southbridge/amd/cs5536
by svn＠openbios.org 11 May '07

11 May '07

Author: stepan Date: 2007-05-11 01:22:27 +0200 (Fri, 11 May 2007) New Revision: 2658 Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c trunk/LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h trunk/LinuxBIOSv2/src/include/cpu/amd/vr.h trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c Log: This patch cleans up and clarifies Geode source code comments. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_lx/cpureginit.c 2007-05-10 23:22:27 UTC (rev 2658) @@ -101,12 +101,7 @@ ;1 16 400MHz 0x82*10055 0x56960004 4 ; ;2 4,4 400MHz 0x82710000 0x56960004 4 -;2 8,8 400MHz 0xC27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** ; -;2 16,4 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 >333 0xB27100A5 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 >333 0xB2710000 0x56960004 4 *** OUT OF PUBLISHED ENVELOPE *** -; ;1 4 <=333MHz 0x83*100FF 0x56960004 3 ;1 8 <=333MHz 0x83*100AA 0x56960004 3 ;1 16 <=333MHz 0x83*100AA 0x56960004 3 @@ -114,9 +109,6 @@ ;2 4,4 <=333MHz 0x837100A5 0x56960004 3 ;2 8,8 <=333MHz 0x937100A5 0x56960004 3 ; -;2 16,4 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,8 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** -;2 16,16 <=333MHz 0xB37100A5 0x56960004 3 *** OUT OF PUBLISHED ENVELOPE *** ;========================================================================= ;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0, ; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1. @@ -130,9 +122,9 @@ ; DIMM Max MBUS ;DIMMs devices Frequency MCP 0x4C00000F Setting ;----- ------- --------- ---------------------- -;1 4 400MHz 0xF2F100FF 0x56960004 4 The MC changes improve Salsa. -;1 8 400MHz 0xF2F100FF 0x56960004 4 Delay controls no real change, -;1 4 <=333MHz 0xF2F100FF 0x56960004 3 just fixing typo in left side. +;1 4 400MHz 0xF2F100FF 0x56960004 4 The No VTT changes improve timing. +;1 8 400MHz 0xF2F100FF 0x56960004 4 +;1 4 <=333MHz 0xF2F100FF 0x56960004 3 ;1 8 <=333MHz 0xF2F100FF 0x56960004 3 ;1 16 <=333MHz 0xF2F100FF 0x56960004 3 */ @@ -233,8 +225,8 @@ wrmsr(msrnum, msr); /* - ; Castle performance setting. - ; Enable Quack for fewer re-RAS on the MC + * LX performance setting. + * Enable Quack for fewer re-RAS on the MC */ msrnum = GLIU0_ARB; msr = rdmsr(msrnum); Modified: trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/cpu/amd/model_lx/vsmsetup.c 2007-05-10 23:22:27 UTC (rev 2658) @@ -290,8 +290,7 @@ /* this is the base of rom on the LX at present. At some point, this has to be * much better parameterized */ - /* the VSA starts at the base of rom - 64 */ - //rom = ((unsigned long) 0) - (ROM_SIZE + 64*1024); + //VSA is cat onto the end after LB builds rom = ((unsigned long)0) - (ROM_SIZE + 36 * 1024); buf = (unsigned char *)VSA2_BUFFER; Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/geode_post_code.h 2007-05-10 23:22:27 UTC (rev 2658) @@ -19,178 +19,178 @@ /* standard AMD post definitions -- might as well use them. */ #define POST_Output_Port (0x080) /* port to write post codes to*/ -#define POST_preSioInit (0x000) /* geode.asm*/ -#define POST_clockInit (0x001) /* geode.asm*/ -#define POST_CPURegInit (0x002) /* geode.asm*/ -#define POST_UNREAL (0x003) /* geode.asm*/ -#define POST_CPUMemRegInit (0x004) /* geode.asm*/ -#define POST_CPUTest (0x005) /* geode.asm*/ -#define POST_memSetup (0x006) /* geode.asm*/ -#define POST_memSetUpStack (0x007) /* geode.asm*/ -#define POST_memTest (0x008) /* geode.asm*/ -#define POST_shadowRom (0x009) /* geode.asm*/ -#define POST_memRAMoptimize (0x00A) /* geode.asm*/ -#define POST_cacheInit (0x00B) /* geode.asm*/ -#define POST_northBridgeInit (0x00C) /* geode.asm*/ -#define POST_chipsetInit (0x00D) /* geode.asm*/ -#define POST_sioTest (0x00E) /* geode.asm*/ -#define POST_pcATjunk (0x00F) /* geode.asm*/ +#define POST_preSioInit (0x000) +#define POST_clockInit (0x001) +#define POST_CPURegInit (0x002) +#define POST_UNREAL (0x003) +#define POST_CPUMemRegInit (0x004) +#define POST_CPUTest (0x005) +#define POST_memSetup (0x006) +#define POST_memSetUpStack (0x007) +#define POST_memTest (0x008) +#define POST_shadowRom (0x009) +#define POST_memRAMoptimize (0x00A) +#define POST_cacheInit (0x00B) +#define POST_northBridgeInit (0x00C) +#define POST_chipsetInit (0x00D) +#define POST_sioTest (0x00E) +#define POST_pcATjunk (0x00F) -#define POST_intTable (0x010) /* geode.asm*/ -#define POST_memInfo (0x011) /* geode.asm*/ -#define POST_romCopy (0x012) /* geode.asm*/ -#define POST_PLLCheck (0x013) /* geode.asm*/ -#define POST_keyboardInit (0x014) /* geode.asm*/ -#define POST_cpuCacheOff (0x015) /* geode.asm*/ -#define POST_BDAInit (0x016) /* geode.asm*/ -#define POST_pciScan (0x017) /* geode.asm*/ -#define POST_optionRomInit (0x018) /* geode.asm*/ -#define POST_ResetLimits (0x019) /* geode.asm*/ -#define POST_summary_screen (0x01A) /* geode.asm*/ -#define POST_Boot (0x01B) /* geode.asm*/ -#define POST_SystemPreInit (0x01C) /* geode.asm*/ -#define POST_ClearRebootFlag (0x01D) /* geode.asm*/ -#define POST_GLIUInit (0x01E) /* geode.asm*/ -#define POST_BootFailed (0x01F) /* geode.asm*/ +#define POST_intTable (0x010) +#define POST_memInfo (0x011) +#define POST_romCopy (0x012) +#define POST_PLLCheck (0x013) +#define POST_keyboardInit (0x014) +#define POST_cpuCacheOff (0x015) +#define POST_BDAInit (0x016) +#define POST_pciScan (0x017) +#define POST_optionRomInit (0x018) +#define POST_ResetLimits (0x019) +#define POST_summary_screen (0x01A) +#define POST_Boot (0x01B) +#define POST_SystemPreInit (0x01C) +#define POST_ClearRebootFlag (0x01D) +#define POST_GLIUInit (0x01E) +#define POST_BootFailed (0x01F) -#define POST_CPU_ID (0x020) /* cpucpuid.asm*/ -#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ -#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ -#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ -#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ -#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ -#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ -#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ -#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ -#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ -#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ -#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ -#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ -#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ -#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ -#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ +#define POST_CPU_ID (0x020) +#define POST_COUNTERBROKEN (0x021) +#define POST_DIFF_DIMMS (0x022) +#define POST_WIGGLE_MEM_LINES (0x023) +#define POST_NO_GLIU_DESC (0x024) +#define POST_CPU_LCD_CHECK (0x025) +#define POST_CPU_LCD_PASS (0x026) +#define POST_CPU_LCD_FAIL (0x027) +#define POST_CPU_STEPPING (0x028) +#define POST_CPU_DM_BIST_FAILURE (0x029) +#define POST_CPU_FLAGS (0x02A) +#define POST_CHIPSET_ID (0x02b) +#define POST_CHIPSET_ID_PASS (0x02c) +#define POST_CHIPSET_ID_FAIL (0x02d) +#define POST_CPU_ID_GOOD (0x02E) +#define POST_CPU_ID_FAIL (0x02F) /* PCI config*/ -#define P80_PCICFG (0x030) /* pcispace.asm*/ +#define P80_PCICFG (0x030) /* PCI io*/ -#define P80_PCIIO (0x040) /* pcispace.asm*/ +#define P80_PCIIO (0x040) /* PCI memory*/ -#define P80_PCIMEM (0x050) /* pcispace.asm*/ +#define P80_PCIMEM (0x050) /* SIO*/ -#define P80_SIO (0x060) /* *sio.asm*/ +#define P80_SIO (0x060) /* Memory Setp*/ -#define P80_MEM_SETUP (0x070) /* docboot meminit*/ -#define POST_MEM_SETUP (0x070) /* memsize.asm*/ -#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ -#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ -#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ -#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ -#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ -#define POST_MEM_ENABLE (0x076) /* memsize.asm*/ -#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ -#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ -#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ -#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ -#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ -#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ -#define ERROR_BANK_SET (0x07d) /* memsize.asm*/ -#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ -#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ +#define P80_MEM_SETUP (0x070) +#define POST_MEM_SETUP (0x070) +#define ERROR_32BIT_DIMMS (0x071) +#define POST_MEM_SETUP2 (0x072) +#define POST_MEM_SETUP3 (0x073) +#define POST_MEM_SETUP4 (0x074) +#define POST_MEM_SETUP5 (0x075) +#define POST_MEM_ENABLE (0x076) +#define ERROR_NO_DIMMS (0x077) +#define ERROR_DIFF_DIMMS (0x078) +#define ERROR_BAD_LATENCY (0x079) +#define ERROR_SET_PAGE (0x07a) +#define ERROR_DENSITY_DIMM (0x07b) +#define ERROR_UNSUPPORTED_DIMM (0x07c) +#define ERROR_BANK_SET (0x07d) +#define POST_MEM_SETUP_GOOD (0x07E) +#define POST_MEM_SETUP_FAIL (0x07F) -#define POST_UserPreInit (0x080) /* geode.asm*/ -#define POST_UserPostInit (0x081) /* geode.asm*/ -#define POST_Equipment_check (0x082) /* geode.asm*/ -#define POST_InitNVRAMBX (0x083) /* geode.asm*/ -#define POST_NoPIRTable (0x084) /* pci.asm*/ -#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ -#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ -#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ -#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ -#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ -#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ -#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ -#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ -#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ -#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ +#define POST_UserPreInit (0x080) +#define POST_UserPostInit (0x081) +#define POST_Equipment_check (0x082) +#define POST_InitNVRAMBX (0x083) +#define POST_NoPIRTable (0x084) +#define POST_ChipsetFingerPrintPass (0x085) +#define POST_ChipsetFingerPrintFail (0x086) +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) +#define POST_CPU_FPU_BIST_FAILURE (0x089) +#define POST_CPU_BTB_BIST_FAILURE (0x08a) +#define POST_CPU_EX_BIST_FAILURE (0x08b) +#define POST_Chipset_PI_Test_Fail (0x08c) +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) +#define POST_BIT_CLK_Fail (0x08e) -#define POST_STACK_SETUP (0x090) /* memstack.asm*/ -#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ -#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ -#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ -#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ -#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ -#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ -#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ -#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ +#define POST_STACK_SETUP (0x090) +#define POST_CPU_PF_BIST_FAILURE (0x091) +#define POST_CPU_L2_BIST_FAILURE (0x092) +#define POST_CPU_GLCP_BIST_FAILURE (0x093) +#define POST_CPU_DF_BIST_FAILURE (0x094) +#define POST_CPU_VG_BIST_FAILURE (0x095) +#define POST_CPU_VIP_BIST_FAILURE (0x096) +#define POST_STACK_SETUP_PASS (0x09E) +#define POST_STACK_SETUP_FAIL (0x09F) -#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ -#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ -#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ -#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ -#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ -#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ -#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ +#define POST_PLL_INIT (0x0A0) +#define POST_PLL_MANUAL (0x0A1) +#define POST_PLL_STRAP (0x0A2) +#define POST_PLL_RESET_FAIL (0x0A3) +#define POST_PLL_PCI_FAIL (0x0A4) +#define POST_PLL_MEM_FAIL (0x0A5) +#define POST_PLL_CPU_VER_FAIL (0x0A6) -#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ -#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ -#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ -#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ -#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ -#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ -#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ +#define POST_MEM_TESTMEM (0x0B0) +#define POST_MEM_TESTMEM1 (0x0B1) +#define POST_MEM_TESTMEM2 (0x0B2) +#define POST_MEM_TESTMEM3 (0x0B3) +#define POST_MEM_TESTMEM4 (0x0B4) +#define POST_MEM_TESTMEM_PASS (0x0BE) +#define POST_MEM_TESTMEM_FAIL (0x0BF) -#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ -#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ -#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ -#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ -#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ -#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ -#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ -#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ -#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ -#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ +#define POST_SECUROM_SECBOOT_START (0x0C0) +#define POST_SECUROM_BOOTSRCSETUP (0x0C1) +#define POST_SECUROM_REMAP_FAIL (0x0C2) +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) +#define POST_SECUROM_DCACHESETUP (0x0C4) +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) +#define POST_SECUROM_ICACHESETUP (0x0C6) +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) +#define POST_SECUROM_PLATFORMSETUP (0x0C9) +#define POST_SECUROM_SIGCHECKBIOS (0x0CA) +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) +#define POST_SECUROM_PASS (0x0CC) +#define POST_SECUROM_FAIL (0x0CD) -#define POST_RCONFInitError (0x0CE) /* cache.asm*/ -#define POST_CacheInitError (0x0CF) /* cache.asm*/ +#define POST_RCONFInitError (0x0CE) +#define POST_CacheInitError (0x0CF) -#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ -#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ -#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ -#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ -#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ -#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ -#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ -#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ -#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ -#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ +#define POST_ROM_PREUNCOMPRESS (0x0D0) +#define POST_ROM_UNCOMPRESS (0x0D1) +#define POST_ROM_SMM_INIT (0x0D2) +#define POST_ROM_VID_BIOS (0x0D3) +#define POST_ROM_LCDINIT (0x0D4) +#define POST_ROM_SPLASH (0x0D5) +#define POST_ROM_HDDINIT (0x0D6) +#define POST_ROM_SYS_INIT (0x0D7) +#define POST_ROM_DMM_INIT (0x0D8) +#define POST_ROM_TVINIT (0x0D9) #define POST_ROM_POSTUNCOMPRESS (0x0DE) -#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ -#define POST_PreChipsetInit (0x0E1) /* geode.asm*/ -#define POST_LateChipsetInit (0x0E2) /* geode.asm*/ -#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ +#define P80_CHIPSET_INIT (0x0E0) +#define POST_PreChipsetInit (0x0E1) +#define POST_LateChipsetInit (0x0E2) +#define POST_NORTHB_INIT (0x0E8) -#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ +#define POST_INTR_SEG_JUMP (0x0F0) Modified: trunk/LinuxBIOSv2/src/include/cpu/amd/vr.h =================================================================== --- trunk/LinuxBIOSv2/src/include/cpu/amd/vr.h 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/include/cpu/amd/vr.h 2007-05-10 23:22:27 UTC (rev 2658) @@ -476,8 +476,6 @@ /* * Write to a Virtual Register - * AX = Class/Index - * CX = data to write */ static inline void vrWrite(uint16_t wClassIndex, uint16_t wData) { @@ -487,7 +485,6 @@ /* * Read from a Virtual Register - * AX = Class/Index * Returns a 16-bit word of data */ static inline uint16_t vrRead(uint16_t wClassIndex) Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/northbridge.c 2007-05-10 23:22:27 UTC (rev 2658) @@ -127,6 +127,7 @@ int sizem = 0; unsigned short dimm; + /* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */ msr = rdmsr(MC_CF07_DATA); printk_debug("sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo); @@ -134,14 +135,14 @@ dimm = msr.hi; /* installed? */ if ((dimm & 7) != 7) { - sizem = 4 << ((dimm >> 12) & 0x0F); + sizem = 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ } /* dimm 1 */ dimm = msr.hi >> 16; /* installed? */ if ((dimm & 7) != 7) { - sizem += 4 << ((dimm >> 12) & 0x0F); + sizem += 4 << ((dimm >> 12) & 0x0F); /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */ } printk_debug("sizeram: sizem 0x%xMB\n", sizem); Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536.c 2007-05-10 23:22:27 UTC (rev 2658) @@ -131,14 +131,12 @@ /* PM_SED */ port = (PMS_IO_BASE + 0x014); -/* mov eax, 0x057642 ; 100ms, works*/ - val = 0x04601; /* 5ms */ + val = 0x04601; /* 5ms, # of 3.57954MHz clock edges */ outl(val, port); /* PM_SIDD */ port = (PMS_IO_BASE + 0x020); -/* mov eax, 0x0AEC84 ; 200ms, works*/ - val = 0x08C02; /* 10ms */ + val = 0x08C02; /* 10ms, # of 3.57954MHz clock edges */ outl(val, port); } Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 2007-05-10 23:13:18 UTC (rev 2657) +++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_early_setup.c 2007-05-10 23:22:27 UTC (rev 2658) @@ -97,10 +97,10 @@ /* Power Button Setup */ outl(0x40020000, PMS_IO_BASE + 0x40); - /* setup GPIO24, it is the external signal for 5536 vsb_work_aux - * which controls all voltage rails except Vstandby & Vmem. + /* setup WORK_AUX/GPIO24, it is the external signal for 5536 + * vsb_work_aux controls all voltage rails except Vstandby & Vmem. * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order. - * If GPIO24 is not enabled then soft-off will not work. + * If WORK_AUX/GPIO24 is not enabled then soft-off will not work. */ outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT); outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); @@ -127,7 +127,7 @@ { msr_t msr; /* The UARTs default to enabled. - * Disable and reset them and configure them later. (SIO init) + * Disable and reset them and configure them later. (SIO init) */ msr = rdmsr(MDD_UART1_CONF); msr.lo = 1; // reset

1 0

[LinuxBIOS] [PATCH 3/3] Geode file updates based on code review comments
by Marc Jones 11 May '07

11 May '07

This patch cleans up \r left in the print strings. They were required for romcc code but no longer needed in cache as ram code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Index: LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/raminit.c 2007-05-10 16:41:22.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-05-10 15:46:55.000000000 -0600 @@ -45,7 +45,7 @@ /* EEPROM byte usage: (5) Number of DIMM Banks */ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { - print_debug("Number of module banks not compatible\r\n"); + print_debug("Number of module banks not compatible\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } @@ -55,7 +55,7 @@ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { - print_debug("Number of device banks not compatible\r\n"); + print_debug("Number of device banks not compatible\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } @@ -70,7 +70,7 @@ */ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { - print_debug("Assymetirc DIMM not compatible\r\n"); + print_debug("Assymetirc DIMM not compatible\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); } @@ -83,7 +83,7 @@ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ dimm_size = __builtin_ctz(dimm_size); if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ - print_debug("Only support up to 1 GB per DIMM\r\n"); + print_debug("Only support up to 1 GB per DIMM\n"); POST_CODE(ERROR_DENSITY_DIMM); __asm__ __volatile__("hlt\n"); } @@ -114,7 +114,7 @@ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; if (spd_byte > MAX_COL_ADDR) { - print_debug("DIMM page size not compatible\r\n"); + print_debug("DIMM page size not compatible\n"); POST_CODE(ERROR_SET_PAGE); __asm__ __volatile__("hlt\n"); } @@ -152,7 +152,7 @@ /* I don't think you need this check. if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ - print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); + print_debug("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); __asm__ __volatile__("hlt\n"); } */ @@ -549,7 +549,7 @@ } spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES); if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_debug("DIMM1 NOT COMPATIBLE\r\n"); + print_debug("DIMM1 NOT COMPATIBLE\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); } @@ -718,7 +718,7 @@ msr.lo |= (209 << 8); /* bits[15:8] = 209 */ wrmsr(msrnum, msr); - print_debug("DRAM controller init done.\r\n"); + print_debug("DRAM controller init done.\n"); POST_CODE(POST_MEM_SETUP_GOOD); //0x7E /* make sure there is nothing stale in the cache */ @@ -750,6 +750,6 @@ msr.lo |= 1; wrmsr(msrnum, msr); } - print_debug("RAM DLL lock\r\n"); + print_debug("RAM DLL lock\n"); } Index: LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c =================================================================== --- LinuxBIOSv2.orig/src/northbridge/amd/lx/pll_reset.c 2007-05-10 16:41:12.000000000 -0600 +++ LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-10 15:47:28.000000000 -0600 @@ -30,7 +30,7 @@ print_debug_hex32(msrGlcpSysRstpll.hi); print_debug(":"); print_debug_hex32(msrGlcpSysRstpll.lo); - print_debug("\r\n"); + print_debug("\n"); POST_CODE(POST_PLL_INIT); if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {

2 1

[LinuxBIOS] r2657 - trunk/LinuxBIOSv2/src/northbridge/amd/lx
by svn＠openbios.org 11 May '07

11 May '07

Author: stuge Date: 2007-05-11 01:13:18 +0200 (Fri, 11 May 2007) New Revision: 2657 Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c Log: This patch cleans up \r left in the print strings. They were required for romcc code but no longer needed in cache as ram code. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-10 23:12:18 UTC (rev 2656) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/pll_reset.c 2007-05-10 23:13:18 UTC (rev 2657) @@ -30,7 +30,7 @@ print_debug_hex32(msrGlcpSysRstpll.hi); print_debug(":"); print_debug_hex32(msrGlcpSysRstpll.lo); - print_debug("\r\n"); + print_debug("\n"); POST_CODE(POST_PLL_INIT); if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { Modified: trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c =================================================================== --- trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-05-10 23:12:18 UTC (rev 2656) +++ trunk/LinuxBIOSv2/src/northbridge/amd/lx/raminit.c 2007-05-10 23:13:18 UTC (rev 2657) @@ -45,7 +45,7 @@ /* EEPROM byte usage: (5) Number of DIMM Banks */ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) { - print_debug("Number of module banks not compatible\r\n"); + print_debug("Number of module banks not compatible\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } @@ -55,7 +55,7 @@ /* EEPROM byte usage: (17) Number of Banks on SDRAM Device */ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) { - print_debug("Number of device banks not compatible\r\n"); + print_debug("Number of device banks not compatible\n"); POST_CODE(ERROR_BANK_SET); __asm__ __volatile__("hlt\n"); } @@ -70,7 +70,7 @@ */ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { - print_debug("Assymetirc DIMM not compatible\r\n"); + print_debug("Assymetirc DIMM not compatible\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); } @@ -83,7 +83,7 @@ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ dimm_size = __builtin_ctz(dimm_size); if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ - print_debug("Only support up to 1 GB per DIMM\r\n"); + print_debug("Only support up to 1 GB per DIMM\n"); POST_CODE(ERROR_DENSITY_DIMM); __asm__ __volatile__("hlt\n"); } @@ -114,7 +114,7 @@ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; if (spd_byte > MAX_COL_ADDR) { - print_debug("DIMM page size not compatible\r\n"); + print_debug("DIMM page size not compatible\n"); POST_CODE(ERROR_SET_PAGE); __asm__ __volatile__("hlt\n"); } @@ -152,7 +152,7 @@ /* I don't think you need this check. if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){ - print_debug("DIMM overclocked. Check GeodeLink Speed\r\n"); + print_debug("DIMM overclocked. Check GeodeLink Speed\n"); POST_CODE(POST_PLL_MEM_FAIL); __asm__ __volatile__("hlt\n"); } */ @@ -549,7 +549,7 @@ } spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES); if ((spd_byte != 0xFF) && (spd_byte & 3)) { - print_debug("DIMM1 NOT COMPATIBLE\r\n"); + print_debug("DIMM1 NOT COMPATIBLE\n"); POST_CODE(ERROR_UNSUPPORTED_DIMM); __asm__ __volatile__("hlt\n"); } @@ -718,7 +718,7 @@ msr.lo |= (209 << 8); /* bits[15:8] = 209 */ wrmsr(msrnum, msr); - print_debug("DRAM controller init done.\r\n"); + print_debug("DRAM controller init done.\n"); POST_CODE(POST_MEM_SETUP_GOOD); //0x7E /* make sure there is nothing stale in the cache */ @@ -750,6 +750,6 @@ msr.lo |= 1; wrmsr(msrnum, msr); } - print_debug("RAM DLL lock\r\n"); + print_debug("RAM DLL lock\n"); }

1 0

[LinuxBIOS] [PATCH 2/3] Geode file updates based on code review comments
by Marc Jones 11 May '07

11 May '07

This patch updates the PCI ID of the Geode IDE device to include the revision. Signed-off-by: Marc Jones <marc.jones(a)amd.com> -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Index: LinuxBIOSv2/src/include/device/pci_ids.h =================================================================== --- LinuxBIOSv2.orig/src/include/device/pci_ids.h 2007-05-10 16:35:53.000000000 -0600 +++ LinuxBIOSv2/src/include/device/pci_ids.h 2007-05-10 15:40:51.000000000 -0600 @@ -452,13 +452,13 @@ #define PCI_DEVICE_ID_AMD_AES 0x2082 #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 -#define PCI_DEVICE_ID_AMD_CS5536_IDE_A0 0x2092 +#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE 0x2092 #define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093 #define PCI_DEVICE_ID_AMD_CS5536_OHCI 0x2094 #define PCI_DEVICE_ID_AMD_CS5536_EHCI 0x2095 #define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096 #define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097 -#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A +#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE 0x209A #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 Index: LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c =================================================================== --- LinuxBIOSv2.orig/src/southbridge/amd/cs5536/cs5536_ide.c 2007-05-10 16:39:12.000000000 -0600 +++ LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c 2007-05-10 15:42:42.000000000 -0600 @@ -64,5 +64,5 @@ static struct pci_driver ide_driver __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_IDE, + .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE, };

2 1

[LinuxBIOS] r2656 - in trunk/LinuxBIOSv2/src: include/device southbridge/amd/cs5536
by svn＠openbios.org 11 May '07

11 May '07

Author: stuge Date: 2007-05-11 01:12:18 +0200 (Fri, 11 May 2007) New Revision: 2656 Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c Log: This patch updates the PCI ID of the Geode IDE device to include the revision. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-05-10 22:46:17 UTC (rev 2655) +++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-05-10 23:12:18 UTC (rev 2656) @@ -452,13 +452,13 @@ #define PCI_DEVICE_ID_AMD_AES 0x2082 #define PCI_DEVICE_ID_AMD_CS5536_ISA 0x2090 #define PCI_DEVICE_ID_AMD_CS5536_FLASH 0x2091 -#define PCI_DEVICE_ID_AMD_CS5536_IDE_A0 0x2092 +#define PCI_DEVICE_ID_AMD_CS5536_A0_IDE 0x2092 #define PCI_DEVICE_ID_AMD_CS5536_AUDIO 0x2093 #define PCI_DEVICE_ID_AMD_CS5536_OHCI 0x2094 #define PCI_DEVICE_ID_AMD_CS5536_EHCI 0x2095 #define PCI_DEVICE_ID_AMD_CS5536_UDC 0x2096 #define PCI_DEVICE_ID_AMD_CS5536_OTG 0x2097 -#define PCI_DEVICE_ID_AMD_CS5536_IDE 0x209A +#define PCI_DEVICE_ID_AMD_CS5536_B0_IDE 0x209A #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c 2007-05-10 22:46:17 UTC (rev 2655) +++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5536/cs5536_ide.c 2007-05-10 23:12:18 UTC (rev 2656) @@ -64,5 +64,5 @@ static struct pci_driver ide_driver __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_IDE, + .device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE, };

1 0

[LinuxBIOS] [PATCH 0/3] Geode file updates based on code review comments
by Marc Jones 11 May '07

11 May '07

The following three patches are based on comments I received on the initial Geode patches. Marc -- Marc Jones Senior Software Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

1 0

[LinuxBIOS] QEMU target cleanups
by Uwe Hermann 11 May '07

11 May '07

See patch. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

4 7

[LinuxBIOS] [PATCH] 440bx RAM calculation fix
by Ceri Coburn 11 May '07

11 May '07

Here is a patch for the 440bx RAM calculation size. The top of RAM was being calculated incorrectly. Ceri.

3 3

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coreboot May 2007