coreboot April 2007

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281 discussions

[LinuxBIOS] ASUS M2V VIA8237A W39V040C flashrom trivial patch
by torkwemada＠gmail.com 27 Apr '07

27 Apr '07

flashrom patch for ASUS M2V motherboard with VIA 8237A south bridge and W39V040C flash chip. signed-off-by: John Torkwemada <torkwemada(a)gmail.com> ---

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[LinuxBIOS] r2621 build service
by LinuxBIOS information 27 Apr '07

27 Apr '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stuge" checked in revision 2621 to the LinuxBIOS source repository and caused the following changes: Change Log: Add initial support for the following flash chips: - Atmel AT29C020 - STMicroelectronics M29F002B - STMicroelectronics M29F002T - STMicroelectronics M29F002NT Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Signed-off-by: Roger Zauner <roger(a)eskimo.com> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of arima:hdama is still broken Compilation of ibm:e325 is still broken Compilation of ibm:e326 is still broken Compilation of iwill:dk8s2 is still broken Compilation of iwill:dk8x is still broken If something broke during this checkin please be a pain in stuge's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] Porting 440bx from v1, is this right?
by Corey Osgood 27 Apr '07

27 Apr '07

I'm trying to port the sdram reading functions from LBv1 up to v2 (for use with the raminit.c that Uwe just committed), but so far haven't gotten it to work, so I'm hoping maybe someone can spot my problem (I think this is where a problem is). For anyone not familiar with v1, ASSERT_RAM_COMMAND() is called by generic_sdram_enable.inc, and is supposed to read from an address on the dimms. Here's the code for just reading: from src/northbridge/intel/440bx/raminit.inc #define RAM_READ 0x0400 #define DIMM0_BASE \ xorl %eax, %eax #define DIMM_BASE(n) \ movl $(0x60 + ((n) -1)), %eax ; \ PCI_READ_CONFIG_BYTE ; \ andl $0xFF, %eax ; \ shll $23, %eax ; \ #define DIMM_READ \ addl %ebx, %eax ; \ movl (%eax), %edx ; \ //%edx indicates a read, right? xorl $0xdff8, %eax ; \ movl (%eax), %edx #define DIMM0_READ DIMM0_BASE ; DIMM_READ #define DIMM1_READ DIMM_BASE(1) ; DIMM_READ #define DIMM2_READ DIMM_BASE(2) ; DIMM_READ #define DIMM3_READ DIMM_BASE(3) ; DIMM_READ #define DIMM4_READ DIMM_BASE(4) ; DIMM_READ #define DIMM5_READ DIMM_BASE(5) ; DIMM_READ #define DIMM6_READ DIMM_BASE(6) ; DIMM_READ #define DIMM7_READ DIMM_BASE(7) ; DIMM_READ #define DIMMS_READ_EBX_OFFSET \ DIMM0_READ ; \ DIMM1_READ ; \ DIMM2_READ ; \ DIMM3_READ ; \ DIMM4_READ ; \ DIMM5_READ ; \ DIMM6_READ ; \ DIMM7_READ #define DIMMS_READ(offset) \ movl $offset, %ebx ; \ DIMMS_READ_EBX_OFFSET #define ASSERT_RAM_COMMAND() DIMMS_READ(RAM_READ) And here's what I've ported it to. Anyone see anything that sticks out as a problem? (offset = 0x0400, except when setting MRS it's 0x01d0) static void dimms_read(unsigned long offset) { int slot; //DIMM0_READ unsigned long addr = 0; addr += offset; PRINT_DEBUG("addr = "); PRINT_DEBUG_HEX32(addr); // FIXME PRINT_DEBUG("\r\n"); //DIMM_READ read32(addr); addr ^= 0xdff8; // xorl $0xdff8, %eax read32(addr); /* All this should be unnecessary for a single sided single dimm and may even screw things up a bit */ for(slot = 0; slot < 7; slot++) { //DIMM_BASE(n) /* Compute DIMM_BASE */ addr = pci_read_config8(0, (0x60 + slot ));//count starts at 0, so slot-1 not necessary /* NOTE: We should probably check if we already read this addr (ie if all dimm slots aren't populated), but easier not to */ addr &= 0xFF; addr = (addr << 23); //DIMM_READ addr += offset; PRINT_DEBUG(" to 0x"); PRINT_DEBUG_HEX32(addr); // FIXME read32(addr); /* This was pulled from v1, I think it's right */ addr ^= 0xdff8; PRINT_DEBUG(" and 0x"); PRINT_DEBUG_HEX32(addr); // FIXME PRINT_DEBUG("\r\n"); read32(addr); } } Here's some of my minicom.cap, showing what addresses this comes up with: <any non-MRS command> to 0x00000000 and 0x0000dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 to 0x04000000 and 0x0400dff8 RAM Enable 4: Mode register set Computed cas value = 0x01d0 Sending RAM command 0x03addr = 000001d0 to 0x000001d0 and 0x0000de28 to 0x040001d0 and 0x0400de28 etc Thanks, Corey

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[LinuxBIOS] Adding STMicroelectronics and Atmel 256k parts to FlashRom?
by roger 27 Apr '07

27 Apr '07

Is it possible to add these parts to FlashRom? Atmel AT29C020 256k STMicroelectronics M29F002 256k I can read through the bios socket with l440gx module after "enabling write" with FlashRom, but performing write operations to these parts using gives me a permission denied error with mtd utils. Currently, I'm just rebooting using a FreeDOS livecd and using UniFlash. Tedious, but it works. :-/ -- Roger http://www.eskimo.com/~roger/index.html Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61 Thu Apr 19 18:17:08 PDT 2007

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[LinuxBIOS] r2621 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 27 Apr '07

27 Apr '07

Author: stuge Date: 2007-04-28 04:22:59 +0200 (Sat, 28 Apr 2007) New Revision: 2621 Modified: trunk/LinuxBIOSv2/util/flashrom/README trunk/LinuxBIOSv2/util/flashrom/flash.h trunk/LinuxBIOSv2/util/flashrom/flashchips.c Log: Add initial support for the following flash chips: - Atmel AT29C020 - STMicroelectronics M29F002B - STMicroelectronics M29F002T - STMicroelectronics M29F002NT Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Signed-off-by: Roger Zauner <roger(a)eskimo.com> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/LinuxBIOSv2/util/flashrom/README =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/README 2007-04-27 21:24:53 UTC (rev 2620) +++ trunk/LinuxBIOSv2/util/flashrom/README 2007-04-28 02:22:59 UTC (rev 2621) @@ -92,6 +92,7 @@ AMD AM-29F016D ASD AE49F2008 Atmel AT-29C040A +Atmel AT-29C020 EMST F49B002UA Intel 82802AB (Firmware Hub) Intel 82802AC (Firmware Hub) @@ -118,6 +119,9 @@ SST SST-49LF004C SST SST-49LF008C SST SST-49LF016C +ST ST-M29F002B +ST ST-M29F002T +ST ST-M29F002NT ST ST-M29F400BT ST ST-M29F040B SyncMOS S29C51001T/B Modified: trunk/LinuxBIOSv2/util/flashrom/flash.h =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flash.h 2007-04-27 21:24:53 UTC (rev 2620) +++ trunk/LinuxBIOSv2/util/flashrom/flash.h 2007-04-28 02:22:59 UTC (rev 2621) @@ -64,6 +64,7 @@ #define ATMEL_ID 0x1F /* Atmel */ #define AT_29C040A 0xA4 +#define AT_29C020 0xDA #define MX_ID 0xC2 /* Macronix (MX) */ #define MX_29F002 0xB0 @@ -106,8 +107,10 @@ #define W_49V002FA 0x32 #define ST_ID 0x20 /* ST */ +#define ST_M29F002B 0x34 +#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */ +#define ST_M29F400BT 0xD5 #define ST_M29F040B 0xE2 -#define ST_M29F400BT 0xD5 #define EMST_ID 0x8c /* EMST / EFST */ #define EMST_F49B002UA 0x00 Modified: trunk/LinuxBIOSv2/util/flashrom/flashchips.c =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flashchips.c 2007-04-27 21:24:53 UTC (rev 2620) +++ trunk/LinuxBIOSv2/util/flashrom/flashchips.c 2007-04-28 02:22:59 UTC (rev 2621) @@ -49,6 +49,8 @@ probe_jedec, erase_chip_jedec, write_jedec, NULL}, {"At29C040A", ATMEL_ID, AT_29C040A, NULL, 512, 256, probe_jedec, erase_chip_jedec, write_jedec, NULL}, + {"At29C020", ATMEL_ID, AT_29C020, NULL, 256, 256, + probe_jedec, erase_chip_jedec, write_jedec, NULL}, {"Mx29f002", MX_ID, MX_29F002, NULL, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002, NULL}, {"SST29EE020A", SST_ID, SST_29EE020A, NULL, 256, 128, @@ -109,10 +111,14 @@ probe_jedec, erase_chip_jedec, write_39sf020, NULL}, {"W39V080A", WINBOND_ID, W_39V080A, NULL, 1024, 64*1024, probe_jedec, erase_chip_jedec, write_39sf020, NULL}, + {"M29F002B", ST_ID, ST_M29F002B, NULL, 256, 64 * 1024, + probe_jedec, erase_chip_jedec, write_jedec, NULL}, + {"M29F002T/NT", ST_ID, ST_M29F002T, NULL, 256, 64 * 1024, + probe_jedec, erase_chip_jedec, write_jedec, NULL}, + {"M29F400BT", ST_ID, ST_M29F400BT, NULL, 512, 64 * 1024, + probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt, NULL}, {"M29F040B", ST_ID, ST_M29F040B, NULL, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b, NULL}, - {"M29F400BT", ST_ID, ST_M29F400BT, NULL, 512, 64 * 1024, - probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt, NULL}, {"82802ab", 137, 173, NULL, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab, NULL}, {"82802ac", 137, 172, NULL, 1024, 64 * 1024,

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[LinuxBIOS] Quick & Easy Success with Tyan S1832DL! (SMP 440BX)
by roger 27 Apr '07

27 Apr '07

I just used Uwe's Tyan S1846 tree and everything *just* worked. :-) However, I don't mean everything worked. I've attached a log file of the boot for those curious. Here's Failure #1 - DRAM Verify Failure --- Begin Snip --- DRAM filled DRAM verify: 00000000-04000000 00000000 00010000 00020000 00030000 00040000 00050000 00060000 00070000 00080000 00090000 000a0000 F ail: @0x000a0000 Read value=0xffffffff Fail: @0x000a0004 Read value=0xffffffff Fail: @0x000a0008 Read value=0xffffffff ... (repeated millions of times) ... Fail: @0x000a0400 Read value=0xffffffff Aborting. 000a0400 DRAM did _NOT_ verify! Done. --- End Snip --- Here's Failure #2 - Cannot Find PCI Bus Operations --- Begin Snip --- Enumerating buses... scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 Cannot find pci bus operations --- End Snip --- -- Roger http://www.eskimo.com/~roger/index.html Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61 Thu Apr 26 23:54:57 PDT 2007

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[LinuxBIOS] Adding new motherboards to LinuxBiosv2
by roger 27 Apr '07

27 Apr '07

(Oh yes. Another motherboard. :-) Are the following the only folders needing to be created to add support for a motherboard to LinuxBiosv2? --- Snipped From Patch --- Index: src/mainboard/tyan/s1846/Config.lb Index: src/mainboard/tyan/s1846/Options.lb Index: src/mainboard/tyan/s1846/auto.c Index: src/mainboard/tyan/s1846/chip.h Index: src/mainboard/tyan/s1846/failover.c Index: src/mainboard/tyan/s1846/mainboard.c Index: targets/tyan/s1846/Config.lb --- End Snip --- Will start working on a Tyan S1832DL hopefully shortly. (Seems very similar to the S1846 tree with the feature of SMP.) -- Roger http://www.eskimo.com/~roger/index.html Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61 Thu Apr 26 23:11:50 PDT 2007

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[LinuxBIOS] r2620 build service
by LinuxBIOS information 27 Apr '07

27 Apr '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2620 to the LinuxBIOS source repository and caused the following changes: Change Log: Add fan control support to ITE IT8716F. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken Compilation of ibm:e325 is still broken Compilation of ibm:e326 is still broken Compilation of iwill:dk8s2 is still broken Compilation of iwill:dk8x is still broken If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision will be backed out. Yours truely, LinuxBIOS automatic build system

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[LinuxBIOS] question about pnp_dev_info structure in it8716f's superio.c
by Ward Vandewege 27 Apr '07

27 Apr '07

Hi there, I would like some advice about the pnp_dev_info structure. It's used in superio.c for it8716f, for instance. This is what's currently in the tree: static struct pnp_info pnp_dev_info[] = { { &ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, IT8716F_KBCM, PNP_IRQ0, }, // No 7 { 0,}, { &ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4}, }, { &ops, IT8716F_GAME, PNP_IO0, { 0x7ff, 0 }, }, { &ops, IT8716F_IR, }, }; The last 2 parameters on the KBCK line are structs of the type io_info: struct io_info { unsigned mask, set; }; The io_info structure is used to calculate the size of the pci resource; putting 0x7f8 works out to 8 bytes if I understand this correctly; 0x7ff becomes 1 byte. I added this line for the 'Environmental Controller' that deals with fans and temperature/voltage sensors: { &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, This seems to work, but I don't fully understand what the io_info values should be. I'm not sure how I can tell from the datasheet what the sizes should be. I think they apply to PNP_IO0 and PNP_IO1. The calculation is done in pnp_get_ioresource in devices/pnp_device.c. Also, the 'set' value seems to be unused in this context, which is confusing; I'm not sure why it is even there? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

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[LinuxBIOS] r2620 - trunk/LinuxBIOSv2/src/superio/ite/it8716f
by svn＠openbios.org 27 Apr '07

27 Apr '07

Author: stepan Date: 2007-04-27 23:24:53 +0200 (Fri, 27 Apr 2007) New Revision: 2620 Modified: trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c Log: Add fan control support to ITE IT8716F. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c 2007-04-26 20:55:45 UTC (rev 2619) +++ trunk/LinuxBIOSv2/src/superio/ite/it8716f/superio.c 2007-04-27 21:24:53 UTC (rev 2620) @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <console/console.h> #include <uart8250.h> #include <pc80/keyboard.h> #include "chip.h" @@ -49,6 +50,31 @@ pnp_write_config(dev, 0x02, 0x02); } +static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) +{ + outb(reg, port_base); + return inb(port_base + 1); +} + +static void init_ec(unsigned long base) +{ + uint8_t value; + + // Read out current value of FAN_CTL Control register (0x14) + value = pnp_read_index(base, 0x14); + printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",base + 0x14, value); + + // Set FAN_CTL Control register (0x14) polarity to High, and activate fans 1, 2 and 3 + pnp_write_index(base, 0x14, value | 0x87); + printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",base + 0x14, value | 0x87); +} + static void it8716f_init(device_t dev) { struct superio_ite_it8716f_config *conf; @@ -60,7 +86,7 @@ conf = dev->chip_info; - /* TODO: FDC, PP, EC, KBCM, MIDI, GAME, IR. */ + /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ switch (dev->path.u.pnp.device) { case IT8716F_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -70,6 +96,11 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; + case IT8716F_EC: + res0 = find_resource(dev, PNP_IDX_IO0); +#define EC_INDEX_PORT 5 + init_ec(res0->base + EC_INDEX_PORT); + break; case IT8716F_KBCK: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); @@ -113,7 +144,7 @@ { &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, IT8716F_EC, }, + { &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, { &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, { &ops, IT8716F_KBCM, PNP_IRQ0, }, // No 7 { 0,},

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coreboot April 2007