here's a first patch for the 440BX code and the Tyan S1846 and the 82371EB
southbridge which gets my Tyan S1846 a lot further in the boot process.
However, it cannot boot a payload, yet.
It seems the major problem was that I did ram_check() on the whole range
from 0 - 64 MB (in my case; I use a 64 MB DIMM for testing). This cannot
work of course, as the range from 640 KB - 1 MB is _not_ RAM but rather
reserved for all kinds of other stuff (thanks Stefan for pointing this out!).
Leaving out that range, but checking the rest of RAM, I get a
"DRAM range verified", so it seems RAM init _does_ work after all.
(it's hardcoded to my board and setup of course, but that'll be fixed)
I've tried setting up the PCI devices correctly in Config.lb, but I'm
absolutely not sure that I got it all right. Can somebody please check
this and let me know of any stupid errors I made?
Here's the lspci output from the Tyan S1846:
00:00.0 0600: 8086:7190 (rev 03)
00:01.0 0604: 8086:7191 (rev 03)
00:07.0 0601: 8086:7110 (rev 02)
00:07.1 0101: 8086:7111 (rev 01)
00:07.2 0c03: 8086:7112 (rev 01)
00:07.3 0680: 8086:7113 (rev 02)
00:10.0 0300: 5333:5631 (rev 06)
00:11.0 0200: 10ec:8029
00:00.0 Host bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (rev 03)
00:01.0 PCI bridge: Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge (rev 03)
00:07.0 ISA bridge: Intel Corporation 82371AB/EB/MB PIIX4 ISA (rev 02)
00:07.1 IDE interface: Intel Corporation 82371AB/EB/MB PIIX4 IDE (rev 01)
00:07.2 USB Controller: Intel Corporation 82371AB/EB/MB PIIX4 USB (rev 01)
00:07.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02)
00:10.0 VGA compatible controller: S3 Inc. 86c325 [ViRGE] (rev 06)
00:11.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8029(AS)
-[0000:00]-+-00.0 Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge
+-07.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA
+-07.1 Intel Corporation 82371AB/EB/MB PIIX4 IDE
+-07.2 Intel Corporation 82371AB/EB/MB PIIX4 USB
+-07.3 Intel Corporation 82371AB/EB/MB PIIX4 ACPI
+-10.0 S3 Inc. 86c325 [ViRGE]
\-11.0 Realtek Semiconductor Co., Ltd. RTL-8029(AS)
(5333:5631 and 10ec:8029 are add-on cards -- VGA and Ethernet)
And this is my current try to setup Config.lb:
chip northbridge/intel/i440bx # Northbridge
device pci_domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 off end # PCI bridge TODO: AGP bridge?
# device pci 7.0 on end # ISA bridge
chip southbridge/intel/i82371eb # Southbridge
device pci 7.0 on # ISA bridge ???
chip superio/nsc/pc87309 # Super I/O
device pnp 2e.0 on end # Floppy
device pnp 2e.1 on end # Parallel port
device pnp 2e.2 on end # Com2
device pnp 2e.3 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
device pnp 2e.4 on end # Power mgmt.
device pnp 2e.5 on end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12 # ???
device pci 7.1 on end # IDE
device pci 7.2 on end # USB
device pci 7.3 on end # ACPI
Does that look correct?
Also, a full boot log is attached. The PCI init _seems_ to work, at
The current end of the story is that elfboot cannot find the payload,
not sure why. Wrong PCI init? Wrong RAM init? Wrong payload location?
http://www.hermann-uwe.de | http://www.holsham-traders.dehttp://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Thanks for your posts on DK8-HTX. I am just starting working on this
mainboard these two days. From what you said in your email, you modify
several things I think, and most of them must be modified by lxbios, I
try to summarize your work:
1 serial console baud_rate -> 115200
2 max_mem_clock -> 400MHz
3 boot_first ("HDD"), boot_second and boot_third ("Fallback_HDD").
I am not sure how to achieve the third one. Is it also in cmos?
And another question is that I don't know how to dd a 36K Video ROM as
you said. Do you just enlarge the size of dd?
such as this?
dd if=/dev/mem of=vgabios.bin skip=1536 count=72
Is that all the things you make LinuxBIOS run on DK8-HTX? Thanks for your help!
On Sat, Apr 21, 2007 at 03:33:30PM +0400, Alexei I. Adamovich wrote:
> Looking at the serial console output after changing the boot_option
> value to "Normal" and the debug_level value to "Spew" in the CMOS,
> I've found that the system hangs near the very begining of load
> process after trying to find some memory (dram0).
Forgot to mention that to see the serial console output I also changed
the baud_rate CMOS value to "115200"--since just this value was
defined in the LinuxBios Config-s and I had set my serial console
client (kermit) to wait connection just on this rate.
Alexei I. Adamovich
Hi, I've been watching this mailing list for a long time mostly to see the
progress on the Gigabyte M575SLI and things seem to be looking very nice. I
have 2 questions: how easy is it to build the LinuxBIOS and flash it without
bricking it? (I've been looking at the sideproject here about using the extra
bios socket, but my soldering skills are not very good and I don't have much
in the way of decent soldering tools) and also, how easy is it to set what
would be normal BIOS settings like voltage, cpu multipliers, etc... (For say
overclocking a system) I've heard about a Google SoC project to get some sort
of CMOS setup like interface after it is booted, but it seems you have to
hard code these values in to the option file before you build the BIOS. Am I
correct? And if so, what are all the options you can set?
I just got back from an extended stay in Asia and while I was there was
introduced to a nifty little device for SPI flash chips. When the mfgs
all switch to SPI it may actually be much easier to deal with non-socket
$275 US gets you a programmer + the hardware to hook it up to your board.
The way it works is by asserting the HOLD pin on the SPI flash which
almost all SPI flash parts have. So the flash thats soldered on board
is suspended and you boot from the one in the adapter.
The only requirement is to have the HOLD pin pulled up via a resistor
rather than tied directly to the SPI part's Vcc. Even if it is tied
directly to Vcc working around it would only involve cutting a single
trace or lifting the HOLD pin.
Richard A. Smith
although it could be hard to port Linuxbios onto this ASUS mainboard
(that uses intel 945 chipset), it has a SPI flash in a convenient
The BIOS chip is a 4Mb flash part, Winbond 25X40VAIZ
Just to let you know the goodies that are around these days.
p.s. i'm not going to do any linuxbios related testing
>> I recently purchased a Tyan S2882 motherboard so that I could play with
>> Alas, even purchasing a supported board with a tutorial isn't straight forward.
>> I have cut and pasted the Config example for FILO with grub, and editing only
>> MENULST_FILE = "hda1:/grub/menu.lst"
>> to MENULST_FILE = "hda1:/boot/grub/menu.lst"
>> to reflect the location of my grub's menu.lst file.
>> But, it won't compile.
>> Any help?
> We're going to need a lot more details. What doesn't compile - filo? What's
> the error you get? What version of GCC do you use?
I'm trying to compile filo-0.5 (It's at the beginning of the tutorial,
so I've started there. I may well have other problems later. (If someone
wants to send me a compiled linuxbios for the S2882 using the ATI bios
with a payload, that would be ok!)
The last few lines of the output are:
make: Leaving directory `/home/jebradl/filo-0.5/drivers/usb'
make -C i386
make: Entering directory `/home/jebradl/filo-0.5/i386'
make: Nothing to be done for `all'.
make: Leaving directory `/home/jebradl/filo-0.5/i386'
ld -m elf_i386 -N -T i386/ldscript -o filo main/builtin.o
main/grub/builtin.o fs/builtin.o drivers/builtin.o drivers/usb/builtin.o
main/builtin.o: In function `number':
printf.c:(.text+0x924): undefined reference to `__stack_chk_fail'
main/builtin.o: In function `elf_load':
(.text+0x18c6): undefined reference to `__stack_chk_fail'
main/grub/builtin.o: In function `run_menu':
stage2.c:(.text+0xe76): undefined reference to `__stack_chk_fail'
main/grub/builtin.o: In function `terminfo_func':
builtins.c:(.text+0x1510): undefined reference to `__stack_chk_fail'
main/grub/builtin.o: In function `md5crypt_func':
builtins.c:(.text+0x1c7d): undefined reference to `__stack_chk_fail'
main/grub/builtin.o:builtins.c:(.text+0x1db7): more undefined references
to `__stack_chk_fail' follow
make: *** [filo] Error 1
I've attempted the compile with gcc 4.1.2 (Ubuntu 4.1.2-0ubuntu4) on
I have the S2882 motherboard without builtin SCSI. I have 2 processors
installed. The drive is an IDE drive. A floppy and CDROM are also installed.
Peter Stuge schrieb:
>> the manual states two separate memories: expansion rom and then the
>> rest of the flash mem.
>> I am somewhat sure it is not purely a PCI expansion ROM .
> No it is definately not just an expansion ROM, but my point was that
> they designed it to hook into the system boot process with an
> expansion ROM that knew how to reach the rest of the flash.
> More generally speaking the board is overkill for our purposes since
> we only need a much simpler FPGA and less flash memory, since no
> chipset currently decodes more than 1MB at 4G anyway. Also their
> design uses lots of flash chips which is not really neccessary today
> when much larger flash chips are available.
>> maybe one should look at the verilog code stuff.
> So I did, the top 7 bits (31-25) of the board's BAR0 set which
> address it listens to (PCI config space 0x10) and bits 22-2 are taken
> from the PCI read cycle.
> Bits 24-23 are ignored, so there are 2^23 effective addresses, each
> accessing a 32-bit word, total 32Mb.
> As for access to the expansion ROM, the VHDL is not complete.
> Specifically the signal ROM_HIT isn't set anywhere. It's likely to
> be set in the generic Xilinx LogiCORE VHDL for PCI devices.
>> Intel does not sell the board but one might find the manual
>> interesting since it deals with our issue on a sidenote I believe.
> Sure, "all" that is needed to make such a PCI card is an FPGA and
> flash memory. :)
sry this got misaddressed
>> For the record, I build FILO with 4.1.1 without problems. Maybe this
>> is a 64/32 problem, I'm just on i686-pc-linux-gnu.
> Yeah, that rings a bell. I think I saw this on x86_64 - could not compile
> FILO with gcc 4.0 or 4.1, but it did work with gcc 3.4.
I did get a payload compiled on my laptop (i686) using gcc-3.4.6. I
couldn't get it to compile on the S2882.
The payload still has some problems, though, as it only allows me to
boot to a grub prompt. I don't get it show the grub menu, or boot the
default settings,, but I do get a display, so I'm making progress.