coreboot December 2007

coreboot@coreboot.org

78 participants
271 discussions

[LinuxBIOS] r3010 - in trunk/LinuxBIOSv2/src/mainboard: a-trend/atc-6220 asus/p2b asus/p2b-f asus/p3b-f azza/pt-6ibd biostar/m6tba compaq/deskpro_en_sff_p600 gigabyte/ga-6bxc tyan/s1846
by svn＠openbios.org 17 Dec '07

17 Dec '07

Author: uwe Date: 2007-12-17 22:34:53 +0100 (Mon, 17 Dec 2007) New Revision: 3010 Modified: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb trunk/LinuxBIOSv2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb Log: Enable IDE legacy port access for all 440BX based boards per default, as this is needed (at the very least) to make FILO work on these boards. Disable UDMA/33 per default, which is slower but the safe choice, as we don't know which IDE devices a user has attached, and some don't support UDMA/33 very well or at all. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -130,6 +130,12 @@ device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -130,6 +130,12 @@ device pci 4.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -130,6 +130,12 @@ device pci 4.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -131,6 +131,12 @@ device pci 4.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -130,6 +130,12 @@ device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -124,6 +124,12 @@ device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -134,6 +134,12 @@ device pci 14.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -128,6 +128,12 @@ device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end Modified: trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-12-17 14:33:32 UTC (rev 3009) +++ trunk/LinuxBIOSv2/src/mainboard/tyan/s1846/Config.lb 2007-12-17 21:34:53 UTC (rev 3010) @@ -126,6 +126,12 @@ device pci 7.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" end end end

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[LinuxBIOS] #91: Add --list-supported option
by LinuxBIOS 17 Dec '07

17 Dec '07

#91: Add --list-supported option ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Enhance the superiotool utility Component: superiotool | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ We should add a --list-supported option which prints the Super I/O chips supported by superiotool (and links to the resp. wiki page, too). -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/91> LinuxBIOS <http://www.linuxbios.org/>

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[LinuxBIOS] #90: Add --list-supported option
by LinuxBIOS 17 Dec '07

17 Dec '07

#90: Add --list-supported option ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Enhance the flashrom utility Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ We should add a --list-supported option which prints the chips, southbridges, and boards supported by flashrom (and links to the resp. wiki page, too). Then drop the list of supported stuff from the README, so we don't have to manually maintain two different lists (which is tedious, error-prone, and hard to keep in sync as seen in the past). -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/90> LinuxBIOS <http://www.linuxbios.org/>

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[LinuxBIOS] Tyan s1894
by Jason Green 17 Dec '07

17 Dec '07

I am new to LinuxBIOS mailing list. I have a few old boards I want to try out. I dunno if it's compatible with this or not. http://www.tyan.com/archive/products/html/tigercub100.html Sakui

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Re: [LinuxBIOS] [PATCH] AMD Barcelona(family 10) support 4 of 4]
by Marc Jones 17 Dec '07

17 Dec '07

Can someone with an dual cpu or dual core Intel system try this patch? Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

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[LinuxBIOS] Trac reminder: list of new ticket(s)
by LinuxBIOS tracker 17 Dec '07

17 Dec '07

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[LinuxBIOS] [PATCH] flashrom: prepare for upcoming massive SPI chip support
by Carl-Daniel Hailfinger 17 Dec '07

17 Dec '07

To make it easier to add new SPI chips to flashchips.c, rename functions with multiple possible opcodes from linear numbering at the end (_1, _2) to include the opcode at the end (_60, _c7). That way, you only have to take a short look at the data sheet and choose the right function by appending the opcode listed in the data sheet. No functional changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-renamespi/flash.h =================================================================== --- flashrom-renamespi/flash.h (Revision 3008) +++ flashrom-renamespi/flash.h (Arbeitskopie) @@ -257,7 +257,7 @@ int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void generic_spi_write_enable(); void generic_spi_write_disable(); -int generic_spi_chip_erase(struct flashchip *flash); +int generic_spi_chip_erase_c7(struct flashchip *flash); int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ Index: flashrom-renamespi/flashchips.c =================================================================== --- flashrom-renamespi/flashchips.c (Revision 3008) +++ flashrom-renamespi/flashchips.c (Arbeitskopie) @@ -47,7 +47,7 @@ {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024, - probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, @@ -141,7 +141,7 @@ {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, {"M25P80", ST_ID, ST_M25P80, 1024, 64 * 1024, - probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"82802ab", 137, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"82802ac", 137, 172, 1024, 64 * 1024, Index: flashrom-renamespi/spi.c =================================================================== --- flashrom-renamespi/spi.c (Revision 3008) +++ flashrom-renamespi/spi.c (Arbeitskopie) @@ -46,24 +46,24 @@ #define JEDEC_WRDI_INSIZE 0x00 /* Chip Erase 0x60 is supported by Macronix/SST chips. */ -#define JEDEC_CE_1 {0x60}; -#define JEDEC_CE_1_OUTSIZE 0x01 -#define JEDEC_CE_1_INSIZE 0x00 +#define JEDEC_CE_60 {0x60}; +#define JEDEC_CE_60_OUTSIZE 0x01 +#define JEDEC_CE_60_INSIZE 0x00 -/* Chip Erase 0xc7 is supported by EON/Macronix chips. */ -#define JEDEC_CE_2 {0xc7}; -#define JEDEC_CE_2_OUTSIZE 0x01 -#define JEDEC_CE_2_INSIZE 0x00 +/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ +#define JEDEC_CE_C7 {0xc7}; +#define JEDEC_CE_C7_OUTSIZE 0x01 +#define JEDEC_CE_C7_INSIZE 0x00 /* Block Erase 0x52 is supported by SST chips. */ -#define JEDEC_BE_1 {0x52}; -#define JEDEC_BE_1_OUTSIZE 0x04 -#define JEDEC_BE_1_INSIZE 0x00 +#define JEDEC_BE_52 {0x52}; +#define JEDEC_BE_52_OUTSIZE 0x04 +#define JEDEC_BE_52_INSIZE 0x00 /* Block Erase 0xd8 is supported by EON/Macronix chips. */ -#define JEDEC_BE_2 {0xd8}; -#define JEDEC_BE_2_OUTSIZE 0x04 -#define JEDEC_BE_2_INSIZE 0x00 +#define JEDEC_BE_D8 {0xd8}; +#define JEDEC_BE_D8_OUTSIZE 0x04 +#define JEDEC_BE_D8_INSIZE 0x00 /* Sector Erase 0x20 is supported by Macronix/SST chips. */ #define JEDEC_SE {0x20}; @@ -277,9 +277,9 @@ return readarr[0]; } -int generic_spi_chip_erase(struct flashchip *flash) +int generic_spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[] = JEDEC_CE_2; + const unsigned char cmd[] = JEDEC_CE_C7; uint8_t statusreg; statusreg = generic_spi_read_status_register(); @@ -287,7 +287,7 @@ generic_spi_write_enable(); /* Send CE (Chip Erase) */ - generic_spi_command(JEDEC_CE_2_OUTSIZE, JEDEC_CE_2_INSIZE, cmd, NULL); + generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ @@ -301,16 +301,16 @@ * 32k for SST * 4-32k non-uniform for EON */ -int generic_spi_block_erase(const struct flashchip *flash, unsigned long addr) +int generic_spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_BE_2_OUTSIZE] = JEDEC_BE_2; + unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = JEDEC_BE_D8; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); generic_spi_write_enable(); /* Send BE (Block Erase) */ - generic_spi_command(JEDEC_BE_2_OUTSIZE, JEDEC_BE_2_INSIZE, cmd, NULL); + generic_spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */

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[LinuxBIOS] r3009 - trunk/util/flashrom
by svn＠openbios.org 17 Dec '07

17 Dec '07

Author: hailfinger Date: 2007-12-17 15:33:32 +0100 (Mon, 17 Dec 2007) New Revision: 3009 Modified: trunk/util/flashrom/flash.h trunk/util/flashrom/flashchips.c trunk/util/flashrom/spi.c Log: To make it easier to add new SPI chips to flashchips.c, rename functions with multiple possible opcodes from linear numbering at the end (_1, _2) to include the opcode at the end (_60, _c7). That way, you only have to take a short look at the data sheet and choose the right function by appending the opcode listed in the data sheet. No functional changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/util/flashrom/flash.h =================================================================== --- trunk/util/flashrom/flash.h 2007-12-16 21:15:27 UTC (rev 3008) +++ trunk/util/flashrom/flash.h 2007-12-17 14:33:32 UTC (rev 3009) @@ -257,7 +257,7 @@ int generic_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); void generic_spi_write_enable(); void generic_spi_write_disable(); -int generic_spi_chip_erase(struct flashchip *flash); +int generic_spi_chip_erase_c7(struct flashchip *flash); int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ Modified: trunk/util/flashrom/flashchips.c =================================================================== --- trunk/util/flashrom/flashchips.c 2007-12-16 21:15:27 UTC (rev 3008) +++ trunk/util/flashrom/flashchips.c 2007-12-17 14:33:32 UTC (rev 3009) @@ -47,7 +47,7 @@ {"MX29F002", MX_ID, MX_29F002, 256, 64 * 1024, probe_29f002, erase_29f002, write_29f002}, {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024, - probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"SST29EE020A", SST_ID, SST_29EE020A, 256, 128, probe_jedec, erase_chip_jedec, write_jedec}, {"SST28SF040A", SST_ID, SST_28SF040, 512, 256, @@ -141,7 +141,7 @@ {"M29F040B", ST_ID, ST_M29F040B, 512, 64 * 1024, probe_29f040b, erase_29f040b, write_29f040b}, {"M25P80", ST_ID, ST_M25P80, 1024, 64 * 1024, - probe_spi, generic_spi_chip_erase, generic_spi_chip_write}, + probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write}, {"82802ab", 137, 173, 512, 64 * 1024, probe_82802ab, erase_82802ab, write_82802ab}, {"82802ac", 137, 172, 1024, 64 * 1024, Modified: trunk/util/flashrom/spi.c =================================================================== --- trunk/util/flashrom/spi.c 2007-12-16 21:15:27 UTC (rev 3008) +++ trunk/util/flashrom/spi.c 2007-12-17 14:33:32 UTC (rev 3009) @@ -46,24 +46,24 @@ #define JEDEC_WRDI_INSIZE 0x00 /* Chip Erase 0x60 is supported by Macronix/SST chips. */ -#define JEDEC_CE_1 {0x60}; -#define JEDEC_CE_1_OUTSIZE 0x01 -#define JEDEC_CE_1_INSIZE 0x00 +#define JEDEC_CE_60 {0x60}; +#define JEDEC_CE_60_OUTSIZE 0x01 +#define JEDEC_CE_60_INSIZE 0x00 -/* Chip Erase 0xc7 is supported by EON/Macronix chips. */ -#define JEDEC_CE_2 {0xc7}; -#define JEDEC_CE_2_OUTSIZE 0x01 -#define JEDEC_CE_2_INSIZE 0x00 +/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */ +#define JEDEC_CE_C7 {0xc7}; +#define JEDEC_CE_C7_OUTSIZE 0x01 +#define JEDEC_CE_C7_INSIZE 0x00 /* Block Erase 0x52 is supported by SST chips. */ -#define JEDEC_BE_1 {0x52}; -#define JEDEC_BE_1_OUTSIZE 0x04 -#define JEDEC_BE_1_INSIZE 0x00 +#define JEDEC_BE_52 {0x52}; +#define JEDEC_BE_52_OUTSIZE 0x04 +#define JEDEC_BE_52_INSIZE 0x00 /* Block Erase 0xd8 is supported by EON/Macronix chips. */ -#define JEDEC_BE_2 {0xd8}; -#define JEDEC_BE_2_OUTSIZE 0x04 -#define JEDEC_BE_2_INSIZE 0x00 +#define JEDEC_BE_D8 {0xd8}; +#define JEDEC_BE_D8_OUTSIZE 0x04 +#define JEDEC_BE_D8_INSIZE 0x00 /* Sector Erase 0x20 is supported by Macronix/SST chips. */ #define JEDEC_SE {0x20}; @@ -277,9 +277,9 @@ return readarr[0]; } -int generic_spi_chip_erase(struct flashchip *flash) +int generic_spi_chip_erase_c7(struct flashchip *flash) { - const unsigned char cmd[] = JEDEC_CE_2; + const unsigned char cmd[] = JEDEC_CE_C7; uint8_t statusreg; statusreg = generic_spi_read_status_register(); @@ -287,7 +287,7 @@ generic_spi_write_enable(); /* Send CE (Chip Erase) */ - generic_spi_command(JEDEC_CE_2_OUTSIZE, JEDEC_CE_2_INSIZE, cmd, NULL); + generic_spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 1-85 s, so wait in 1 s steps. */ @@ -301,16 +301,16 @@ * 32k for SST * 4-32k non-uniform for EON */ -int generic_spi_block_erase(const struct flashchip *flash, unsigned long addr) +int generic_spi_block_erase_d8(const struct flashchip *flash, unsigned long addr) { - unsigned char cmd[JEDEC_BE_2_OUTSIZE] = JEDEC_BE_2; + unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = JEDEC_BE_D8; cmd[1] = (addr & 0x00ff0000) >> 16; cmd[2] = (addr & 0x0000ff00) >> 8; cmd[3] = (addr & 0x000000ff); generic_spi_write_enable(); /* Send BE (Block Erase) */ - generic_spi_command(JEDEC_BE_2_OUTSIZE, JEDEC_BE_2_INSIZE, cmd, NULL); + generic_spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */

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Re: [LinuxBIOS] AMD Geode LX on Lippert Roadrunner LX800
by Peter Stuge 17 Dec '07

17 Dec '07

Hi again, On Sun, Dec 16, 2007 at 09:41:28PM -0600, Simpson, Matthew wrote: > I am subscribed to the list for msimpson(a)bellhelicopter.textron.com Ok! > I'll try one of those others and see how far I get. Please report back. :) > I am interested in increasing the boot time of this little board. I > am running FC7 on it with a tweeked-out 2.6.23 kernel. Oh. Then you may be optimizing the wrong thing, also look into how much time the boot-time scripts need. That is the first thing I look at to reduce the boot time, usually quite a lot of time is spent there, because the boot scripts are usually made to be very general, while in an embedded system you can use one simple script instead. (I just replace the boot, sysinit and default scripts that are called by init.) //Peter

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[LinuxBIOS] Getting started with LinuxBIOS on a MSI K9N Neo-F (MS-7260).
by Carsten Koch 17 Dec '07

17 Dec '07

Hi, I am completely new to LinuxBIOS. After checking the Supported Motherboards table on http://linuxbios.org/Supported_Motherboards for a well-supported main board, I bought a MSI K9N Neo-F (MS-7260) on ebay. Now I need to get a suitable CPU, RAM and at least one pre-flashed PROM (I do not have a prommer and according to the MSI MS-7260 Build Tutorial, the flashrom tool does not work with the original BIOS). My questions are: Would a AMD Athlon 64 X2 4000+ 65nm (Brisbane) be a good choice or is there any reason this CPU might not currently work with LinuxBIOS? The table in the MSI MS-7260 Build Tutorial says "Untested" under "Dual channel support". If I buy 2 1GB DDR2 DIMMs and tested it, would anyone be ready to help me make it work if it does not work out of the box? Would anyone be ready to send me one or two pre-flashed chips? I'd pay for all the costs in advance. Thanks an Cheers, Carsten.

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coreboot December 2007