coreboot October 2007

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[LinuxBIOS] [PATCH] VIA VT8237R support
by Rudolf Marek 29 Oct '07

29 Oct '07

Hello, Its Friday night... I have no date... I think I fixed everything what Uwe wanted. Here comes much better patch (after five hours ;) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Corey, I fixed the SMBus so it does work from the beginning. Please can you test on your side too? Rudolf

6 21

[LinuxBIOS] r2907 - in trunk/LinuxBIOSv2/src: include/device southbridge/via southbridge/via/vt8237r
by svn＠openbios.org 29 Oct '07

29 Oct '07

Author: uwe Date: 2007-10-30 04:09:39 +0100 (Tue, 30 Oct 2007) New Revision: 2907 Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/Config.lb trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h Log: Add support for the VIA VT8237R southbridge. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: <corey.osgood(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h =================================================================== --- trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-10-30 02:24:49 UTC (rev 2906) +++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-10-30 03:09:39 UTC (rev 2907) @@ -1138,6 +1138,21 @@ #define PCI_DEVICE_ID_VIA_8505_1 0x8605 #define PCI_DEVICE_ID_VIA_8633_1 0xB091 #define PCI_DEVICE_ID_VIA_8367_1 0xB099 +#define PCI_DEVICE_ID_VIA_K8T890CE_0 0x0238 +#define PCI_DEVICE_ID_VIA_K8T890CE_1 0x1238 +#define PCI_DEVICE_ID_VIA_K8T890CE_2 0x2238 +#define PCI_DEVICE_ID_VIA_K8T890CE_3 0x3238 +#define PCI_DEVICE_ID_VIA_K8T890CE_4 0x4238 +#define PCI_DEVICE_ID_VIA_K8T890CE_5 0x5238 +#define PCI_DEVICE_ID_VIA_K8T890CE_7 0x7238 +#define PCI_DEVICE_ID_VIA_K8T890CE_PEG 0xa238 +#define PCI_DEVICE_ID_VIA_K8T890CE_PEX0 0xc238 +#define PCI_DEVICE_ID_VIA_K8T890CE_PEX1 0xd238 +#define PCI_DEVICE_ID_VIA_K8T890CE_PEX2 0xe238 +#define PCI_DEVICE_ID_VIA_K8T890CE_PEX3 0xf238 +#define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188 +#define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149 +#define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227 #define PCI_VENDOR_ID_SIEMENS 0x110A #define PCI_DEVICE_ID_SIEMENS_DSCC4 0x2102 Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/Config.lb 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,26 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License v2 as published by +## the Free Software Foundation. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h + +driver vt8237r.o +driver vt8237r_ide.o +driver vt8237r_lpc.o +driver vt8237r_sata.o +driver vt8237r_bridge.o Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/chip.h 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,60 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_VIA_VT8237R_CHIP_H +#define SOUTHBRIDGE_VIA_VT8237R_CHIP_H + +#include <stdint.h> + +extern struct chip_operations southbridge_via_vt8237r_ops; + +struct southbridge_via_vt8237r_config { + /** + * Function disable. 1 = disabled. + * 7 Dev 17 fn 6 MC97 + * 6 Dev 17 fn 5 AC97 + * 5 Dev 16 fn 1 USB 1.1 UHCI Ports 2-3 + * 4 Dev 16 fn 0 USB 1.1 UHCI Ports 0-1 + * 3 Dev 15 fn 0 Serial ATA + * 2 Dev 16 fn 2 USB 1.1 UHCI Ports 4-5 + * 1 Dev 16 fn 4 USB 2.0 EHCI + * 0 Dev 16 fn 3 USB 1.1 UHCI Ports 6-7 + */ + u16 fn_ctrl_lo; + + /** + * 7 USB Device Mode 1=dis + * 6 Reserved + * 5 Internal LAN Controller Clock Gating 1=gated + * 4 Internal LAN Controller 1=di + * 3 Internal RTC 1=en + * 2 Internal PS2 Mouse 1=en + * 1 Internal KBC Configuration 0=dis ports 0x2e/0x2f off 0xe0-0xef + * 0 Internal Keyboard Controller 1=en + */ + u16 fn_ctrl_hi; + + int ide0_enable:1; + int ide1_enable:1; + /* 1 = 80-pin cable */ + int ide0_80pin_cable:1; + int ide1_80pin_cable:1; +}; + +#endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.c 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,89 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <pc80/keyboard.h> +#include "chip.h" + +/* + * Datasheet: http://www.via.com.tw/en/downloads/datasheets/chipsets/ + * VT8237R_SouthBridge_Revision2.06_Lead-Free.zip + */ + +void hard_reset(void) +{ + printk_err("NO HARD RESET ON VT8237R! FIX ME!\n"); +} + +#if DEFAULT_CONSOLE_LOGLEVEL > 7 +void writeback(struct device *dev, u16 where, u8 what) +{ + u8 regval; + + pci_write_config8(dev, where, what); + regval = pci_read_config8(dev, where); + + if (regval != what) { + print_debug("Writeback to "); + print_debug_hex8(where); + print_debug("failed "); + print_debug_hex8(regval); + print_debug("\n "); /* TODO: Drop the space? */ + } +} +#else +void writeback(struct device *dev, u16 where, u8 what) +{ + pci_write_config8(dev, where, what); +} +#endif + +void dump_south(device_t dev) +{ + int i, j; + + for (i = 0; i < 256; i += 16) { + printk_debug("%02x: ", i); + for (j = 0; j < 16; j++) { + printk_debug("%02x ", + pci_read_config8(dev, i + j)); + } + printk_debug("\n"); + } +} + +static void vt8237r_enable(struct device *dev) +{ + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *) dev->chip_info; + + pci_write_config8(dev, 0x50, sb->fn_ctrl_lo); + pci_write_config8(dev, 0x51, sb->fn_ctrl_hi); + + /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ +} + +struct chip_operations southbridge_via_vt8237r_ops = { + CHIP_NAME("VIA VT8237R Southbridge") + .enable_dev = vt8237r_enable, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r.h 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,33 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_VIA_VT8237R_VT8237R_H +#define SOUTHBRIDGE_VIA_VT8237R_VT8237R_H + +/* Static resources for the VT8237R southbridge. */ + +#define VT8237R_APIC_ID 0x2 +#define VT8237R_ACPI_IO_BASE 0x500 +#define VT8237R_SMBUS_IO_BASE 0x400 +/* 0x0 disabled, 0x2 reserved, 0xf = IRQ15 */ +#define VT8237R_ACPI_IRQ 0x9 +#define VT8237R_HPET_ADDR 0xfed00000ULL +#define VT8237R_APIC_BASE 0xfec00000ULL + +#endif Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_bridge.c 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,57 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> + +static void bridge_enable(struct device *dev) +{ + print_debug("B188 device dump\n"); + + /* VIA recommends this, sorry no known info. */ + writeback(dev, 0x40, 0x91); + writeback(dev, 0x41, 0x40); + writeback(dev, 0x43, 0x44); + writeback(dev, 0x44, 0x31); + writeback(dev, 0x45, 0x3a); + writeback(dev, 0x46, 0x88); /* PCI ID lo */ + writeback(dev, 0x47, 0xb1); /* PCI ID hi */ + writeback(dev, 0x3e, 0x16); /* Bridge control */ + + dump_south(dev); +} + +static struct device_operations bridge_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .enable = bridge_enable, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &bridge_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_K8T890CE_BR, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_early_smbus.c 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,168 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey_osgood(a)verizon.net> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_ids.h> +#include "vt8237r.h" + +#define VT8237R_POWER_WELL 0x94 +#define VT8237R_SMBUS_IO_BASE_REG 0xd0 +#define VT8237R_SMBUS_HOST_CONF 0xd2 + +#define SMBHSTSTAT (VT8237R_SMBUS_IO_BASE + 0x0) +#define SMBSLVSTAT (VT8237R_SMBUS_IO_BASE + 0x1) +#define SMBHSTCTL (VT8237R_SMBUS_IO_BASE + 0x2) +#define SMBHSTCMD (VT8237R_SMBUS_IO_BASE + 0x3) +#define SMBXMITADD (VT8237R_SMBUS_IO_BASE + 0x4) +#define SMBHSTDAT0 (VT8237R_SMBUS_IO_BASE + 0x5) + +#define HOST_RESET 0xff +/* 1 in the 0 bit of SMBHSTADD states to READ. */ +#define READ_CMD 0x01 +#define SMBUS_TIMEOUT (100 * 1000 * 10) +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 + +#if DEBUG_SMBUS == 1 +#define PRINT_DEBUG(x) print_debug(x) +#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#else +#define PRINT_DEBUG(x) +#define PRINT_DEBUG_HEX16(x) +#endif + +#define SMBUS_DELAY() inb(0x80) + +static void smbus_print_error(u8 host_status, int loops) +{ + /* Check if there actually was an error. */ + if (host_status == 0x00 || host_status == 0x40 || + host_status == 0x42) + return; + + if (loops >= SMBUS_TIMEOUT) + print_err("SMBus timeout\r\n"); + if (host_status & (1 << 4)) + print_err("Interrupt/SMI# was Failed Bus Transaction\r\n"); + if (host_status & (1 << 3)) + print_err("Bus error\r\n"); + if (host_status & (1 << 2)) + print_err("Device error\r\n"); + if (host_status & (1 << 1)) + print_err("Interrupt/SMI# was Successful Completion\r\n"); + if (host_status & (1 << 0)) + print_err("Host busy\r\n"); +} + +static void smbus_wait_until_ready(void) +{ + int loops; + + PRINT_DEBUG("Waiting until SMBus ready\r\n"); + + loops = 0; + /* Yes, this is a mess, but it's the easiest way to do it. */ + while ((inb(SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT) + ++loops; + smbus_print_error(inb(SMBHSTSTAT), loops); +} + +static void smbus_reset(void) +{ + outb(HOST_RESET, SMBHSTSTAT); + /* Datasheet says we have to read it to take ownership of SMBus. */ + inb(SMBHSTSTAT); + + PRINT_DEBUG("After reset status: "); + PRINT_DEBUG_HEX16(inb(SMBHSTSTAT)); + PRINT_DEBUG("\r\n"); +} + +u8 smbus_read_byte(u32 dimm, u32 offset) +{ + u32 val; + + PRINT_DEBUG("DIMM "); + PRINT_DEBUG_HEX16(dimm); + PRINT_DEBUG(" OFFSET "); + PRINT_DEBUG_HEX16(offset); + PRINT_DEBUG("\r\n"); + + smbus_reset(); + /* Clear host data port. */ + outb(0x00, SMBHSTDAT0); + SMBUS_DELAY(); + smbus_wait_until_ready(); + + /* Actual addr to reg format. */ + dimm = (dimm << 1); + dimm |= 1; + outb(dimm, SMBXMITADD); + outb(offset, SMBHSTCMD); + /* Start transaction, byte data read. */ + outb(0x48, SMBHSTCTL); + + SMBUS_DELAY(); + + smbus_wait_until_ready(); + + val = inb(SMBHSTDAT0); + PRINT_DEBUG("Read: "); + PRINT_DEBUG_HEX16(val); + PRINT_DEBUG("\r\n"); + + /* Probably don't have to do this, but it can't hurt. */ + smbus_reset(); + + /* Can I just "return inb(SMBHSTDAT0)"? */ + return val; +} + +void enable_smbus(void) +{ + device_t dev; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + + if (dev == PCI_DEV_INVALID) + die("Power Management Controller not found\r\n"); + + /* 7 = SMBus Clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp + */ + pci_write_config8(dev, VT8237R_POWER_WELL, 0xa0); + + /* Enable SMBus */ + pci_write_config16(dev, VT8237R_SMBUS_IO_BASE_REG, + VT8237R_SMBUS_IO_BASE | 0x1); + + /* SMBus Host Configuration, enable */ + pci_write_config8(dev, VT8237R_SMBUS_HOST_CONF, 0x01); + + /* Make it work for I/O. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + smbus_reset(); + + /* Reset the internal pointer. */ + inb(SMBHSTCTL); +} Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_ide.c 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,116 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Based on other VIA SB code. */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include "vt8237r.h" +#include "chip.h" + +#define IDE_CS 0x40 +#define IDE_CONF_I 0x41 +#define IDE_CONF_II 0x42 +#define IDE_CONF_FIFO 0x43 +#define IDE_MISC_I 0x44 +#define IDE_MISC_II 0x45 +#define IDE_UDMA 0x50 + +/** + * No native mode. Interrupts from unconnected HDDs might occur if + * IRQ14/15 is used for PCI. Therefore no native mode support. + */ +static void ide_init(struct device *dev) +{ + struct southbridge_via_vt8237r_config *sb = + (struct southbridge_via_vt8237r_config *) dev->chip_info; + + u8 enables; + u32 cablesel; + + printk_info("%s IDE interface %s\n", "Primary", + sb->ide0_enable ? "enabled" : "disabled"); + printk_info("%s IDE interface %s\n", "Secondary", + sb->ide1_enable ? "enabled" : "disabled"); + enables = pci_read_config8(dev, IDE_CS) & ~0x3; + enables |= (sb->ide0_enable << 1) | sb->ide1_enable; + pci_write_config8(dev, IDE_CS, enables); + enables = pci_read_config8(dev, IDE_CS); + printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables); + + /* Enable only compatibility mode. */ + enables = pci_read_config8(dev, IDE_CONF_II); + enables &= ~0xc0; + pci_write_config8(dev,IDE_CONF_II, enables); + enables = pci_read_config8(dev, IDE_CONF_II); + printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables); + + /* Enable prefetch buffers. */ + enables = pci_read_config8(dev, IDE_CONF_I); + enables |= 0xf0; + pci_write_config8(dev, IDE_CONF_I, enables); + + /* Flush FIFOs at half. */ + enables = pci_read_config8(dev, IDE_CONF_FIFO); + enables &= 0xf0; + enables |= (1 << 2) | (1 << 0); + pci_write_config8(dev, IDE_CONF_FIFO, enables); + + /* PIO read prefetch counter, Bus Master IDE Status Reg. Read Retry. */ + enables = pci_read_config8(dev, IDE_MISC_I); + enables &= 0xe2; + enables |= (1 << 4) | (1 << 3); + pci_write_config8(dev, IDE_MISC_I, enables); + + /* Use memory read multiple, Memory-Write-and-Invalidate. */ + enables = pci_read_config8(dev, IDE_MISC_II); + enables |= (1 << 2) | (1 << 3); + pci_write_config8(dev, IDE_MISC_II, enables); + + /* Force interrupts to use compat mode. */ + pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Cable guy... */ + cablesel = pci_read_config32(dev, IDE_UDMA); + cablesel &= ~((1 << 28) | (1 << 20) | (1 <<12) | (1 << 4)); + cablesel |= (sb->ide0_80pin_cable << 28) | + (sb->ide0_80pin_cable << 20) | + (sb->ide1_80pin_cable << 12) | + (sb->ide1_80pin_cable << 4); + pci_write_config32(dev, IDE_UDMA, cablesel); +} + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init, + .enable = 0, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_82C586_1, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,350 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Inspiration from other VIA SB code. */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> +#include <stdlib.h> +#include "vt8237r.h" +#include "chip.h" + +#define ALL (0xff << 24) +#define NONE (0) +#define DISABLED (1 << 16) +#define ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8) + +extern void dump_south(device_t dev); + +struct ioapicreg { + u32 reg; + u32 value_low; + u32 value_high; +} ioapic_table[] = { + /* IO-APIC virtual wire mode configuration. */ + /* mask, trigger, polarity, destination, delivery, vector */ + {0, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | + ExtINT, NONE}, + {1, DISABLED, NONE}, + {2, DISABLED, NONE}, + {3, DISABLED, NONE}, + {4, DISABLED, NONE}, + {5, DISABLED, NONE}, + {6, DISABLED, NONE}, + {7, DISABLED, NONE}, + {8, DISABLED, NONE}, + {9, DISABLED, NONE}, + {10, DISABLED, NONE}, + {11, DISABLED, NONE}, + {12, DISABLED, NONE}, + {13, DISABLED, NONE}, + {14, DISABLED, NONE}, + {15, DISABLED, NONE}, + {16, DISABLED, NONE}, + {17, DISABLED, NONE}, + {18, DISABLED, NONE}, + {19, DISABLED, NONE}, + {20, DISABLED, NONE}, + {21, DISABLED, NONE}, + {22, DISABLED, NONE}, + {23, DISABLED, NONE}, +}; + +static void setup_ioapic(u32 ioapic_base) +{ + u32 value_low, value_high, val; + volatile u32 *l; + int i; + + /* All delivered to CPU0. */ + ioapic_table[0].value_high = (lapicid()) << (56 - 32); + l = (unsigned long *) ioapic_base; + + /* Set APIC to FSB message bus. */ + l[0] = 0x3; + val = l[4]; + l[4] = (val & 0xFFFFFE) | 1; + + /* Set APIC ADDR - this will be VT8237R_APIC_ID. */ + l[0] = 0; + val = l[4]; + l[4] = (val & 0xF0FFFF) | (VT8237R_APIC_ID << 24); + + for (i = 0; i < ARRAY_SIZE(ioapic_table); i++) { + l[0] = (ioapic_table[i].reg * 2) + 0x10; + l[4] = ioapic_table[i].value_low; + value_low = l[4]; + l[0] = (ioapic_table[i].reg * 2) + 0x11; + l[4] = ioapic_table[i].value_high; + value_high = l[4]; + + if ((i == 0) && (value_low == 0xffffffff)) { + printk_warning("IO APIC not responding.\n"); + return; + } + } +} + +/** Set up PCI IRQ routing, route everything through APIC. */ +static void pci_routing_fixup(struct device *dev) +{ + /* PCI PNP Interrupt Routing INTE/F - disable */ + pci_write_config8(dev, 0x44, 0x00); + + /* PCI PNP Interrupt Routing INTG/H - disable */ + pci_write_config8(dev, 0x45, 0x00); + + /* Route INTE-INTH through registers above, no map to INTA-INTD. */ + pci_write_config8(dev, 0x46, 0x10); + + /* PCI Interrupt Polarity */ + pci_write_config8(dev, 0x54, 0x00); + + /* PCI INTA# Routing */ + pci_write_config8(dev, 0x55, 0x00); + + /* PCI INTB#/C# Routing */ + pci_write_config8(dev, 0x56, 0x00); + + /* PCI INTD# Routing */ + pci_write_config8(dev, 0x57, 0x00); +} + +/** + * Set up the power management capabilities directly into ACPI mode. + * This avoids having to handle any System Management Interrupts (SMIs). + */ +void setup_pm(device_t dev) +{ + /* Debounce LID and PWRBTN# Inputs for 16ms. */ + pci_write_config8(dev, 0x80, 0x20); + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Set ACPI to 9, must set IRQ 9 override to level! Set PSON gating. */ + pci_write_config8(dev, 0x82, 0x40 | VT8237R_ACPI_IRQ); + + /* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */ + pci_write_config16(dev, 0x84, 0x30b2); + + /* SMI output level to low, 7.5us throttle clock */ + pci_write_config8(dev, 0x8d, 0x18); + + /* GP Timer Control 1s */ + pci_write_config8(dev, 0x93, 0x88); + + /* 7 = SMBus clock from RTC 32.768KHz + * 5 = Internal PLL reset from susp + * 2 = GPO2 is GPIO + */ + pci_write_config8(dev, 0x94, 0xa4); + + /* 7 = stp to sust delay 1msec + * 6 = SUSST# Deasserted Before PWRGD for STD + * 3 = GPO26/GPO27 is GPO + * 2 = Disable Alert on Lan + */ + pci_write_config8(dev, 0x95, 0xcc); + + /* Disable GP3 timer. */ + pci_write_config8(dev, 0x98, 0); + + /* Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x9); + + /* REQ5 as PCI request input - should be together with INTE-INTH. */ + pci_write_config8(dev, 0xe4, 0x4); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* Clear status events. */ + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x00); + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x20); + outw(0xffff, VT8237R_ACPI_IO_BASE + 0x28); + outl(0xffffffff, VT8237R_ACPI_IO_BASE + 0x30); + + /* Disable SCI on GPIO. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x22); + + /* Disable SMI on GPIO. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x24); + + /* Disable all global enable SMIs. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x2a); + + /* All SMI off, both IDE buses ON, PSON rising edge. */ + outw(0x0, VT8237R_ACPI_IO_BASE + 0x2c); + + /* Primary activity SMI disable. */ + outl(0x0, VT8237R_ACPI_IO_BASE + 0x34); + + /* GP timer reload on none. */ + outl(0x0, VT8237R_ACPI_IO_BASE + 0x38); + + /* Disable extended IO traps. */ + outb(0x0, VT8237R_ACPI_IO_BASE + 0x42); + + /* SCI is generated for RTC/pwrBtn/slpBtn. */ + outw(0x001, VT8237R_ACPI_IO_BASE + 0x04); +} + +static void vt8237r_init(struct device *dev) +{ + u8 enables, byte; + + /* Enable addr/data stepping. */ + byte = pci_read_config8(dev, PCI_COMMAND); + byte |= PCI_COMMAND_WAIT; + pci_write_config8(dev, PCI_COMMAND, byte); + + /* Enable the internal I/O decode. */ + enables = pci_read_config8(dev, 0x6C); + enables |= 0x80; + pci_write_config8(dev, 0x6C, enables); + + /* FIXME: Map 4MB of flash into the address space, + * this should be in CAR call. + */ + /* pci_write_config8(dev, 0x41, 0x7f); */ + + /* Set bit 6 of 0x40 (I/O recovery time). + * IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so + * that PCI interrupts can be properly marked as level triggered. + */ + enables = pci_read_config8(dev, 0x40); + enables |= 0x44; + pci_write_config8(dev, 0x40, enables); + + /* Line buffer control */ + enables = pci_read_config8(dev, 0x42); + enables |= 0xf8; + pci_write_config8(dev, 0x42, enables); + + /* Delay transaction control */ + pci_write_config8(dev, 0x43, 0xb); + + /* I/O recovery time */ + pci_write_config8(dev, 0x4c, 0x44); + + /* ROM memory cycles go to LPC. */ + pci_write_config8(dev, 0x59, 0x80); + + /* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */ + pci_write_config8(dev, 0x5B, 0xb); + + /* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */ + pci_write_config8(dev, 0x48, 0x8c); + + /* Set 0x58 to 0x43 APIC and RTC. */ + pci_write_config8(dev, 0x58, 0x43); + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + enables = pci_read_config8(dev, 0x4f); + enables |= 0x08; + pci_write_config8(dev, 0x4f, enables); + + /* Enable serial IRQ, 6PCI clocks. */ + pci_write_config8(dev, 0x52, 0x9); + + /* Enable HPET at VT8237R_HPET_ADDR. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + /* Power management setup */ + setup_pm(dev); + + /* Start the RTC. */ + rtc_init(0); +} + +void vt8237r_read_resources(device_t dev) +{ + struct resource *res; + + pci_dev_read_resources(dev); + /* Fixed APIC resource */ + res = new_resource(dev, 0x44); + res->base = VT8237R_APIC_BASE; + res->size = 256; + res->limit = res->base + res->size - 1; + res->align = 8; + res->gran = 8; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +/** + * The VT8237R is not a PCI bridge and has no resources of its own (other + * than standard PC I/O addresses), however it does control the ISA bus + * and so we need to manually call enable childrens resources on that bus. + */ +void vt8237r_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + enable_childrens_resources(dev); +} + +static void init_keyboard(struct device *dev) +{ + u8 regval = pci_read_config8(dev, 0x51); + if (regval & 0x1) + init_pc_keyboard(0x60, 0x64, 0); +} + +static void southbridge_init(struct device *dev) +{ + vt8237r_init(dev); + pci_routing_fixup(dev); + setup_ioapic(VT8237R_APIC_BASE); + setup_i8259(); + init_keyboard(dev); +} + +static struct device_operations vt8237r_lpc_ops = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = vt8237r_enable_resources, + .init = &southbridge_init, + .scan_bus = scan_static_bus, +}; + +static struct pci_driver lpc_driver __pci_driver = { + .ops = &vt8237r_lpc_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, +}; Added: trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/via/vt8237r/vt8237r_sata.c 2007-10-30 03:09:39 UTC (rev 2907) @@ -0,0 +1,58 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License v2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> + +#define SATA_MISC_CTRL 0x45 + +static void sata_init(struct device *dev) +{ + u8 reg; + + printk_debug("Configuring VIA SATA controller\n"); + + /* Class IDE Disk */ + reg = pci_read_config8(dev, SATA_MISC_CTRL); + reg &= 0x7f; /* Sub Class Write Protect off */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); + + /* Change the device class to SATA from RAID. */ + pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); + reg |= 0x80; /* Sub Class Write Protect on */ + pci_write_config8(dev, SATA_MISC_CTRL, reg); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = 0, + .ops_pci = 0, +}; + +static struct pci_driver northbridge_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT6420_SATA, +};

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[LinuxBIOS] r2904 build service
by LinuxBIOS information 29 Oct '07

29 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "stepan" checked in revision 2904 to the LinuxBIOS source repository and caused the following changes: Change Log: K8 resource dump utility from Rudolf Marek Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=khepri&vendor… Compilation of sis:sis761 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2904&device=sis761&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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Re: [LinuxBIOS] r2906 - in trunk/LinuxBIOSv2/targets/sis: . sis761
by Corey Osgood 29 Oct '07

29 Oct '07

svn(a)openbios.org wrote: > Author: stepan > Date: 2007-10-30 03:24:49 +0100 (Tue, 30 Oct 2007) > New Revision: 2906 > > Added: > trunk/LinuxBIOSv2/targets/sis/sis761/ > trunk/LinuxBIOSv2/targets/sis/sis761/Config-abuild.lb > Removed: > trunk/LinuxBIOSv2/targets/sis/churchill/ > Log: > move target directory to have the same name as the directory in the > mainboard/ path. Also add a Config.lb for abuild. It's required for the > three images variant as abuild doesnt detect this automatically. > Trivial patch - it does not even fix the build yet. Patches welcome. > > Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> > Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Shouldn't these go into gigabyte/ga-2761gxdx/ (eventually)? -Corey

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[LinuxBIOS] Which BIOS Savior for VIA EPIA M-II?
by Coquelicot 29 Oct '07

29 Oct '07

Dear LinuxBIOSers, I have a brand new VIA EPIA M-II (with 1 GHz CPU) motherboard that I would like to boot faster than by factory default (carputer projects). I have following purchased BIOS Savior from FrozenCPU : RD1-PMC2 but it seems that it is the wrong one (I have installed the BIOS Savior but the motherboard doesn't boot, I have tried both positions of the switch). After replacing the original BIOS back on the motherboard the boot works OK, so it seems that's definitely the BIOS Savior chip that is not working. I am tempted to do the direct flashing (ie. without the BIOS Savior) but I know that's pretty risky... especially that I want the motherboard boot Linux from CF port (I read the howto and I think I know what to do) which can be tricky. Greetings to all LinuxBIOS users & developers, -- Coquelicot

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[LinuxBIOS] r2906 - in trunk/LinuxBIOSv2/targets/sis: . sis761
by svn＠openbios.org 29 Oct '07

29 Oct '07

Author: stepan Date: 2007-10-30 03:24:49 +0100 (Tue, 30 Oct 2007) New Revision: 2906 Added: trunk/LinuxBIOSv2/targets/sis/sis761/ trunk/LinuxBIOSv2/targets/sis/sis761/Config-abuild.lb Removed: trunk/LinuxBIOSv2/targets/sis/churchill/ Log: move target directory to have the same name as the directory in the mainboard/ path. Also add a Config.lb for abuild. It's required for the three images variant as abuild doesnt detect this automatically. Trivial patch - it does not even fix the build yet. Patches welcome. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Copied: trunk/LinuxBIOSv2/targets/sis/sis761 (from rev 2902, trunk/LinuxBIOSv2/targets/sis/churchill) Added: trunk/LinuxBIOSv2/targets/sis/sis761/Config-abuild.lb =================================================================== --- trunk/LinuxBIOSv2/targets/sis/sis761/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/sis/sis761/Config-abuild.lb 2007-10-30 02:24:49 UTC (rev 2906) @@ -0,0 +1,55 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target sis_sis761 +mainboard sis/sis761 + +__COMPRESSION__ + +option ROM_SIZE = 512*1024 + +romimage "normal" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=0x28000 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION=".0-Normal" + payload __PAYLOAD__ +end + +romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x20000 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION=".0-Fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option LINUXBIOS_EXTRA_VERSION=".0-Failover" +end + + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"

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[LinuxBIOS] r2905 - trunk/LinuxBIOSv2/src/southbridge/sis/sis966
by svn＠openbios.org 29 Oct '07

29 Oct '07

Author: stepan Date: 2007-10-30 03:17:49 +0100 (Tue, 30 Oct 2007) New Revision: 2905 Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ht.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pcie.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c Log: fix the readwrite/readonly clashes for the pci_driver structs in the sis code. This is trivial, I did it for the other components before. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_aza.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -31,8 +31,7 @@ #include <arch/io.h> #include "sis966.h" -uint8_t SiS_SiS7502_init[6][3]={ - +uint8_t SiS_SiS7502_init[7][3]={ {0x04, 0xFF, 0x07}, {0x2C, 0xFF, 0x39}, {0x2D, 0xFF, 0x10}, @@ -493,7 +492,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver azaaudio_driver __pci_driver = { +static const struct pci_driver azaaudio_driver __pci_driver = { .ops = &aza_audio_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_AZA, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ht.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ht.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ht.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -48,7 +48,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver ht_driver __pci_driver = { +static const struct pci_driver ht_driver __pci_driver = { .ops = &ht_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_HT, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_ide.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -167,7 +167,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver ide_driver __pci_driver = { +static const struct pci_driver ide_driver __pci_driver = { .ops = &ide_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_IDE, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_lpc.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -397,39 +397,39 @@ // .enable = sis966_enable, .ops_pci = &lops_pci, }; -static struct pci_driver lpc_driver __pci_driver = { +static const struct pci_driver lpc_driver __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_LPC, }; -static struct pci_driver lpc_driver_pro __pci_driver = { +static const struct pci_driver lpc_driver_pro __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PRO, }; -static struct pci_driver lpc_driver_lpc2 __pci_driver = { +static const struct pci_driver lpc_driver_lpc2 __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_LPC_2, }; -static struct pci_driver lpc_driver_lpc3 __pci_driver = { +static const struct pci_driver lpc_driver_lpc3 __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_LPC_3, }; -static struct pci_driver lpc_driver_lpc4 __pci_driver = { +static const struct pci_driver lpc_driver_lpc4 __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_LPC_4, }; -static struct pci_driver lpc_driver_lpc5 __pci_driver = { +static const struct pci_driver lpc_driver_lpc5 __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_LPC_5, }; -static struct pci_driver lpc_driver_lpc6 __pci_driver = { +static const struct pci_driver lpc_driver_lpc6 __pci_driver = { .ops = &lpc_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_LPC_6, @@ -444,7 +444,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver lpc_driver_slave __pci_driver = { +static const struct pci_driver lpc_driver_slave __pci_driver = { .ops = &lpc_slave_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_SLAVE, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_nic.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -631,12 +631,12 @@ // .enable = sis966_enable, .ops_pci = &lops_pci, }; -static struct pci_driver nic_driver __pci_driver = { +static const struct pci_driver nic_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_NIC1, }; -static struct pci_driver nic_bridge_driver __pci_driver = { +static const struct pci_driver nic_bridge_driver __pci_driver = { .ops = &nic_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_NIC_BRIDGE, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pci.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -101,7 +101,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver pci_driver __pci_driver = { +static const struct pci_driver pci_driver __pci_driver = { .ops = &pci_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PCI, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pcie.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pcie.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_pcie.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -58,27 +58,27 @@ .ops_pci = &lops_pci, }; -static struct pci_driver pciebc_driver __pci_driver = { +static const struct pci_driver pciebc_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PCIE_B_C, }; -static struct pci_driver pciee_driver __pci_driver = { +static const struct pci_driver pciee_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PCIE_E, }; -static struct pci_driver pciea_driver __pci_driver = { +static const struct pci_driver pciea_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PCIE_A, }; -static struct pci_driver pcief_driver __pci_driver = { +static const struct pci_driver pcief_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PCIE_F, }; -static struct pci_driver pcied_driver __pci_driver = { +static const struct pci_driver pcied_driver __pci_driver = { .ops = &pcie_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_PCIE_D, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_sata.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -288,13 +288,13 @@ .ops_pci = &lops_pci, }; -static struct pci_driver sata0_driver __pci_driver = { +static const struct pci_driver sata0_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_SATA0, }; -static struct pci_driver sata1_driver __pci_driver = { +static const struct pci_driver sata1_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_SATA1, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_smbus.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -146,7 +146,7 @@ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; -static struct pci_driver smbus_driver __pci_driver = { +static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_SM2, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -107,7 +107,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver usb_driver __pci_driver = { +static const struct pci_driver usb_driver __pci_driver = { .ops = &usb_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_USB, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sis966_usb2.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -161,7 +161,7 @@ .ops_pci = &lops_pci, }; -static struct pci_driver usb2_driver __pci_driver = { +static const struct pci_driver usb2_driver __pci_driver = { .ops = &usb2_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS966_EHCI, Modified: trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c 2007-10-30 01:12:20 UTC (rev 2904) +++ trunk/LinuxBIOSv2/src/southbridge/sis/sis966/sisnb.c 2007-10-30 02:17:49 UTC (rev 2905) @@ -185,7 +185,7 @@ .ops_pci = 0, }; -static struct pci_driver sisnb_driver __pci_driver = { +static const struct pci_driver sisnb_driver __pci_driver = { .ops = &sisnb_ops, .vendor = PCI_VENDOR_ID_SIS, .device = PCI_DEVICE_ID_SIS_SIS761,

1 0

[LinuxBIOS] [PATCH]Fintek F71805f for LinuxBIOSv3
by Corey Osgood 29 Oct '07

29 Oct '07

See patch. -Corey

4 10

[LinuxBIOS] r508 - in LinuxBIOSv3: . superio superio/fintek superio/fintek/f71805f
by svn＠openbios.org 29 Oct '07

29 Oct '07

Author: stepan Date: 2007-10-30 03:03:43 +0100 (Tue, 30 Oct 2007) New Revision: 508 Added: LinuxBIOSv3/superio/fintek/ LinuxBIOSv3/superio/fintek/f71805f/ LinuxBIOSv3/superio/fintek/f71805f/Makefile LinuxBIOSv3/superio/fintek/f71805f/dts LinuxBIOSv3/superio/fintek/f71805f/f71805f.h LinuxBIOSv3/superio/fintek/f71805f/stage1.c LinuxBIOSv3/superio/fintek/f71805f/superio.c Modified: LinuxBIOSv3/Kconfig Log: I know there is still an ongoing discussion on the list about this patch, and how support for superios might look in the future. This code (like all the rest, too) will certainly change and evolve in the future, as v3 evolves. ----- Add support for the Fintek F71805f to LinuxBIOSv3. It hasn't been tested yet because something's failing to build elsewhere, but the stage1 does build, and for the moment that's what matters. It's based on working v2 code so it should work fine. Signed-off-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: LinuxBIOSv3/Kconfig =================================================================== --- LinuxBIOSv3/Kconfig 2007-10-16 19:29:34 UTC (rev 507) +++ LinuxBIOSv3/Kconfig 2007-10-30 02:03:43 UTC (rev 508) @@ -84,6 +84,8 @@ # Super I/Os: config SUPERIO_WINBOND_W83627HF boolean +config SUPERIO_FINTEK_F71805F + boolean # Source all northbridge/southbridge/superio Kconfig files: source northbridge/intel/i440bxemulation/Kconfig Added: LinuxBIOSv3/superio/fintek/f71805f/Makefile =================================================================== --- LinuxBIOSv3/superio/fintek/f71805f/Makefile (rev 0) +++ LinuxBIOSv3/superio/fintek/f71805f/Makefile 2007-10-30 02:03:43 UTC (rev 508) @@ -0,0 +1,29 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SUPERIO_FINTEK_F71805F),y) + +STAGE0_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/stage1.o +STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o + +# Always add to variables, as there could be more than one Super I/O. +STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o + +endif Added: LinuxBIOSv3/superio/fintek/f71805f/dts =================================================================== --- LinuxBIOSv3/superio/fintek/f71805f/dts (rev 0) +++ LinuxBIOSv3/superio/fintek/f71805f/dts 2007-10-30 02:03:43 UTC (rev 508) @@ -0,0 +1,53 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +{ + /* Floppy */ + floppydev = "0x0"; + floppyenable = "0"; + floppyio = "0x3f0"; + floppyirq = "6"; + floppydrq = "2"; + + /* Parallel port */ + ppdev = "1"; + ppenable = "1"; + ppio = "0x378"; + ppirq = "7"; + + /* Note: renaming from comx to spx may have broken the DTS + * We'll find out later */ + /* Serial Port 1 */ + sp1dev = "2"; + sp1enable = "1"; + sp1io = "0x3f8"; + sp1irq = "4"; + + /* Serial Port 2 */ + sp2dev = "3"; + sp2enable = "1"; + sp2io = "0x2f8"; + sp2irq = "3"; + + /* Hardware Monitor */ + hwmdev = "0xb"; + hwmenable = "0"; + hwmio = "0xec00"; +}; Added: LinuxBIOSv3/superio/fintek/f71805f/f71805f.h =================================================================== --- LinuxBIOSv3/superio/fintek/f71805f/f71805f.h (rev 0) +++ LinuxBIOSv3/superio/fintek/f71805f/f71805f.h 2007-10-30 02:03:43 UTC (rev 508) @@ -0,0 +1,36 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Corey Osgood <corey(a)slightlyhackish.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: F71805F/FG Super H/W Monitor + LPC IO + * - URL: http://www.fintek.com.tw/eng/products.asp?BID=1&SID=17 + * - PDF: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf + * - Revision: V0.25P + */ + +/* Logical Device Numbers (LDN). */ +#define F71805F_FDC 0x00 /* Floppy */ +#define F71805F_SP1 0x01 /* UART1 */ +#define F71805F_SP2 0x02 /* UART2 */ +#define F71805F_PP 0x03 /* Parallel Port */ +#define F71805F_HWM 0x04 /* Hardware Monitor */ +#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71805F_PME 0x0a /* Power Management Events (PME) */ Added: LinuxBIOSv3/superio/fintek/f71805f/stage1.c =================================================================== --- LinuxBIOSv3/superio/fintek/f71805f/stage1.c (rev 0) +++ LinuxBIOSv3/superio/fintek/f71805f/stage1.c 2007-10-30 02:03:43 UTC (rev 508) @@ -0,0 +1,41 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <io.h> +#include <device/pnp.h> +#include "f71805f.h" + +static inline void f71805f_rawpnp_enter_ext_func_mode(u8 dev) +{ + /* Fintek F71805f needs this only once, but Winbond needs it twice. + * Perhaps modify rawpnp_enter_ext_func_mode() to only do it once, + * then modify the winbond to call it twice? */ + outb(0x87, dev); +} + +void f71805f_enable_serial(u8 dev, u8 serial, u16 iobase) +{ + f71805f_rawpnp_enter_ext_func_mode(dev); + rawpnp_set_logical_device(dev, serial); + rawpnp_set_enable(dev, 0); + rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase); + rawpnp_set_enable(dev, 1); + rawpnp_exit_ext_func_mode(dev); +} Added: LinuxBIOSv3/superio/fintek/f71805f/superio.c =================================================================== --- LinuxBIOSv3/superio/fintek/f71805f/superio.c (rev 0) +++ LinuxBIOSv3/superio/fintek/f71805f/superio.c 2007-10-30 02:03:43 UTC (rev 508) @@ -0,0 +1,117 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright 2007 Corey Osgood <corey.osgood(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Ported from v2 driver */ + +#include <io.h> +#include <lib.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console.h> +#include <string.h> +#include <uart8250.h> +#include <statictree.h> +#include "f71805f.h" + +static void enable_dev(struct device *dev); +void f71805f_pnp_set_resources(struct device *dev); +void f71805f_pnp_set_resources(struct device *dev); +void f71805f_pnp_enable_resources(struct device *dev); +void f71805f_pnp_enable(struct device *dev); +static void f71805f_init(struct device *dev); + +static void pnp_enter_conf_state(struct device *dev); +static void pnp_exit_conf_state(struct device *dev); + +static void pnp_enter_conf_state(struct device *dev) +{ + outb(0x87, dev->path.u.pnp.port); +} + +static void pnp_exit_conf_state(struct device *dev) +{ + outb(0xaa, dev->path.u.pnp.port); +} + +void f71805f_pnp_set_resources(struct device *dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +void f71805f_pnp_enable_resources(struct device *dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +void f71805f_pnp_enable(struct device *dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, dev->enabled) + pnp_exit_conf_state(dev); +} + +static void f71805f_init(struct device *dev) +{ + struct superio_smsc_f71805f_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) + return; + + switch (dev->path.u.pnp.device) { + case F71805F_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + //TODO: needed? fix or remove? + //init_uart8250(res0->base, &conf->sp1); + break; + + case F71805F_SP2: + res1 = find_resource(dev, PNP_IDX_IO0); + //init_uart8250(res0->base, &conf->sp2); + break; + + /* No KBC on F71805f */ + } +} + +static struct device_operations ops; +static struct pnp_info pnp_dev_info[] = { + { &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + /* TODO: Everything else */ +}; + +static void phase2_setup_scan_bus(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static struct device_operations ops = { + .phase2_setup_scan_bus = phase2_setup_scan_bus, + .phase4_read_resources = pnp_read_resources, + .phase4_set_resources = f71805f_pnp_set_resources, + .phase4_enable_disable = f71805f_pnp_enable_resources, + .phase5_enable_resources = f71805f_pnp_enable, + .phase6_init = f71805f_init, +};

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[LinuxBIOS] r2903 build service
by LinuxBIOS information 29 Oct '07

29 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2903 to the LinuxBIOS source repository and caused the following changes: Change Log: Add support for Intel 440MX systems. Add support for the Fujitsu MBM29F400TC flash part. Detection and reading works, writing is not tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=khepri&vendor… Compilation of sis:sis761 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2903&device=sis761&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

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coreboot October 2007