coreboot October 2007

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[LinuxBIOS] r2919 - in trunk/LinuxBIOSv2: src/mainboard src/mainboard/biostar src/mainboard/biostar/m6tba targets targets/biostar targets/biostar/m6tba
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 01:25:06 +0100 (Wed, 31 Oct 2007) New Revision: 2919 Added: trunk/LinuxBIOSv2/src/mainboard/biostar/ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Options.lb trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/auto.c trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/chip.h trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/mainboard.c trunk/LinuxBIOSv2/targets/biostar/ trunk/LinuxBIOSv2/targets/biostar/m6tba/ trunk/LinuxBIOSv2/targets/biostar/m6tba/Config.lb Log: Add initial support for the Biostar M6TBA. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Config.lb 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,129 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.8 on # Aux I/O + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end +end Added: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/Options.lb 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,99 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/auto.c 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,72 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + smscsuperio_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/chip.h 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,22 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_biostar_m6tba_ops; +struct mainboard_biostar_m6tba_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/irq_tables.c 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,50 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router device */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc7, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/biostar/m6tba/mainboard.c 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_biostar_m6tba_ops = { + CHIP_NAME("Biostar M6TBA Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/biostar/m6tba/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/biostar/m6tba/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/biostar/m6tba/Config.lb 2007-10-31 00:25:06 UTC (rev 2919) @@ -0,0 +1,50 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target m6tba +mainboard biostar/m6tba + +# Note: The original flash ROM chip is 128 KB. +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "Biostar" +option MAINBOARD_PART_NUMBER = "M6TBA" + +option IRQ_SLOT_COUNT = 7 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] r2918 - in trunk/LinuxBIOSv2: src/mainboard src/mainboard/azza src/mainboard/azza/pt-6ibd targets targets/azza targets/azza/pt-6ibd
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 01:23:57 +0100 (Wed, 31 Oct 2007) New Revision: 2918 Added: trunk/LinuxBIOSv2/src/mainboard/azza/ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Options.lb trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/auto.c trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/chip.h trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/mainboard.c trunk/LinuxBIOSv2/targets/azza/ trunk/LinuxBIOSv2/targets/azza/pt-6ibd/ trunk/LinuxBIOSv2/targets/azza/pt-6ibd/Config.lb Log: Add initial support for the AZZA PT-6IBD. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Config.lb 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,135 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end +end Added: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/Options.lb 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,99 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/auto.c 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,75 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +/* FIXME: It's a Winbond W83977EF, actually. */ +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +/* FIXME: It's a Winbond W83977EF, actually. */ +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + /* FIXME: It's a Winbond W83977EF, actually. */ + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/chip.h 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,22 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_azza_pt_6ibd_ops; +struct mainboard_azza_pt_6ibd_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/irq_tables.c 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,50 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router device */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3c, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x09<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0f<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x11<<3)|0x0, {{0x61, 0xdeb8}, {0x60, 0xdeb8}, {0x63, 0xdeb8}, {0x62, 0x0deb8}}, 0x5, 0x0}, + {0x00,(0x07<<3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/azza/pt-6ibd/mainboard.c 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_azza_pt_6ibd_ops = { + CHIP_NAME("AZZA PT-6IBD Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/azza/pt-6ibd/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/azza/pt-6ibd/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/azza/pt-6ibd/Config.lb 2007-10-31 00:23:57 UTC (rev 2918) @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target pt-6ibd +mainboard azza/pt-6ibd + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "AZZA" +option MAINBOARD_PART_NUMBER = "PT-6IBD" + +option IRQ_SLOT_COUNT = 7 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] r2917 - in trunk/LinuxBIOSv2: src/mainboard src/mainboard/a-trend src/mainboard/a-trend/atc-6220 targets targets/a-trend targets/a-trend/atc-6220
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 01:22:32 +0100 (Wed, 31 Oct 2007) New Revision: 2917 Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Options.lb trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/auto.c trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/chip.h trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/mainboard.c trunk/LinuxBIOSv2/targets/a-trend/ trunk/LinuxBIOSv2/targets/a-trend/atc-6220/ trunk/LinuxBIOSv2/targets/a-trend/atc-6220/Config.lb Log: Add initial support for the A-Trend ATC-6220. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Config.lb 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,135 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end +end Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/Options.lb 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,99 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/auto.c 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,72 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/chip.h 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,22 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_a_trend_atc_6220_ops; +struct mainboard_a_trend_atc_6220_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/irq_tables.c 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,50 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router device */ + 0x600, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x4e, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0a<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0c<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07<<3)|0x1, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x07<<3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/a-trend/atc-6220/mainboard.c 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_a_trend_atc_6220_ops = { + CHIP_NAME("A-Trend ATC-6220 Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/a-trend/atc-6220/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/a-trend/atc-6220/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/a-trend/atc-6220/Config.lb 2007-10-31 00:22:32 UTC (rev 2917) @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target atc-6220 +mainboard a-trend/atc-6220 + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "A-Trend" +option MAINBOARD_PART_NUMBER = "ATC-6220" + +option IRQ_SLOT_COUNT = 7 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

1 0

[LinuxBIOS] r52 - in buildrom-devel: config/payloads config/platforms packages/filo/conf packages/linuxbios packages/linuxbios/patches
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: jcrouse Date: 2007-10-31 01:09:41 +0100 (Wed, 31 Oct 2007) New Revision: 52 Added: buildrom-devel/config/platforms/ga-2761gxdk.conf buildrom-devel/packages/filo/conf/ga-2761gxdk-Config buildrom-devel/packages/linuxbios/ga-2761gxdk-linuxbios.mk buildrom-devel/packages/linuxbios/patches/2761gxdk-fix-target.patch Modified: buildrom-devel/config/payloads/Config.in buildrom-devel/config/platforms/Config.in buildrom-devel/config/platforms/platforms.conf Log: [BUILDROM] Add support for the GIGABYTE GA-2761GXDK Add buildrom support for the new GIGABYTE board added to LinuxBIOS. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: buildrom-devel/config/payloads/Config.in =================================================================== --- buildrom-devel/config/payloads/Config.in 2007-10-30 00:50:43 UTC (rev 51) +++ buildrom-devel/config/payloads/Config.in 2007-10-31 00:09:41 UTC (rev 52) @@ -24,10 +24,12 @@ select PAYLOAD config PAYLOAD_KERNEL + depends !PLATFORM_GA_2761GXDK bool "Linux kernel payload" select PAYLOAD config PAYLOAD_LAB + depends !PLATFORM_GA_2761GXDK bool "Linux As Bootloader" select PAYLOAD Modified: buildrom-devel/config/platforms/Config.in =================================================================== --- buildrom-devel/config/platforms/Config.in 2007-10-30 00:50:43 UTC (rev 51) +++ buildrom-devel/config/platforms/Config.in 2007-10-31 00:09:41 UTC (rev 52) @@ -61,6 +61,11 @@ depends VENDOR_GIGABYTE select PLATFORM +config PLATFORM_GA_2761GXDK + bool "GIGABYTE GA-2761GXDK" + depends VENDOR_GIGABYTE + select PLATFORM + config PLATFORM_TYAN_S2882 bool "Tyan S2882" depends VENDOR_TYAN Added: buildrom-devel/config/platforms/ga-2761gxdk.conf =================================================================== --- buildrom-devel/config/platforms/ga-2761gxdk.conf (rev 0) +++ buildrom-devel/config/platforms/ga-2761gxdk.conf 2007-10-31 00:09:41 UTC (rev 52) @@ -0,0 +1,40 @@ +# Support for the Gigabyte GA-2761GXDK board with the SIS761/966L chipset + +#### Platform configuration + +CC=gcc +STRIP=strip +AS=as + +TARGET_ARCH=i686 +CFLAGS_platform = -m32 + +# Targets + +# Disable for now - I don't know the right kernel for this platform +#KERNEL_MK=$(PACKAGE_DIR)/kernel/ +LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/ga-2761gxdk-linuxbios.mk + +# kernel configuration (for LAB) + +# Disable for now - I don't know the right kernel for this platform +#KERNEL_VERSION=2.6.22.2 +#KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/ +UCLIBC_ARCH=i386 + +# Etherboot configuration +ETHERBOOT_ARCH=i386 + +# LinuxBIOS configuration + +LINUXBIOS_VENDOR=gigabyte +LINUXBIOS_BOARD=ga_2761gxdk +LINUXBIOS_CONFIG=Config.lb +LINUXBIOS_TDIR=ga_2761gxdk +LINUXBIOS_TAG=2908 +LINUXBIOS_ROM_NAME=linuxbios.rom + +# FILO configuration + +FILO_CONFIG=ga-2761gxdk-Config + Modified: buildrom-devel/config/platforms/platforms.conf =================================================================== --- buildrom-devel/config/platforms/platforms.conf 2007-10-30 00:50:43 UTC (rev 51) +++ buildrom-devel/config/platforms/platforms.conf 2007-10-31 00:09:41 UTC (rev 52) @@ -15,5 +15,6 @@ PLATFORM-$(CONFIG_PLATFORM_TYAN_S2882) = tyan-s2882.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf +PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf include $(CONFIG_DIR)/platforms/$(PLATFORM-y) Added: buildrom-devel/packages/filo/conf/ga-2761gxdk-Config =================================================================== --- buildrom-devel/packages/filo/conf/ga-2761gxdk-Config (rev 0) +++ buildrom-devel/packages/filo/conf/ga-2761gxdk-Config 2007-10-31 00:09:41 UTC (rev 52) @@ -0,0 +1,50 @@ +# Use grub instead of autoboot? +USE_GRUB = 1 +# Grub menu.lst path +MENULST_FILE = "hde1:/boot/grub/menu.lst" +# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus +IDE_DISK = 1 +# Add a short delay when polling status registers +# (required on some broken SATA controllers) +IDE_DISK_POLL_DELAY = 1 +# Driver for USB Storage +USB_DISK = 1 +# VGA text console +VGA_CONSOLE = 1 +PC_KEYBOARD = 1 +# Enable the serial console +SERIAL_CONSOLE = 1 +# Serial console; real external serial port +SERIAL_IOBASE = 0x3f8 +SERIAL_SPEED = 115200 +# Filesystems +FSYS_EXT2FS = 1 +FSYS_ISO9660 = 1 +# Support for boot disk image in bootable CD-ROM (El Torito) +ELTORITO = 1 +# PCI support +SUPPORT_PCI = 1 +# Enable this to scan PCI busses above bus 0 +# AMD64 based boards do need this. +PCI_BRUTE_SCAN = 1 +# Loader for standard Linux kernel image, a.k.a. /vmlinuz +LINUX_LOADER = 1 + +# Debugging +#DEBUG_ALL = 1 +#DEBUG_ELFBOOT = 1 +#DEBUG_ELFNOTE = 1 +#DEBUG_LINUXBIOS = 1 +#DEBUG_MALLOC = 1 +#DEBUG_MULTIBOOT = 1 +#DEBUG_SEGMENT = 1 +#DEBUG_SYS_INFO = 1 +#DEBUG_TIMER = 1 +#DEBUG_BLOCKDEV = 1 +#DEBUG_PCI = 1 +#DEBUG_VIA_SOUND = 1 +#DEBUG_LINUXLOAD = 1 +#DEBUG_IDE = 1 +#DEBUG_USB = 1 +#DEBUG_ELTORITO = 1 + Added: buildrom-devel/packages/linuxbios/ga-2761gxdk-linuxbios.mk =================================================================== --- buildrom-devel/packages/linuxbios/ga-2761gxdk-linuxbios.mk (rev 0) +++ buildrom-devel/packages/linuxbios/ga-2761gxdk-linuxbios.mk 2007-10-31 00:09:41 UTC (rev 52) @@ -0,0 +1,31 @@ +# This is the Generic LinuxBIOS target + +ifeq ($(CONFIG_PLATFORM),y) +ifeq ($(LINUXBIOS_TAG),) +$(error You need to specify a version to pull in your platform config) +endif +endif + +LINUXBIOS_PATCHES=$(PACKAGE_DIR)/linuxbios/patches/2761gxdk-fix-target.patch + +LINUXBIOS_BASE_DIR=svn +LINUXBIOS_URL=svn://linuxbios.org/repos/trunk/LinuxBIOSv2 +LINUXBIOS_TARBALL=linuxbios-svn-$(LINUXBIOS_TAG).tar.gz +LINUXBIOS_PAYLOAD_TARGET=$(LINUXBIOS_BUILD_DIR)/payload.elf +TARGET_ROM = $(LINUXBIOS_VENDOR)-$(LINUXBIOS_BOARD).rom + +include $(PACKAGE_DIR)/linuxbios/linuxbios.inc + +$(SOURCE_DIR)/$(LINUXBIOS_TARBALL): + @ echo "Fetching the LinuxBIOS code..." + @ mkdir -p $(SOURCE_DIR)/linuxbios + @ $(BIN_DIR)/fetchsvn.sh $(LINUXBIOS_URL) $(SOURCE_DIR)/linuxbios \ + $(LINUXBIOS_TAG) $(SOURCE_DIR)/$(LINUXBIOS_TARBALL) \ + > $(LINUXBIOS_FETCH_LOG) 2>&1 + +$(OUTPUT_DIR)/$(TARGET_ROM): $(LINUXBIOS_OUTPUT) + @ cat $(LINUXBIOS_OUTPUT) > $@ + +linuxbios: $(OUTPUT_DIR)/$(TARGET_ROM) +linuxbios-clean: generic-linuxbios-clean +linuxbios-distclean: generic-linuxbios-distclean Added: buildrom-devel/packages/linuxbios/patches/2761gxdk-fix-target.patch =================================================================== --- buildrom-devel/packages/linuxbios/patches/2761gxdk-fix-target.patch (rev 0) +++ buildrom-devel/packages/linuxbios/patches/2761gxdk-fix-target.patch 2007-10-31 00:09:41 UTC (rev 52) @@ -0,0 +1,24 @@ +Index: svn/targets/gigabyte/ga_2761gxdk/Config.lb +=================================================================== +--- svn.orig/targets/gigabyte/ga_2761gxdk/Config.lb ++++ svn/targets/gigabyte/ga_2761gxdk/Config.lb +@@ -42,7 +42,8 @@ romimage "normal" + # option ROM_IMAGE_SIZE=0x15800 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +- payload ../../../../payloads/filo_uda1.elf ++# payload ../../../../payloads/filo_uda1.elf ++ payload ../payload.elf + end + + romimage "fallback" +@@ -55,7 +56,8 @@ romimage "fallback" + # option ROM_IMAGE_SIZE=0x15800 + option XIP_ROM_SIZE=0x40000 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" +- payload ../../../../payloads/filo_uda1.elf ++# payload ../../../../payloads/filo_uda1.elf ++ payload ../payload.elf + end + + romimage "failover"

1 0

[LinuxBIOS] r2916 - in trunk/LinuxBIOSv2: src/mainboard/gigabyte src/mainboard/gigabyte/ga-6bxc targets/gigabyte targets/gigabyte/ga-6bxc
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 01:07:31 +0100 (Wed, 31 Oct 2007) New Revision: 2916 Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Options.lb trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/auto.c trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/chip.h trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/mainboard.c trunk/LinuxBIOSv2/targets/gigabyte/ga-6bxc/ trunk/LinuxBIOSv2/targets/gigabyte/ga-6bxc/Config.lb Log: Add initial support for the GIGABYTE GA-6BXC. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Config.lb 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,133 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/ite/it8671f # Super I/O + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.2 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.4 on # APC + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 3f0.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 3f0.7 on # GPIO + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end +end Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/Options.lb 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,99 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/auto.c 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,72 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/ite/it8671f/it8671f_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + it8671f_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/chip.h 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,22 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_gigabyte_ga_6bxc_ops; +struct mainboard_gigabyte_ga_6bxc_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/irq_tables.c 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,49 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router device */ + 0xc00, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x7000, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x8, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x08<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0}, + {0x00,(0x07<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga-6bxc/mainboard.c 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_gigabyte_ga_6bxc_ops = { + CHIP_NAME("GIGABYTE GA-6BXC Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/gigabyte/ga-6bxc/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/gigabyte/ga-6bxc/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/gigabyte/ga-6bxc/Config.lb 2007-10-31 00:07:31 UTC (rev 2916) @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target ga-6bxc +mainboard gigabyte/ga-6bxc + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "GIGABYTE" +option MAINBOARD_PART_NUMBER = "GA-6BXC" + +option IRQ_SLOT_COUNT = 6 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

1 0

[LinuxBIOS] r2915 - in trunk/LinuxBIOSv2: src/mainboard/asus src/mainboard/asus/p3b-f targets/asus targets/asus/p3b-f
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 01:00:57 +0100 (Wed, 31 Oct 2007) New Revision: 2915 Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Options.lb trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/auto.c trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/chip.h trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/mainboard.c trunk/LinuxBIOSv2/targets/asus/p3b-f/ trunk/LinuxBIOSv2/targets/asus/p3b-f/Config.lb Log: Add initial support for the ASUS P3B-F. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Config.lb 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,136 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +# TODO +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end +end Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/Options.lb 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,99 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/auto.c 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,75 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/chip.h 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,22 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_asus_p3b_f_ops; +struct mainboard_asus_p3b_f_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/irq_tables.c 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,51 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x95, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, + {0x00,(0x0e<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x6, 0x0}, + {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p3b-f/mainboard.c 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_asus_p3b_f_ops = { + CHIP_NAME("ASUS P3B-F Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/asus/p3b-f/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/asus/p3b-f/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/asus/p3b-f/Config.lb 2007-10-31 00:00:57 UTC (rev 2915) @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target p3b-f +mainboard asus/p3b-f + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "ASUS" +option MAINBOARD_PART_NUMBER = "P3B-F" + +option IRQ_SLOT_COUNT = 8 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

1 0

[LinuxBIOS] r2914 - in trunk/LinuxBIOSv2: src/mainboard/asus src/mainboard/asus/p2b-f targets/asus targets/asus/p2b-f
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 00:59:47 +0100 (Wed, 31 Oct 2007) New Revision: 2914 Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Options.lb trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/auto.c trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/chip.h trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/mainboard.c trunk/LinuxBIOSv2/targets/asus/p2b-f/ trunk/LinuxBIOSv2/targets/asus/p2b-f/Config.lb Log: Add initial support for the ASUS P2B-F. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Config.lb 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,135 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/x86/mmx/enable_mmx.inc +mainboardinit ./auto.inc +mainboardinit cpu/x86/mmx/disable_mmx.inc + +dir /pc80 +config chip.h + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end +end Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/Options.lb 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,99 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses HAVE_MP_TABLE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN + +default ROM_SIZE = 256 * 1024 +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default HAVE_OPTION_TABLE = 0 +#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc -m32" +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 9 +default MAXIMUM_CONSOLE_LOGLEVEL = 9 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 + +end Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/auto.c 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,75 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" + +/* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" +#include "sdram/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .channel0 = {0x50, 0x51, 0x52, 0x53}, + } + }; + + if (bist == 0) + early_mtrr_init(); + + /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ + w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + enable_smbus(); + /* dump_spd_registers(&memctrl[0]); */ + sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/chip.h 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,22 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_asus_p2b_f_ops; +struct mainboard_asus_p2b_f_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/irq_tables.c 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,50 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xf9, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x0d<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x5, 0x0}, + {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b-f/mainboard.c 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_asus_p2b_f_ops = { + CHIP_NAME("ASUS P2B-F Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/asus/p2b-f/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/asus/p2b-f/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/asus/p2b-f/Config.lb 2007-10-30 23:59:47 UTC (rev 2914) @@ -0,0 +1,49 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +target p2b-f +mainboard asus/p2b-f + +option ROM_SIZE = 256 * 1024 + +option MAINBOARD_VENDOR = "ASUS" +option MAINBOARD_PART_NUMBER = "P2B-F" + +option IRQ_SLOT_COUNT = 7 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload /tmp/filo.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload /tmp/filo.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] r2913 - in trunk/LinuxBIOSv2: src/mainboard/asus/p2b targets/asus/p2b
by svn＠openbios.org 31 Oct '07

31 Oct '07

Author: uwe Date: 2007-10-31 00:57:59 +0100 (Wed, 31 Oct 2007) New Revision: 2913 Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/irq_tables.c Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Options.lb trunk/LinuxBIOSv2/src/mainboard/asus/p2b/auto.c trunk/LinuxBIOSv2/src/mainboard/asus/p2b/chip.h trunk/LinuxBIOSv2/src/mainboard/asus/p2b/mainboard.c trunk/LinuxBIOSv2/targets/asus/p2b/Config.lb Log: Various smaller fixes to make the ASUS P2B match the format of all the other boards in this patch series. Add missing PIRQ table to make most devices work. Enable VGA support. Add flashrom flashing protection code. Make CPU init actually work (result: massive speed-up). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb 2007-10-30 21:55:11 UTC (rev 2912) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Config.lb 2007-10-30 23:57:59 UTC (rev 2913) @@ -25,7 +25,8 @@ default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) default ROM_SECTION_OFFSET = 0 end -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) default XIP_ROM_SIZE = 64 * 1024 @@ -80,11 +81,16 @@ config chip.h chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) + device apic 0 on end # APIC + end + end device pci_domain 0 on # PCI domain device pci 0.0 on end # Host bridge - device pci 1.0 on end # AGP bridge + device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA + device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O device pnp 3f0.0 on # Floppy io 0x60 = 0x3f0 @@ -99,11 +105,11 @@ io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 3f0.3 on # COM2 + device pnp 3f0.3 on # COM2 / IR io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 3f0.5 on # PS/2 keyboard + device pnp 3f0.5 on # PS/2 keyboard / mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 # PS/2 keyboard interrupt @@ -126,6 +132,4 @@ register "ide1_enable" = "1" end end - chip cpu/intel/socket_PGA370 - end end Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Options.lb 2007-10-30 21:55:11 UTC (rev 2912) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/Options.lb 2007-10-30 23:57:59 UTC (rev 2913) @@ -59,18 +59,27 @@ uses TTYS0_BASE uses TTYS0_LCS uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses CONFIG_CONSOLE_VGA +uses CONFIG_PCI_ROM_RUN default ROM_SIZE = 256 * 1024 default HAVE_FALLBACK_BOOT = 1 default HAVE_MP_TABLE = 0 default HAVE_HARD_RESET = 0 -default HAVE_PIRQ_TABLE = 0 -default IRQ_SLOT_COUNT = 4 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 0 # Override this in targets/*/Config.lb. +default MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. +default MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 default HAVE_OPTION_TABLE = 0 -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = 131072 -default STACK_SIZE = 0x2000 -default HEAP_SIZE = 0x4000 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default USE_OPTION_TABLE = 0 default _RAMBASE = 0x00004000 @@ -81,9 +90,10 @@ default CONFIG_CONSOLE_SERIAL8250 = 1 default TTYS0_BAUD = 115200 default TTYS0_BASE = 0x3f8 -default TTYS0_LCS = 0x3 +default TTYS0_LCS = 0x3 # 8n1 default DEFAULT_CONSOLE_LOGLEVEL = 9 default MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_UDELAY_TSC = 1 +default CONFIG_CONSOLE_VGA = 1 +default CONFIG_PCI_ROM_RUN = 1 end Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/auto.c 2007-10-30 21:55:11 UTC (rev 2912) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/auto.c 2007-10-30 23:57:59 UTC (rev 2913) @@ -30,13 +30,13 @@ #include "arch/i386/lib/console.c" #include "ram/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" -#include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "northbridge/intel/i440bx/raminit.h" -#include "mainboard/bitworks/ims/debug.c" /* FIXME */ +#include "mainboard/asus/mew-vm/debug.c" /* FIXME */ #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -64,10 +64,9 @@ w83977tf_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); - report_bist_failure(bist); enable_smbus(); - dump_spd_registers(&memctrl[0]); + /* dump_spd_registers(&memctrl[0]); */ sdram_initialize(sizeof(memctrl) / sizeof(memctrl[0]), memctrl); - ram_check(0, 640 * 1024); + /* ram_check(0, 640 * 1024); */ } Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/chip.h 2007-10-30 21:55:11 UTC (rev 2912) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/chip.h 2007-10-30 23:57:59 UTC (rev 2913) @@ -19,7 +19,4 @@ */ extern struct chip_operations mainboard_asus_p2b_ops; - -struct mainboard_asus_p2b_config { - int nothing; -}; +struct mainboard_asus_p2b_config {}; Added: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/irq_tables.c 2007-10-30 23:57:59 UTC (rev 2913) @@ -0,0 +1,49 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, + PIRQ_VERSION, + 32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x04 << 3) | 0x0, /* Interrupt router device */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x54, /* Checksum */ + { + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0}, + {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0}, + {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0}, + {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0}, + {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Modified: trunk/LinuxBIOSv2/src/mainboard/asus/p2b/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/asus/p2b/mainboard.c 2007-10-30 21:55:11 UTC (rev 2912) +++ trunk/LinuxBIOSv2/src/mainboard/asus/p2b/mainboard.c 2007-10-30 23:57:59 UTC (rev 2913) @@ -24,4 +24,3 @@ struct chip_operations mainboard_asus_p2b_ops = { CHIP_NAME("ASUS P2B Mainboard") }; - Modified: trunk/LinuxBIOSv2/targets/asus/p2b/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/asus/p2b/Config.lb 2007-10-30 21:55:11 UTC (rev 2912) +++ trunk/LinuxBIOSv2/targets/asus/p2b/Config.lb 2007-10-30 23:57:59 UTC (rev 2913) @@ -23,16 +23,25 @@ option ROM_SIZE = 256 * 1024 +option MAINBOARD_VENDOR = "ASUS" +option MAINBOARD_PART_NUMBER = "P2B" + +option IRQ_SLOT_COUNT = 6 + +option DEFAULT_CONSOLE_LOGLEVEL = 9 +option MAXIMUM_CONSOLE_LOGLEVEL = 9 + +option CONFIG_CONSOLE_VGA = 1 +option CONFIG_PCI_ROM_RUN = 1 + romimage "normal" option USE_FALLBACK_IMAGE = 0 - option ROM_IMAGE_SIZE = 64 * 1024 option LINUXBIOS_EXTRA_VERSION = ".0Normal" payload /tmp/filo.elf end romimage "fallback" option USE_FALLBACK_IMAGE = 1 - option ROM_IMAGE_SIZE = 64 * 1024 option LINUXBIOS_EXTRA_VERSION = ".0Fallback" payload /tmp/filo.elf end

1 0

[LinuxBIOS] r2912 build service
by LinuxBIOS information 30 Oct '07

30 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2912 to the LinuxBIOS source repository and caused the following changes: Change Log: Various fixes and improvements of the 82801xx code. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=hdama&vendor=… Compilation of gigabyte:ga_2761gxdk is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=ga_2761gxdk&v… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2912&device=khepri&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] r2912 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx
by svn＠openbios.org 30 Oct '07

30 Oct '07

Author: uwe Date: 2007-10-30 22:55:11 +0100 (Tue, 30 Oct 2007) New Revision: 2912 Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c Log: Various fixes and improvements of the 82801xx code. Signed-off-by: Joseph Smith <joe(a)smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h 2007-10-30 17:53:53 UTC (rev 2911) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx.h 2007-10-30 21:55:11 UTC (rev 2912) @@ -33,21 +33,30 @@ #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 -#define PCICMD 0x04 #define PMBASE 0x40 -#define PM_BASE_ADDR 0x1100 #define ACPI_CNTL 0x44 #define BIOS_CNTL 0x4E -#define GPIO_BASE 0x58 -#define GPIO_BASE_ADDR 0x1180 -#define GPIO_CNTL 0x5C +#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */ +#define GPIO_BASE_ICH6_9 0x48 /* LPC GPIO Base Address Register (ICH6-ICH9) */ +#define GPIO_CNTL_ICH0_5 0x5C /* LPC GPIO Control Register (ICH0-ICH5) */ +#define GPIO_CNTL_ICH6_9 0x4C /* LPC GPIO Control Register (ICH6-ICH9) */ + #define PIRQA_ROUT 0x60 +#define PIRQB_ROUT 0x61 +#define PIRQC_ROUT 0x62 +#define PIRQD_ROUT 0x63 #define PIRQE_ROUT 0x68 -#define COM_DEC 0xE0 -#define LPC_EN 0xE6 +#define PIRQF_ROUT 0x69 +#define PIRQG_ROUT 0x6A +#define PIRQH_ROUT 0x6B + #define FUNC_DIS 0xF2 -#define CMD 0x04 +#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */ +#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */ +#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */ + #define SBUS_NUM 0x19 #define SUB_BUS_NUM 0x1A #define SMLT 0x1B Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2007-10-30 17:53:53 UTC (rev 2911) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_lpc.c 2007-10-30 21:55:11 UTC (rev 2912) @@ -32,14 +32,53 @@ #include <arch/io.h> #include "i82801xx.h" +#define PMBASE_ADDR 0x00000400 /* ACPI Base Address Register */ +#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */ + #define NMI_OFF 0 -void i82801xx_enable_ioapic(struct device *dev) +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +#define PIRQA 0x03 +#define PIRQB 0x05 +#define PIRQC 0x06 +#define PIRQD 0x07 +#define PIRQE 0x09 +#define PIRQF 0x0A +#define PIRQG 0x0B +#define PIRQH 0x0C + +void i82801xx_enable_apic(struct device *dev) { uint32_t reg32; volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec00000; volatile uint32_t *ioapic_data = (volatile uint32_t *)0xfec00010; + /* Set ACPI base address (I/O space). */ + pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); + + /* Enable ACPI I/O and power management. */ + pci_write_config8(dev, ACPI_CNTL, 0x10); + reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (3 << 7); /* Enable IOAPIC */ reg32 |= (1 << 13); /* Coprocessor error enable */ @@ -58,8 +97,8 @@ die("APIC Error\n"); /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; // Select Boot Configuration register - *ioapic_data = 1; // Use Processor System Bus to deliver interrupts + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } void i82801xx_enable_serial_irqs(struct device *dev) @@ -72,22 +111,67 @@ /* TODO: Explain/#define the real meaning of these magic numbers. */ } -void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask) +static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) { - uint16_t reg16; - int i; + /* Route PIRQA - PIRQD. */ + pci_write_config8(dev, PIRQA_ROUT, PIRQA); + pci_write_config8(dev, PIRQB_ROUT, PIRQB); + pci_write_config8(dev, PIRQC_ROUT, PIRQC); + pci_write_config8(dev, PIRQD_ROUT, PIRQD); - reg16 = pci_read_config16(dev, PCI_DMA_CFG); - reg16 &= 0x300; - for (i = 0; i < 8; i++) { - if (i == 4) - continue; - reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); + /* Route PIRQE - PIRQH (for ICH2-ICH9). */ + if (ich_model >= 0x2440) { + pci_write_config8(dev, PIRQE_ROUT, PIRQE); + pci_write_config8(dev, PIRQF_ROUT, PIRQF); + pci_write_config8(dev, PIRQG_ROUT, PIRQG); + pci_write_config8(dev, PIRQH_ROUT, PIRQH); } - pci_write_config16(dev, PCI_DMA_CFG, reg16); } -/* TODO: Needs serious cleanup/comments. */ +static void i82801xx_power_options(device_t dev) +{ + uint8_t byte; + int pwr_on = -1; + int nmi_option; + + /* power after power fail */ + /* FIXME this doesn't work! */ + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + */ + pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); + printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + + /* Set up NMI on errors. */ + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); + + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + byte &= ~(1 << 7); /* Set NMI. */ + outb(byte, 0x70); + } +} + +static void gpio_init(device_t dev, uint16_t ich_model) +{ + /* Set the value for GPIO base address register and enable GPIO. + * Note: ICH-ICH5 registers differ from ICH6-ICH9. + */ + if (ich_model <= 0x24D0) { + pci_write_config32(dev, GPIO_BASE_ICH0_5, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH0_5, 0x10); + } else if (ich_model >= 0x2640) { + pci_write_config32(dev, GPIO_BASE_ICH6_9, (GPIO_BASE_ADDR | 1)); + pci_write_config8(dev, GPIO_CNTL_ICH6_9, 0x10); + } +} + void i82801xx_rtc_init(struct device *dev) { uint8_t reg8; @@ -97,46 +181,47 @@ reg8 = pci_read_config8(dev, GEN_PMCON_3); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { - reg8 &= ~(1 << 1); /* preserve the power fail state */ + reg8 &= ~(1 << 1); /* Preserve the power fail state. */ pci_write_config8(dev, GEN_PMCON_3, reg8); } reg32 = pci_read_config32(dev, GEN_STS); rtc_failed |= reg32 & (1 << 2); rtc_init(rtc_failed); + + /* Enable access to the upper 128 byte bank of CMOS RAM. */ + pci_write_config8(dev, RTC_CONF, 0x04); } -void i82801xx_1f0_misc(struct device *dev) +void i82801xx_lpc_route_dma(struct device *dev, uint8_t mask) { - /* TODO: break this down into smaller functions */ + uint16_t reg16; + int i; - //move to acpi_enable or something - /* Set ACPI base address to 0x1100 (I/O space) */ - pci_write_config32(dev, PMBASE, PM_BASE_ADDR | 1); - /* Enable ACPI I/O and power management */ - pci_write_config8(dev, ACPI_CNTL, 0x10); - /* Set GPIO base address to 0x1180 (I/O space) */ - pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDR | 1); - /* Enable GPIO */ - pci_write_config8(dev, GPIO_CNTL, 0x10); + reg16 = pci_read_config16(dev, PCI_DMA_CFG); + reg16 &= 0x300; + for (i = 0; i < 8; i++) { + if (i == 4) + continue; + reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); + } + pci_write_config16(dev, PCI_DMA_CFG, reg16); +} - //get rid of? - /* Route PIRQA to IRQ11, PIRQB to IRQ3, PIRQC to IRQ5, PIRQD to IRQ10 */ - pci_write_config32(dev, PIRQA_ROUT, 0x0A05030B); - /* Route PIRQE to IRQ7. Leave PIRQF - PIRQH unrouted */ - pci_write_config8(dev, PIRQE_ROUT, 0x07); - - //move to i82801xx_init - /* Prevent LPC disabling, enable parity errors, and SERR# (System Error) */ - pci_write_config16(dev, PCI_COMMAND, 0x014f); - /* Enable access to the upper 128 byte bank of CMOS RAM */ - pci_write_config8(dev, RTC_CONF, 0x04); - /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB */ - pci_write_config8(dev, COM_DEC, 0x10); - /* LPT decode defaults to 0x378-0x37F and 0x778-0x77F - * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7 */ - /* Enable: COMA, COMB, LPT, Floppy - * Disable: Microcontroller, Sound, Gameport */ - pci_write_config16(dev, LPC_EN, 0x000F); +static void i82801xx_lpc_decode_en(device_t dev, uint16_t ich_model) +{ + /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. + * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. + * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. + * We also need to set the value for LPC I/F Enables Register. + * Note: ICH-ICH5 registers differ from ICH6-ICH9. + */ + if (ich_model <= 0x24D0) { + pci_write_config8(dev, COM_DEC, 0x10); + pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F); + } else if (ich_model >= 0x2640) { + pci_write_config8(dev, LPC_IO_DEC, 0x10); + pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F); + } } static void enable_hpet(struct device *dev) @@ -146,7 +231,7 @@ uint32_t code = (0 & 0x3); reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET */ + reg32 |= (1 << 17); /* Enable HPET. */ /* * Bits [16:15] Memory Address Range * 00 FED0_0000h - FED0_03FFh @@ -156,67 +241,45 @@ */ reg32 &= ~(3 << 15); /* Clear it */ reg32 |= (code << 15); - /* reg32 is never written to anywhere? */ + /* TODO: reg32 is never written to anywhere? */ printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); #endif } static void lpc_init(struct device *dev) { - uint8_t byte; - int pwr_on = -1; - int nmi_option; + uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); - /* IO APIC initialization */ - i82801xx_enable_ioapic(dev); + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + /* IO APIC initialization. */ + i82801xx_enable_apic(dev); + i82801xx_enable_serial_irqs(dev); - /* TODO: Find out if this is being used/works */ -#ifdef SUSPICIOUS_LOOKING_CODE - /* The ICH-4 datasheet does not mention this configuration register. - * This code may have been inherited (incorrectly) from code for - * the AMD 766 southbridge, which *does* support this functionality. - */ + /* Setup the PIRQ. */ + i82801xx_pirq_init(dev, ich_model); - /* Posted memory write enable */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif + /* Setup power options. */ + i82801xx_power_options(dev); - /* power after power fail */ - /* FIXME this doesn't work! */ - /* Which state do we want to goto after g3 (power restored)? - * 0 == S0 Full On - * 1 == S5 Soft Off - */ - pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + /* Set the state of the GPIO lines. */ + gpio_init(dev, ich_model); - /* Set up NMI on errors */ - byte = inb(0x61); - byte &= ~(1 << 3); /* IOCHK# NMI Enable */ - byte &= ~(1 << 2); /* PCI SERR# Enable */ - outb(byte, 0x61); - byte = inb(0x70); - - nmi_option = NMI_OFF; - get_option(&nmi_option, "nmi"); - if (nmi_option) { - byte &= ~(1 << 7); /* Set NMI */ - outb(byte, 0x70); - } - - /* Initialize the real time clock */ + /* Initialize the real time clock. */ i82801xx_rtc_init(dev); + /* Route DMA. */ i82801xx_lpc_route_dma(dev, 0xff); - /* Initialize isa dma */ + /* Initialize ISA DMA. */ isa_dma_init(); - i82801xx_1f0_misc(dev); - /* Initialize the High Precision Event Timers, if present */ + /* Setup decode ports and LPC I/F enables. */ + i82801xx_lpc_decode_en(dev, ich_model); + + /* Initialize the High Precision Event Timers, if present. */ enable_hpet(dev); } @@ -224,10 +287,10 @@ { struct resource *res; - /* Get the normal pci resources of this device */ + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); - /* Add an extra subtractive resource for both memory and I/O */ + /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;

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coreboot October 2007