coreboot October 2007

coreboot@coreboot.org

84 participants
481 discussions

[LinuxBIOS] [BUILDROM] Missing Serengeti-Cheetah file
by Jordan Crouse 09 Nov '07

09 Nov '07

I missed a patch file when I added the S-C stuff to buildrom last week. THis just patches LB to use ../payload.elf as the target (an unfortunate v2 side effect). -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc. [BUILDROM] Missing Serengeti-Cheetah file This file should have gone with the rest of the patch - it patches LinuxBIOS to look for payload in ../ Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Index: buildrom-devel/packages/… [View More]linuxbios/patches/s-c-buildrom-payload.patch =================================================================== --- /dev/null +++ buildrom-devel/packages/linuxbios/patches/s-c-buildrom-payload.patch @@ -0,0 +1,45 @@ +Index: svn/targets/amd/serengeti_cheetah/Config.lb +=================================================================== +--- svn.orig/targets/amd/serengeti_cheetah/Config.lb ++++ svn/targets/amd/serengeti_cheetah/Config.lb +@@ -29,7 +29,7 @@ romimage "normal" + # payload ../../../payloads/tg3.zelf + # payload ../../../../payloads/tg3_vga.zelf + # payload ../../../../payloads/tg3--filo_hda2_vga.zelf +- payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf ++# payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf + # payload ../../../../payloads/e1000_vga.zelf + # payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf + # payload ../../../payloads/tg3_com2.zelf +@@ -38,6 +38,7 @@ romimage "normal" + # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf + # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf + # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf ++ payload ../payload.elf + end + + romimage "fallback" +@@ -62,7 +63,7 @@ romimage "fallback" + # payload ../../../../payloads/filo_hda.zelf + # payload ../../../../payloads/tg3--filo_hda2_vga.zelf + # payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf +- payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf ++# payload ../../../../payloads/tg3--filo_hda2_vga_5.4.1.zelf + # payload ../../../../payloads/filo_hda2_novga.zelf + # payload ../../../payloads/tg3_com2.zelf + # payload ../../../payloads/e1000--filo.zelf +@@ -70,6 +71,7 @@ romimage "fallback" + # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf + # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf + # payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf ++ payload ../payload.elf + end + + romimage "failover" +@@ -81,5 +83,5 @@ romimage "failover" + end + + +-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover" ++buildrom ./serengeti_cheetah.rom ROM_SIZE "normal" "fallback" "failover" + #buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" [View Less]

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Re: [LinuxBIOS] #35: Make it possible to boot Windows using LinuxBIOS
by LinuxBIOS 09 Nov '07

09 Nov '07

#35: Make it possible to boot Windows using LinuxBIOS ----------------------------+----------------------------------------------- Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: critical | Milestone: Going mainstream Component: code | Version: v2 Resolution: | Keywords: Dependencies: | Patchstatus: … [View More]

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[LinuxBIOS] #80: serial console in grub2 works
by LinuxBIOS 07 Nov '07

07 Nov '07

#80: serial console in grub2 works ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: oxygene Type: enhancement | Status: new Priority: major | Milestone: Port GRUB2 to LinuxBIOS Component: code | Version: v3 Keywords: | Dependencies: … [View More]

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[LinuxBIOS] LinuxBIOS and FreeBSD
by Philip Schulz 05 Nov '07

05 Nov '07

Hi, I recently played around with LinuxBIOS and FreeBSD. In short, it somewhat works in QEMU using ADLO, see [1]. While trying to build LinuxBIOS and ADLO on FreeBSD, I came across some problems. They all come from the assumption that "make" is "GNU make" which isn't true on the BSDs. I've uploaded some really hackish patches to [2]. Unfortunately, I have no idea how to detect FreeBSD from a Makefile or a Python script. But maybe someone on this list knows and wants enhance the … [View More]

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[LinuxBIOS] patch 2:corrected alix1c memory size
by ron minnich 05 Nov '07

05 Nov '07

This patch has the fix and the memory size is now right. thanks ron p.s. will send memory image and instructions to anyone who wants to take a try.

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[LinuxBIOS] [IMPORT] GIGABYTE GA-2761GXDK
by Morgan Tsai 05 Nov '07

05 Nov '07

Copyright (C) 2007 Morgan Tsai <my_tsai(a)sis.com> Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) Change Log: Newly support GIGABYTE GA-2761GXDK CPU type: AMD AM2 socket Northbridge: SiS 761GX Southbridge: SiS 966 SuperIO: ITE8716F The board is still under testing sample. When we finish test without major problems, this sample will soon become marketing board. Signed-off-by: Morgan Tsai <my_tsai(a)sis.com>

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[LinuxBIOS] [PATCH] Adding AXUS TC320 LinuxBIOSv2 support
by Juergen Beisert 04 Nov '07

04 Nov '07

Hi, below find the patch to support the AXUS TC320 terminal in LinuxBIOS. This terminal is a Geode GX1 based board like the BCOM Winnet. -> http://linuxbios.org/AXUS_WINTERM_Build_Tutorial Patch should apply against LinuxBIOSv2 version 2895 (2007-10-24). From: Juergen Beisert <juergen(a)kreuzholzen.de> This patch adds the AXUS TC320 to LinuxBIOSv2. This board uses nearly the same devices than the BCOM Winnet100, so most of the new code here is from the BCOM Winnet100. They … [View More]differ in the IRQ routing table only. BTW: The AXUS board uses standard DIMM memory and can be run at 100MHz SDRAM clock speed (it runs reliably here since month). Signed-off-by: Juergen Beisert <juergen(a)kreuzholzen.de> src/mainboard/axus/tc320/Config.lb | 131 ++++++++++++++++++++++++++++++++++ src/mainboard/axus/tc320/Options.lb | 102 ++++++++++++++++++++++++++ src/mainboard/axus/tc320/auto.c | 53 +++++++++++++ src/mainboard/axus/tc320/chip.h | 25 ++++++ src/mainboard/axus/tc320/irq_tables.c | 122 +++++++++++++++++++++++++++++++ src/mainboard/axus/tc320/mainboard.c | 26 ++++++ targets/axus/tc320/Config.lb | 53 +++++++++++++ 7 files changed, 512 insertions(+) --- Index: src/mainboard/axus/tc320/Config.lb =================================================================== --- src/mainboard/axus/tc320/Config.lb (Revision 0) +++ src/mainboard/axus/tc320/Config.lb (Revision 0) @@ -0,0 +1,131 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +dir /pc80 +config chip.h + +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + device pci 12.0 on + chip superio/nsc/pc97317 + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe800 + end + register "com1" = "{115200}" + register "com2" = "{38400}" + end + device pci 12.1 off end # SMI + device pci 12.2 off end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA + device pci 13.0 on end # USB + end + end + end + chip cpu/amd/model_gx1 + end +end Index: src/mainboard/axus/tc320/irq_tables.c =================================================================== --- src/mainboard/axus/tc320/irq_tables.c (Revision 0) +++ src/mainboard/axus/tc320/irq_tables.c (Revision 0) @@ -0,0 +1,122 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * Interrupt routing description for AXUS's TC320 board. + * It was not possible to read back the pirq-Table. There was no BIOS to ask + * for it, only a bootloader for an embedded OS... + * But with the method described here: + * http://linuxbios.org/Creating_Valid_IRQ_Tables + * it was possible to detect the physical IRQ routing on this board + * + * This is the physical routing on this board: + * + * IRQ 5530 USB Network + * controller northbridge device device + * 00.13.0 00.0e.00 + * -------------------------------------------- + * 11 INTA# INTA# n.c. + * 15 INTB# n.c. INTA# + * INTC# n.c. n.c. + * INTD# n.c. n.c. + */ + +#include <arch/pirq_routing.h> + +#define INT_A 0x01 +#define INT_B 0x02 +#define INT_C 0x03 +#define INT_D 0x04 + +/* + * the USB controller should be connected to IRQ11, + * the network controller should be connected to IRQ15 + */ + +#define IRQ_BITMAP_LINK0 0x0800 +#define IRQ_BITMAP_LINK1 0x8000 +#define IRQ_BITMAP_LINK2 0x0000 +#define IRQ_BITMAP_LINK3 0x0000 + +/** Reserved interrupt channels for exclusive PCI usage. */ +#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK1) + +/** + * Routing description. + * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx + */ +const struct irq_routing_table intel_irq_routing_table = { + .signature = PIRQ_SIGNATURE, /* PIRQ signature */ + .version = PIRQ_VERSION, /* PIRQ version */ + .size = 32 + 16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */ + .rtr_bus = 0x00, /* Interrupt router bus */ + .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ + .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ + .rtr_vendor = 0x1078, /* Vendor */ + .rtr_device = 0x0100, /* Device */ + .miniport_data = 0, /* Crap (miniport) */ + .checksum = 0xe3, /* Checksum */ + .slots = { + /* + * Definition for "slot#1". There is no real slot, + * the USB device is embedded... + */ + [0] = { + .bus = 0x00, + .devfn = (0x13 << 3) | 0x0, + .irq = { + /* Link Bitmap */ + [0] = { INT_A, IRQ_BITMAP_LINK0 }, + [1] = { INT_B, IRQ_BITMAP_LINK1 }, + [2] = { INT_C, IRQ_BITMAP_LINK2 }, + [3] = { INT_D, IRQ_BITMAP_LINK3 } + }, + .slot = 0x0, + }, + /* + * Definition for "slot#2". There is no real slot, + * the network device is soldered... + */ + [1] = { + .bus = 0x00, + .devfn = (0x0e << 3) | 0x0, + .irq = { + /* Link Bitmap */ + [0] = { INT_B, IRQ_BITMAP_LINK1 }, + [1] = { INT_C, IRQ_BITMAP_LINK2 }, + [2] = { INT_D, IRQ_BITMAP_LINK3 }, + [3] = { INT_A, IRQ_BITMAP_LINK0 }, + }, + .slot = 0x0, + } + } +}; + +/** + * Copy the IRQ routing table to memory. + * + * @param[in] addr destination address (between 0xF0000...0x100000) + * @return TODO + **/ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Index: src/mainboard/axus/tc320/Options.lb =================================================================== --- src/mainboard/axus/tc320/Options.lb (Revision 0) +++ src/mainboard/axus/tc320/Options.lb (Revision 0) @@ -0,0 +1,102 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +default CONFIG_GX1_VIDEO = 1 +default CONFIG_GX1_VIDEOMODE = 0 +default CONFIG_SPLASH_GRAPHIC = 1 +default CONFIG_VIDEO_MB = 2 + +default ROM_SIZE = 256 * 1024 +default MAINBOARD_VENDOR = "AXUS" +default MAINBOARD_PART_NUMBER = "TC320" +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots +default HAVE_OPTION_TABLE = 0 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc " +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 6 +default MAXIMUM_CONSOLE_LOGLEVEL = 6 + +end Index: src/mainboard/axus/tc320/auto.c =================================================================== --- src/mainboard/axus/tc320/auto.c (Revision 0) +++ src/mainboard/axus/tc320/auto.c (Revision 0) @@ -0,0 +1,53 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "superio/nsc/pc97317/pc97317_early_serial.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Initialize RAM. */ + sdram_init(); + + /* Check whether RAM works. */ + /* ram_check(0, 640 * 1024); */ +} Index: src/mainboard/axus/tc320/chip.h =================================================================== --- src/mainboard/axus/tc320/chip.h (Revision 0) +++ src/mainboard/axus/tc320/chip.h (Revision 0) @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_axus_tc320_ops; + +struct mainboard_axus_tc320_config { + int nothing; +}; Index: src/mainboard/axus/tc320/mainboard.c =================================================================== --- src/mainboard/axus/tc320/mainboard.c (Revision 0) +++ src/mainboard/axus/tc320/mainboard.c (Revision 0) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_axus_tc320_ops = { + CHIP_NAME("AXUS TC320 Mainboard") +}; Index: targets/axus/tc320/Config.lb =================================================================== --- targets/axus/tc320/Config.lb (Revision 0) +++ targets/axus/tc320/Config.lb (Revision 0) @@ -0,0 +1,53 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## See also: http://linuxbios.org/AXUS_WINTERM_Build_Tutorial + +target tc320 +mainboard axus/tc320 + +option ROM_SIZE = 256 * 1024 + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +option CONFIG_GX1_VIDEO = 1 +option CONFIG_GX1_VIDEOMODE = 0 +option CONFIG_SPLASH_GRAPHIC = 1 +option CONFIG_VIDEO_MB = 2 + +option DEFAULT_CONSOLE_LOGLEVEL = 6 +option MAXIMUM_CONSOLE_LOGLEVEL = 6 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = 64 * 1024 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload ../../../../../../../images/etherboot.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 64 * 1024 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload ../../../../../../../images/etherboot.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" [View Less]

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[LinuxBIOS] [PATCH] Add support for the Asus A8V-E SE motherboard
by Rudolf Marek 03 Nov '07

03 Nov '07

Hello all, I'm attaching the patch to add support for Asus A8V-E SE motherboard. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> I tried to clean the code as much as possible, but I left there the CMOS setting, cause removing the file will cause a lot of trouble and I cannot figure out how to fix that. Same applies for Config.lb and Option.lb files. I fixed the ACPI dsdt build, and FADT table uses static resources defined in SB, so it will be always consistent with SB implementation. Thanks, Rudolf

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Re: [LinuxBIOS] r2921 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
by Uwe Hermann 02 Nov '07

02 Nov '07

On Wed, Oct 31, 2007 at 01:49:39AM +0100, svn(a)openbios.org wrote: > Author: hailfinger > Date: 2007-10-31 01:49:38 +0100 (Wed, 31 Oct 2007) > New Revision: 2921 > > Modified: > trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c > Log: > As started in > http://www.linuxbios.org/pipermail/linuxbios/2007-October/025385.html , > but change all apparantly related values that differ on my board with > legacy BIOS. > > This makes both PCI … [View More]cards appear, as well as the firewire device > TSB43AB23. > * PCI 01:07.0 appears fully functional > * PCI 01:08.0 (closer to the board edge) appears, but no interrupts > * PCI 01:0a.0 (FireWire) untested > > Since none of these was even present without the patch I suggest to > apply it. > > Signed-off-by: Torsten Duwe <duwe(a)lst.de> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Tested-by: Harald Gutmann <harald.gutmann(a)gmx.net> > > > Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c > =================================================================== > --- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-10-31 00:26:08 UTC (rev 2920) > +++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2007-10-31 00:49:38 UTC (rev 2921) > @@ -134,10 +134,10 @@ > #define MCP55_PCI_E_X_0 0 > > #define MCP55_MB_SETUP \ > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ > - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \ > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \ > + RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \ > RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ > RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ Can somebody please update the wiki status page? Thanks, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org [View Less]

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[LinuxBIOS] dualcore trouble with LB - opteron 175
by Rudolf Marek 02 Nov '07

02 Nov '07

Hello all, I have new CPU opteron 175 - sigle cpu dualcore, I'm not able to initialize AP properly. http://assembler.cz/download/minicom_dc.txt It seems I can boot them, but they never arrive to check point. Any idea what might be wrong? Also I don't know why my core1 have APIC ID 0x11 instead of APIC ID 0x1... Any help very appreciated. Thanks, Rudolf

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coreboot October 2007