coreboot October 2007

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[LinuxBIOS] superiotool - dump support for fdc37b72x
by Robinson Tryon 07 Oct '07

07 Oct '07

Signed-off-by: Robinson P. Tryon <bishop.robinson(a)gmail.com> I did my best to interpret the data sheet properly. I wasn't sure if the TEST registers were important or not, so I left them in. I'm still not sure about whether I should put a copyright notice in the file, so feel free to keep or kill that line as appropriate.

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[LinuxBIOS] r2838 - trunk/util/superiotool
by svn＠openbios.org 07 Oct '07

07 Oct '07

Author: uwe Date: 2007-10-07 23:50:29 +0200 (Sun, 07 Oct 2007) New Revision: 2838 Modified: trunk/util/superiotool/ite.c Log: Some more ITE chips and small fixes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2007-10-07 21:48:26 UTC (rev 2837) +++ trunk/util/superiotool/ite.c 2007-10-07 21:50:29 UTC (rev 2838) @@ -26,7 +26,6 @@ #define CHIP_VERSION_REG 0x22 -/* Note: IT8726F has ID 0x8726 (datasheet wrongly says 0x8716). */ const static struct superio_registers reg_table[] = { {0x8661, "IT8661F", { /* TODO: Needs different init sequence. */ @@ -64,7 +63,7 @@ {EOT}}}, {0x8702, "IT8702F", { {EOT}}}, - {0x8705, "IT8705F/AF or IT8700F", { + {0x8705, "IT8705F/AF / IT8700F", { {NOLDN, NULL, {0x07,0x20,0x21,0x22,0x23,0x24,EOT}, {NANA,0x87,0x05,0x00,0x00,NANA,EOT}}, @@ -112,6 +111,9 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, {EOT}}}, + {0x8706, "IT8706R", { /* TODO: Not yet in sensors-detect */ + /* This is a "Special General Purpose I/O chip". */ + {EOT}}}, {0x8708, "IT8708F", { {NOLDN, NULL, {0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, @@ -167,7 +169,7 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x00,0x0a,0x00,EOT}}, {EOT}}}, - {0x8710, "IT8710F", { + {0x8710, "IT8710F", { /* TODO: Not yet in sensors-detect */ {EOT}}}, {0x8712, "IT8712F", { {NOLDN, NULL, @@ -316,6 +318,9 @@ {0x30,0x60,0x61,0x70,0xf0,EOT}, {0x00,0x03,0x10,0x0b,0x00,EOT}}, {EOT}}}, + {0x8726, "IT8726F", { + /* Datasheet wrongly says that the ID is 0x8716. */ + {EOT}}}, {EOT} };

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[LinuxBIOS] r2837 - trunk/util/superiotool
by svn＠openbios.org 07 Oct '07

07 Oct '07

Author: uwe Date: 2007-10-07 23:48:26 +0200 (Sun, 07 Oct 2007) New Revision: 2837 Modified: trunk/util/superiotool/nsc.c Log: Detection support for a bunch of NSC Super I/Os (trivial). Also, dump support for the NSC PC87351. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/nsc.c =================================================================== --- trunk/util/superiotool/nsc.c 2007-10-07 21:00:02 UTC (rev 2836) +++ trunk/util/superiotool/nsc.c 2007-10-07 21:48:26 UTC (rev 2837) @@ -24,10 +24,74 @@ #define CHIP_ID_REG 0x20 /* Super I/O ID (SID) / family */ #define CHIP_REV_REG 0x27 /* Super I/O revision ID (SRID) */ -/* SID[7..0]: chip family. SRID[7..5]: chip ID, SRID[4..0]: chip rev. */ const static struct superio_registers reg_table[] = { + {0xd0, "PC87371", { /* From sensors-detect */ + {EOT}}}, + {0xdf, "PC97371", { /* From sensors-detect */ + {EOT}}}, + {0xe1, "PC87360", { + {EOT}}}, + {0xe2, "PC87351", { + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x27,0x2e,EOT}, + {0xe2,0x11,0xa1,0x00,MISC,NANA,RSVD,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}}, + {0x1, "Parallel port", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}}, + {0x3, "COM1", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}}, + {0x4, "System wake-up control (SWC)", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}}, + {0x5, "Mouse", + {0x30,0x70,0x71,0x74,0x75,EOT}, + {0x00,0x0c,0x02,0x04,0x04,EOT}}, + {0x6, "Keyboard", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75, + 0xf0,EOT}, + {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04, + 0x40,EOT}}, + {0x7, "GPIO", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,EOT}}, + {0x8, "Fan speed control", + {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}}, + {EOT}}}, + {0xe4, "PC87364", { + {EOT}}}, + {0xe5, "PC87365", { /* SRID[7..0] == chip revision */ + {EOT}}}, + {0xe8, "PC87363", { + {EOT}}}, + {0xe9, "PC87366", { + {EOT}}}, + + /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */ + {0xea, "PC8739x", { + {EOT}}}, + {0xec, "PC87591x", { + /* SRID[7..5]: 000=PC87591E, 001=PC87591S, 100=PC87591L */ + {EOT}}}, + {0xee, "PC8741x", { + /* SRID[7..5] is marked as "not applicable for the PC8741x". */ + {EOT}}}, + {0xf0, "PC87372", { + {EOT}}}, {0xf1, "PC8374L", { {EOT}}}, + {0xf2, "PC87427", { + /* SRID[7..5] is marked as "not applicable for the PC87427". */ + {EOT}}}, + {0xf3, "PC87373", { + {EOT}}}, {EOT} };

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[LinuxBIOS] r2835 build service
by LinuxBIOS information 07 Oct '07

07 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2835 to the LinuxBIOS source repository and caused the following changes: Change Log: Print a short message if no Super I/O chip could be detected (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2835&device=khepri&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] Superiotool dump for (Soltek mainboard with 82801 / i865 / w83627thf/thg)
by Idwer Vollering 07 Oct '07

07 Oct '07

Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627THF/THG (id=0x82, rev=0x83) at 0x2e Register dump: idx 20 21 22 23 24 25 26 28 29 2a 2b 2c 2d 2e 2f val 82 83 ff fe 42 00 00 00 00 00 00 00 00 00 ff def 82 NA ff 00 MM 00 MM 00 00 00 MM MM MM 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 00 00 00 04 3c def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 04 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 42 def 01 00 60 00 64 01 0c 80 LDN 0x07 (GPIO 1, GPIO 5, game port, MIDI port) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 val 00 02 01 03 30 09 ff ff ff ff ff ff def 00 02 01 03 30 09 ff 00 00 ff 00 00 LDN 0x08 (GPIO 2) idx 30 f0 f1 f2 f3 f4 f5 f6 f7 val 00 ff ff ff 00 ff 40 00 00 def 00 ff 00 00 00 RR 00 00 00 LDN 0x09 (GPIO 3, GPIO 4) idx 30 f0 f1 f2 f3 f4 f5 f6 val 00 ff ff ff 00 ff ff ff def 00 ff 00 00 00 ff 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f3 f4 f6 f7 f9 fe ff val 00 00 00 00 00 6f 10 00 00 00 00 8f 37 00 00 00 00 00 00 def 00 00 00 00 MM MM 00 00 00 00 00 00 00 00 00 00 00 RR RR LDN 0x0b (Hardware monitor) idx 30 60 61 70 val 01 02 90 00 def 00 00 00 00 No human-readable dump available for this Super I/O _________________________________________________________________ Probeer Live.nl Probeer Live.nl: zoekmachine van de makers van MSN!

2 2

[LinuxBIOS] r2836 - in trunk/LinuxBIOSv2/src: config southbridge/amd/cs5530
by svn＠openbios.org 07 Oct '07

07 Oct '07

Author: uwe Date: 2007-10-07 23:00:02 +0200 (Sun, 07 Oct 2007) New Revision: 2836 Modified: trunk/LinuxBIOSv2/src/config/Options.lb trunk/LinuxBIOSv2/src/southbridge/amd/cs5530/cs5530_vga.c Log: Fix some issues with spaces in the code and Doxygen style documentation. Painting the splash graphic is now ifdef'ed. Signed-off-by: Juergen Beisert <juergen127(a)kreuzholzen.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/config/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/config/Options.lb 2007-10-07 20:01:23 UTC (rev 2835) +++ trunk/LinuxBIOSv2/src/config/Options.lb 2007-10-07 21:00:02 UTC (rev 2836) @@ -1016,6 +1016,12 @@ comment "Integrated graphics with UMA has dynamic setup" end +define CONFIG_SPLASH_GRAPHIC + default 0 + export used + comment "Paint a splash screen" +end + define CONFIG_GX1_VIDEO default 0 export used Modified: trunk/LinuxBIOSv2/src/southbridge/amd/cs5530/cs5530_vga.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/amd/cs5530/cs5530_vga.c 2007-10-07 20:01:23 UTC (rev 2835) +++ trunk/LinuxBIOSv2/src/southbridge/amd/cs5530/cs5530_vga.c 2007-10-07 21:00:02 UTC (rev 2836) @@ -13,11 +13,22 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +/** + * @brief Activate the VGA feature in a Geode GX1 based system with one + * of five possible VESA modes: VGA, SVGA, XGA, 4:3 SXGA and 5:4 SXGA. + * Also it is prepared to display a splash screen. * - * Purpose: - * Activate the VGA feature in a Geode GX1 based system with one of five - * possible VESA modes: VGA, SVGA, XGA, 4:3 SXGA and 5:4 SXGA. Also it is - * prepared to display a splash screen. + * In a Geode GX1 environment the companion CS5530 is the VGA + * interface only. It contains a PLL for pixel clock generation, + * DACs to generate the analogue RGB signals, drivers for HSYNC + * and VSYNC and drivers for a digital flatpanel. + * The graphic feature itself (framebuffer, acceleration unit) + * is not part of this device. It is part of the CPU device. + * But both depend on each other, we cannot divide them into + * different drivers. So this driver is not only a CS5530 driver, + * it is also a Geode GX1 chipset graphic driver. */ #include <arch/io.h> #include <device/device.h> @@ -52,13 +63,13 @@ #define DC_TIMING_CFG 0x8308 #define DC_OUTPUT_CFG 0x830C -/* +/** * what colour depth should be used as default (in bpp) * Note: Currently no other value than 16 is supported */ #define COLOUR_DEPTH 16 -/* +/** * Support for a few basic video modes * Note: all modes only for CRT. The flatpanel feature is * not supported here (due to the lack of hardware to test) @@ -67,33 +78,34 @@ int pixel_clock; /*<< pixel clock in Hz */ unsigned long pll_value; /*<< pll register value for this clock */ - int visible_pixel; - int hsync_start; - int hsync_end; - int line_length; + int visible_pixel; /*<< visible pixels in one line */ + int hsync_start; /*<< start of hsync behind visible pixels */ + int hsync_end; /*<< end of hsync behind its start */ + int line_length; /*<< whole line length */ - int visible_lines; - int vsync_start; - int vsync_end; - int picture_length; + int visible_lines; /*<< visible lines on screen */ + int vsync_start; /*<< vsync start behind last visible line */ + int vsync_end; /*<< end of vsync behind its start */ + int picture_length; /*<< whole screen length */ int sync_pol; /*<< 0: low, 1: high, bit 0 hsync, bit 1 vsync */ }; /* - * values for .sync_pol + * values for .sync_pol in struct video_mode */ #define HSYNC_HIGH_POL 0 #define HSYNC_LOW_POL 1 #define VSYNC_HIGH_POL 0 #define VSYNC_LOW_POL 2 -/* ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync */ +/** + * 640x480 @ 72Hz hsync: 37.9kHz + * VESA standard mode for classic 4:3 monitors + * Copied from X11: + * ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync + */ static const struct video_mode mode_640x480 = { - /* - * 640x480 @ 72Hz hsync: 37.9kHz - * VESA standard mode for classic 4:3 monitors - */ .pixel_clock = 31500000, .pll_value = 0x33915801, @@ -107,15 +119,16 @@ .vsync_end = 491, .picture_length = 520, /* 13.89ms */ - .sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL + .sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL, }; -/* ModeLine "800x600" 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync */ +/** + * 800x600 @ 72Hz hsync: 48.1kHz + * VESA standard mode for classic 4:3 monitors + * Copied from X11: + * ModeLine "800x600" 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync + */ static const struct video_mode mode_800x600 = { - /* - * 800x600 @ 72Hz hsync: 48.1kHz - * VESA standard mode for classic 4:3 monitors - */ .pixel_clock = 50000000, .pll_value = 0x23088801, @@ -129,15 +142,16 @@ .vsync_end = 643, .picture_length = 666, /* 13.89ms */ - .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL + .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL, }; -/* ModeLine "1024x768" 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync */ +/** + * 1024x768 @ 70Hz (VESA) hsync: 56.5kHz + * Standard mode for classic 4:3 monitors + * Copied from X11: + * ModeLine "1024x768" 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync + */ static const struct video_mode mode_1024x768 = { - /* - * 1024x768 @ 70Hz (VESA) hsync: 56.5kHz - * Standard mode for classic 4:3 monitors - */ .pixel_clock = 75000000, .pll_value = 0x37E22801, @@ -151,15 +165,16 @@ .vsync_end = 777, .picture_length = 806, /* 14.3us */ - .sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL + .sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL, }; -/* ModeLine "1280x960" 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync */ +/** + * 1280x960 @ 60Hz (VESA) hsync: 60.0kHz + * Mode for classic 4:3 monitors + * Copied from X11: + * ModeLine "1280x960" 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync + */ static const struct video_mode mode_1280x960 = { - /* - * 1280x960 @ 60Hz (VESA) hsync: 60.0kHz - * Mode for classic 4:3 monitors - */ .pixel_clock = 108000000, .pll_value = 0x2710C805, @@ -173,15 +188,16 @@ .vsync_end = 964, .picture_length = 1000, /* 16.67ms */ - .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL + .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL, }; -/* ModeLine "1280x1024" 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync */ +/** + * 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz + * Mode for modern 5:4 flat screens + * Copied from X11: + * ModeLine "1280x1024" 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync + */ static const struct video_mode mode_1280x1024 = { - /* - * 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz - * Mode for modern 5:4 flat screens - */ .pixel_clock = 108000000, .pll_value = 0x2710C805, @@ -195,11 +211,11 @@ .vsync_end = 1028, .picture_length = 1066, - .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL + .sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL, }; -/* - * a few supported common modes +/** + * List of supported common modes */ static const struct video_mode *modes[] = { &mode_640x480, /* CONFIG_GX1_VIDEOMODE = 0 */ @@ -214,12 +230,14 @@ # error Requested video mode is unknown! #endif -/* +/** * Setup the pixel PLL in the companion chip - * base: register's base address - * pll_val: pll register value to be set + * @param[in] base register's base address + * @param[in] pll_val pll register value to be set + * + * The PLL to program here is located in the CS5530 */ -static void cs5530_set_clock_frequency(void *io_base,unsigned long pll_val) +static void cs5530_set_clock_frequency(void *io_base, unsigned long pll_val) { unsigned long reg; @@ -247,17 +265,26 @@ writel(reg, io_base+CS5530_DOT_CLK_CONFIG); } -/* +/** * Setup memory layout - * gx_base: GX register area - * mode: Data about the video mode to setup + * @param[in] gx_base GX register area + * @param[in] mode Data about the video mode to setup * - * This routine assumes unlocked DC registers. Using compressed buffer - * is not supported! (makes more sense later, but not while booting) + * Memory layout must be setup in Geode GX1's chipset. + * Note: This routine assumes unlocked DC registers. + * Note: Using compressed buffer is not supported yet! + * (makes more sense later, but not while booting) + * + * At this point a check is missed if the requested video + * mode is possible with the provided video memory. + * Check if symbol CONFIG_VIDEO_MB is at least: + * - 1 (=1MiB) for VGA and SVGA + * - 2 (=2MiB) for XGA + * - 4 (=4MiB) for SXGA */ -static void dc_setup_layout(void *gx_base,const struct video_mode *mode) +static void dc_setup_layout(void *gx_base, const struct video_mode *mode) { - unsigned long base = 0x00000000; + u32 base = 0x00000000; writel(base, gx_base + DC_FB_ST_OFFSET); @@ -270,12 +297,13 @@ writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3, gx_base + DC_BUF_SIZE); } -/* +/** * Setup the HSYNC/VSYNC, active video timing - * gx_base: GX register area - * mode: Data about the video mode to setup + * @param[in] gx_base GX register area + * @param[in] mode Data about the video mode to setup * - * This routine assumes unlocked DC registers + * Sync signal generation is done in Geode GX1's chipset. + * Note: This routine assumes unlocked DC registers * * |<------------------------- htotal ----------------------------->| * |<------------ hactive -------------->| | @@ -295,10 +323,10 @@ * |#####################################___________________________| line data * |______________________________________________---------_________| YSYNC */ -static void dc_setup_timing(void *gx_base,const struct video_mode *mode) +static void dc_setup_timing(void *gx_base, const struct video_mode *mode) { - unsigned long hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; - unsigned long vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; + u32 hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; + u32 vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; hactive = mode->visible_pixel & 0x7FF; hblankstart = hactive; @@ -331,10 +359,13 @@ writel((vsyncstart - 2) | ((vsyncend - 2) << 16), gx_base + DC_FP_V_TIMING); } -/* +/** * Setup required internals to bring the mode up and running - * gx_base: GX register area - * mode: Data about the video mode to setup + * @param[in] gx_base GX register area + * @param[in] mode Data about the video mode to setup + * + * Must be setup in Geode GX1's chipset. + * Note: This routine assumes unlocked DC registers. */ static void cs5530_activate_mode(void *gx_base, const struct video_mode *mode) { @@ -348,21 +379,24 @@ writel(0x00003004, gx_base + DC_OUTPUT_CFG); } -/* +/** * Activate the current mode to be "visible" outside - * gx_base: GX register area - * mode: Data about the video mode to setup + * @param[in] gx_base GX register area + * @param[in] mode Data about the video mode to setup + * + * As we now activate the interface this must be done + * in the CS5530 */ static void cs5530_activate_video(void *io_base, const struct video_mode *mode) { u32 val; - val = mode->sync_pol; - val <<= 8; - + val = (u32)mode->sync_pol << 8; writel(val | 0x0020002F, io_base + CS5530_DISPLAY_CONFIG); } +#if CONFIG_SPLASH_GRAPHIC == 1 + /* * This bitmap file must provide: * int width: pixel count in one line @@ -382,7 +416,7 @@ * * This routine assumes we are using a 16 bit colour depth! */ -static void show_boot_splash_16(u32 swidth,u32 sheight,u32 pitch,void *base) +static void show_boot_splash_16(u32 swidth, u32 sheight, u32 pitch,void *base) { int word_count,i; unsigned short *adr; @@ -391,51 +425,52 @@ * fill the screen with the colour of the * left top pixel in the graphic */ - word_count = pitch*sheight; - printk_debug("Clear Screen at %p, %d words\n",base,word_count); - adr = (unsigned short *) base; - for (i=0; i < word_count; i++, adr++) + word_count = pitch * sheight; + adr = (unsigned short*)base; + for (i = 0; i < word_count; i++, adr++) *adr = colour_map[bitmap[0]]; - printk_debug("Ready\n"); /* * paint the splash */ - xstart=swidth-width; - ystart=sheight-height; - printk_debug("Start at %u,%u\n",xstart,ystart); - for (y=0;y<height;y++) { - adr=(unsigned short*)(base + pitch*(y+ystart)+2*xstart); - for (x=0;x<width;x++) { - *adr=(unsigned short)colour_map[(int)bitmap[x+y*width]]; + xstart = swidth-width; + ystart = sheight-height; + for (y = 0; y < height; y++) { + adr=(unsigned short*)(base + pitch*(y+ystart) + 2 * xstart); + for (x = 0; x < width; x++) { + *adr=(unsigned short)colour_map[(int)bitmap[x + y * width]]; adr++; } } } +#else +# define show_boot_splash_16(w, x, y , z) +#endif -/* - * management part +/** + * LinuxBIOS management part + * @param[in] dev Info about the PCI device to initialise */ static void cs5530_vga_init(device_t dev) { const struct video_mode *mode; void *io_base, *gx_base; - io_base = (void*)pci_read_config32(dev,0x10); + io_base = (void*)pci_read_config32(dev, 0x10); gx_base = (void*)GX_BASE; mode = modes[CONFIG_GX1_VIDEOMODE]; printk_debug("Setting up video mode %dx%d with %d Hz clock\n", mode->visible_pixel, mode->visible_lines, mode->pixel_clock); - cs5530_set_clock_frequency(io_base,mode->pll_value); + cs5530_set_clock_frequency(io_base, mode->pll_value); writel(DC_UNLOCK_MAGIC, gx_base + DC_UNLOCK); show_boot_splash_16(mode->visible_pixel, mode->visible_lines, - mode->visible_pixel*(COLOUR_DEPTH>>3),(void*)(GX_BASE+0x800000)); + mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000)); - cs5530_activate_mode(gx_base,mode); + cs5530_activate_mode(gx_base, mode); cs5530_activate_video(io_base, mode); writel(0x00000000, gx_base + DC_UNLOCK); @@ -446,13 +481,13 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = cs5530_vga_init, - .enable = NULL /* not required */ + .enable = NULL, /* not required */ }; static struct pci_driver vga_pci_driver __pci_driver = { .ops = &vga_ops, .vendor = PCI_VENDOR_ID_CYRIX, - .device = PCI_DEVICE_ID_CYRIX_5530_VIDEO + .device = PCI_DEVICE_ID_CYRIX_5530_VIDEO, }; #endif /* #if CONFIG_GX1_VIDEO == 1 */

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[LinuxBIOS] superiotool - dump support for FDC37M81x
by Robinson Tryon 07 Oct '07

07 Oct '07

Signed-off-by: Robinson P. Tryon <bishop.robinson(a)gmail.com>

3 3

[LinuxBIOS] r2834 build service
by LinuxBIOS information 07 Oct '07

07 Oct '07

Dear LinuxBIOS readers! This is the automated build check service of LinuxBIOS. The developer "uwe" checked in revision 2834 to the LinuxBIOS source repository and caused the following changes: Change Log: Add a list of contributors to the README (trivial). Also, a small hint about where to send additional register dumps. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of arima:hdama is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=hdama&vendor=… Compilation of ibm:e325 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=e325&vendor=i… Compilation of ibm:e326 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=e326&vendor=i… Compilation of iei:juki-511p is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=juki-511p&ven… Compilation of iwill:dk8s2 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=dk8s2&vendor=… Compilation of iwill:dk8x is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=dk8x&vendor=i… Compilation of newisys:khepri is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=2834&device=khepri&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, LinuxBIOS automatic build system

1 0

[LinuxBIOS] Flashrom: support for At29C010A added.
by Peter Lemenkov 07 Oct '07

07 Oct '07

Hello All! Very simple patch - easy to review. Unfortunately I still not tested it on real hardware (due to lack of AT-power supply). -- With best regards!

3 4

[LinuxBIOS] Superiotool dump for Epox 8RDA3+
by Gavin Kinsey 07 Oct '07

07 Oct '07

Just noticed that superiotool now supports my board, don't know whether someone has already posted a dump for this chip but another can't hurt if they have so... Mainboard: Epox 8RDA3+ nVidia nForce 2 chipset $ sudo ./superiotool -d Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x17) at 0x2e Register dump: idx 02 07 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f val ff 0b 52 17 ff fe 80 00 00 00 00 7c c0 ff 00 ff def 00 NA 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 01 03 78 07 04 3c def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 00 80 def 01 00 60 00 64 01 0c 80 LDN 0x06 (Consumer IR) idx 30 60 61 70 val 00 00 00 00 def 00 00 00 00 LDN 0x07 (Game port, MIDI port, GPIO 1) idx 30 60 61 62 63 70 f0 f1 f2 val 07 02 01 03 30 0a ff 00 00 def 00 02 01 03 30 09 ff 00 00 LDN 0x08 (GPIO 2, Watchdog timer) idx 30 f0 f1 f2 f3 f5 f6 f6 f7 val 01 ff 07 01 00 00 00 00 00 def 00 ff 00 00 00 00 00 00 00 LDN 0x09 (GPIO 3) idx 30 f0 f1 f2 f3 val 01 ff 00 00 40 def 00 ff 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f3 f4 f6 f7 f9 fe ff val 00 00 40 03 14 00 00 00 00 00 00 af 37 04 00 00 00 00 00 def 00 00 00 00 NA NA 00 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 val 01 02 90 00 00 def 00 00 00 00 00

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coreboot October 2007