coreboot October 2007

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[LinuxBIOS] r2844 - trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100
by svn＠openbios.org 10 Oct '07

10 Oct '07

Author: uwe Date: 2007-10-10 01:58:35 +0200 (Wed, 10 Oct 2007) New Revision: 2844 Modified: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c Log: Minor cosmetic changes (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c 2007-10-09 23:26:19 UTC (rev 2843) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c 2007-10-09 23:58:35 UTC (rev 2844) @@ -40,6 +40,11 @@ #include <arch/pirq_routing.h> +#define INT_A 0x01 +#define INT_B 0x02 +#define INT_C 0x03 +#define INT_D 0x04 + /* * The USB controller should be connected to IRQ11, * the network controller should be connected to IRQ15. @@ -49,7 +54,7 @@ #define IRQ_BITMAP_LINK2 0x8000 #define IRQ_BITMAP_LINK3 0x0200 -/** Reserved interrupt channels for PCI. */ +/** Reserved interrupt channels for exclusive PCI usage. */ #define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK2) /** @@ -57,16 +62,16 @@ * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx */ const struct irq_routing_table intel_irq_routing_table = { - .signature = PIRQ_SIGNATURE, /* u32 signature */ - .version = PIRQ_VERSION, /* u16 version */ - .size = 32+16*IRQ_SLOT_COUNT, /* There can be total IRQ_SLOT_COUNT devices on the bus */ - .rtr_bus = 0x00, /* Where the interrupt router lies (bus) */ - .rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ - .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted exclusively to PCI usage */ + .signature = PIRQ_SIGNATURE, /* PIRQ signature */ + .version = PIRQ_VERSION, /* PIRQ version */ + .size = 32 +16 * IRQ_SLOT_COUNT,/* Max. IRQ_SLOT_COUNT devices */ + .rtr_bus = 0x00, /* Interrupt router bus */ + .rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */ + .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */ .rtr_vendor = 0x1078, /* Vendor */ .rtr_device = 0x0100, /* Device */ .miniport_data = 0, /* Crap (miniport) */ - .checksum = 0xBF+16, + .checksum = 0xbf + 16, /* Checksum */ .slots = { /* * Definition for "slot#1". There is no real slot, @@ -76,22 +81,11 @@ .bus = 0x00, .devfn = (0x13 << 3) | 0x0, .irq = { - [0] = { - .link = 0x01, /* INT A */ - .bitmap = IRQ_BITMAP_LINK0, - }, - [1] = { - .link = 0x02, /* INT B */ - .bitmap = IRQ_BITMAP_LINK1, - }, - [2] = { - .link = 0x03, /* INT C */ - .bitmap = IRQ_BITMAP_LINK2, - }, - [3] = { - .link = 0x04, /* INT D */ - .bitmap = IRQ_BITMAP_LINK3, - } + /* Link Bitmap */ + [0] = { INT_A, IRQ_BITMAP_LINK0 }, + [1] = { INT_B, IRQ_BITMAP_LINK1 }, + [2] = { INT_C, IRQ_BITMAP_LINK2 }, + [3] = { INT_D, IRQ_BITMAP_LINK3 }, }, .slot = 0x0, }, @@ -104,22 +98,11 @@ .bus = 0x00, .devfn = (0x0f << 3) | 0x0, .irq = { - [0] = { - .link = 0x03, - .bitmap = IRQ_BITMAP_LINK2, - }, - [1] = { - .link = 0x04, - .bitmap = IRQ_BITMAP_LINK3, - }, - [2] = { - .link = 0x01, - .bitmap = IRQ_BITMAP_LINK0, - }, - [3] = { - .link = 0x02, - .bitmap = IRQ_BITMAP_LINK1, - } + /* Link Bitmap */ + [0] = { INT_C, IRQ_BITMAP_LINK2 }, + [1] = { INT_D, IRQ_BITMAP_LINK3 }, + [2] = { INT_A, IRQ_BITMAP_LINK0 }, + [3] = { INT_B, IRQ_BITMAP_LINK1 }, }, .slot = 0x0, }

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[LinuxBIOS] r2843 - in trunk/LinuxBIOSv2: src/mainboard src/mainboard/bcom src/mainboard/bcom/winnet100 targets targets/bcom targets/bcom/winnet100
by svn＠openbios.org 10 Oct '07

10 Oct '07

Author: uwe Date: 2007-10-10 01:26:19 +0200 (Wed, 10 Oct 2007) New Revision: 2843 Added: trunk/LinuxBIOSv2/src/mainboard/bcom/ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Config.lb trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Options.lb trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/auto.c trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/chip.h trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/mainboard.c trunk/LinuxBIOSv2/targets/bcom/ trunk/LinuxBIOSv2/targets/bcom/winnet100/ trunk/LinuxBIOSv2/targets/bcom/winnet100/Config.lb Log: Add support for the BCOM WinNET100 (used in the IGEL-316 thin client). See http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial for hardware description and build tutorials. Signed-off-by: Juergen Beisert <juergen(a)kreuzholzen.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Config.lb 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,133 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if USE_FALLBACK_IMAGE + default ROM_SECTION_SIZE = FALLBACK_SIZE + default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE) +else + default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE) + default ROM_SECTION_OFFSET = 0 +end +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) +default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE) +default XIP_ROM_SIZE = 64 * 1024 +default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE) +arch i386 end +driver mainboard.o +if HAVE_PIRQ_TABLE + object irq_tables.o +end +makerule ./failover.E + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./failover.inc + depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc" + action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" +end +makerule ./auto.E + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +makerule ./auto.inc + # depends "$(MAINBOARD)/auto.c option_table.h ./romcc" + depends "$(MAINBOARD)/auto.c ./romcc" + action "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" +end +mainboardinit cpu/x86/16bit/entry16.inc +mainboardinit cpu/x86/32bit/entry32.inc +ldscript /cpu/x86/16bit/entry16.lds +ldscript /cpu/x86/32bit/entry32.lds +if USE_FALLBACK_IMAGE + mainboardinit cpu/x86/16bit/reset16.inc + ldscript /cpu/x86/16bit/reset16.lds +else + mainboardinit cpu/x86/32bit/reset32.inc + ldscript /cpu/x86/32bit/reset32.lds +end +mainboardinit arch/i386/lib/cpu_reset.inc +mainboardinit arch/i386/lib/id.inc +ldscript /arch/i386/lib/id.lds +if USE_FALLBACK_IMAGE + ldscript /arch/i386/lib/failover.lds + mainboardinit ./failover.inc +end +mainboardinit cpu/x86/fpu/enable_fpu.inc +mainboardinit cpu/amd/model_gx1/cpu_setup.inc +mainboardinit cpu/amd/model_gx1/gx_setup.inc +mainboardinit ./auto.inc + +dir /pc80 +config chip.h + +chip northbridge/amd/gx1 + device pci_domain 0 on + device pci 0.0 on end + chip southbridge/amd/cs5530 + device pci 12.0 on + chip superio/nsc/pc97317 + device pnp 2e.0 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.1 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.2 on # RTC + io 0x60 = 0x70 + irq 0x70 = 8 + end + device pnp 2e.3 off # Floppy + end + device pnp 2e.4 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.5 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xe0 + end + device pnp 2e.8 on # Power management + io 0x60 = 0xe800 + end + register "com1" = "{115200}" + register "com2" = "{38400}" + end + device pci 12.1 off end # SMI + device pci 12.2 off end # IDE + device pci 12.3 on end # Audio + device pci 12.4 on end # VGA + # device pci 13.0 on end # USB + end + end + end + chip cpu/amd/model_gx1 + end +end Added: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Options.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Options.lb (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/Options.lb 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,102 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +uses HAVE_MP_TABLE +uses HAVE_PIRQ_TABLE +uses USE_FALLBACK_IMAGE +uses HAVE_FALLBACK_BOOT +uses HAVE_HARD_RESET +uses HAVE_OPTION_TABLE +uses USE_OPTION_TABLE +uses CONFIG_ROM_PAYLOAD +uses IRQ_SLOT_COUNT +uses MAINBOARD +uses MAINBOARD_VENDOR +uses MAINBOARD_PART_NUMBER +uses LINUXBIOS_EXTRA_VERSION +uses ARCH +uses FALLBACK_SIZE +uses STACK_SIZE +uses HEAP_SIZE +uses ROM_SIZE +uses ROM_SECTION_SIZE +uses ROM_IMAGE_SIZE +uses ROM_SECTION_SIZE +uses ROM_SECTION_OFFSET +uses CONFIG_ROM_PAYLOAD_START +uses PAYLOAD_SIZE +uses _ROMBASE +uses _RAMBASE +uses XIP_ROM_SIZE +uses XIP_ROM_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY +uses DEFAULT_CONSOLE_LOGLEVEL +uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_UDELAY_TSC +uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 +uses CONFIG_VIDEO_MB +uses CONFIG_SPLASH_GRAPHIC +uses CONFIG_GX1_VIDEO +uses CONFIG_GX1_VIDEOMODE + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +default CONFIG_GX1_VIDEO = 1 +default CONFIG_GX1_VIDEOMODE = 0 +default CONFIG_SPLASH_GRAPHIC = 1 +default CONFIG_VIDEO_MB = 2 + +default ROM_SIZE = 256 * 1024 +default MAINBOARD_VENDOR = "BCOM" +default MAINBOARD_PART_NUMBER = "WinNET100" +default HAVE_FALLBACK_BOOT = 1 +default HAVE_MP_TABLE = 0 +default HAVE_HARD_RESET = 0 +default CONFIG_UDELAY_TSC = 1 +default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 +default HAVE_PIRQ_TABLE = 1 +default IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots +default HAVE_OPTION_TABLE = 0 +default ROM_IMAGE_SIZE = 64 * 1024 +default FALLBACK_SIZE = 128 * 1024 +default STACK_SIZE = 8 * 1024 +default HEAP_SIZE = 16 * 1024 +default USE_OPTION_TABLE = 0 +default _RAMBASE = 0x00004000 +default CONFIG_ROM_PAYLOAD = 1 +default CROSS_COMPILE = "" +default CC = "$(CROSS_COMPILE)gcc " +default HOSTCC = "gcc" +default CONFIG_CONSOLE_SERIAL8250 = 1 +default TTYS0_BAUD = 115200 +default TTYS0_BASE = 0x3f8 +default TTYS0_LCS = 0x3 # 8n1 +default DEFAULT_CONSOLE_LOGLEVEL = 6 +default MAXIMUM_CONSOLE_LOGLEVEL = 6 + +end Added: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/auto.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/auto.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/auto.c 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,53 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/amd/gx1/raminit.c" +#include "superio/nsc/pc97317/pc97317_early_serial.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Initialize RAM. */ + sdram_init(); + + /* Check whether RAM works. */ + /* ram_check(0, 640 * 1024); */ +} Added: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/chip.h 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,25 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_bcom_winnet100_ops; + +struct mainboard_bcom_winnet100_config { + int nothing; +}; Added: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/irq_tables.c 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,138 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * Interrupt routing description for BCOM's Winnet100 board. + * It was not possible to read back the pirq-Table. In the 0xF segment was + * no string like $PIRQ... + * But the already running 2.4.21 kernel provides eth0 IRQ15 and USB IRQ 11. + * The Realtek was device 0.f.0, the USB 0.13.0. + * + * This is the physical routing on this board: + * + * 5530 USB Network + * northbridge device device + * 00.13.0 00.0f.00 + * ------------------------------------ + * INTA# INTA# n.c. + * INTB# n.c. n.c. + * INTC# n.c. INTA# + * INTD# n.c. n.c. + */ + +#include <arch/pirq_routing.h> + +/* + * The USB controller should be connected to IRQ11, + * the network controller should be connected to IRQ15. + */ +#define IRQ_BITMAP_LINK0 0x0800 +#define IRQ_BITMAP_LINK1 0x0400 +#define IRQ_BITMAP_LINK2 0x8000 +#define IRQ_BITMAP_LINK3 0x0200 + +/** Reserved interrupt channels for PCI. */ +#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK2) + +/** + * Routing description. + * Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx + */ +const struct irq_routing_table intel_irq_routing_table = { + .signature = PIRQ_SIGNATURE, /* u32 signature */ + .version = PIRQ_VERSION, /* u16 version */ + .size = 32+16*IRQ_SLOT_COUNT, /* There can be total IRQ_SLOT_COUNT devices on the bus */ + .rtr_bus = 0x00, /* Where the interrupt router lies (bus) */ + .rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */ + .exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted exclusively to PCI usage */ + .rtr_vendor = 0x1078, /* Vendor */ + .rtr_device = 0x0100, /* Device */ + .miniport_data = 0, /* Crap (miniport) */ + .checksum = 0xBF+16, + .slots = { + /* + * Definition for "slot#1". There is no real slot, + * the USB device is embedded... + */ + [0] = { + .bus = 0x00, + .devfn = (0x13 << 3) | 0x0, + .irq = { + [0] = { + .link = 0x01, /* INT A */ + .bitmap = IRQ_BITMAP_LINK0, + }, + [1] = { + .link = 0x02, /* INT B */ + .bitmap = IRQ_BITMAP_LINK1, + }, + [2] = { + .link = 0x03, /* INT C */ + .bitmap = IRQ_BITMAP_LINK2, + }, + [3] = { + .link = 0x04, /* INT D */ + .bitmap = IRQ_BITMAP_LINK3, + } + }, + .slot = 0x0, + }, + + /* + * Definition for "slot#3". There is no real slot, + * the network device is soldered... + */ + [1] = { + .bus = 0x00, + .devfn = (0x0f << 3) | 0x0, + .irq = { + [0] = { + .link = 0x03, + .bitmap = IRQ_BITMAP_LINK2, + }, + [1] = { + .link = 0x04, + .bitmap = IRQ_BITMAP_LINK3, + }, + [2] = { + .link = 0x01, + .bitmap = IRQ_BITMAP_LINK0, + }, + [3] = { + .link = 0x02, + .bitmap = IRQ_BITMAP_LINK1, + } + }, + .slot = 0x0, + } + } +}; + +/** + * Copy the IRQ routing table to memory. + * + * @param[in] addr Destination address (between 0xF0000...0x100000). + * @return TODO. + */ +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/mainboard.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/mainboard.c (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/bcom/winnet100/mainboard.c 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,26 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_bcom_winnet100_ops = { + CHIP_NAME("BCOM WinNET100 Mainboard") +}; Added: trunk/LinuxBIOSv2/targets/bcom/winnet100/Config.lb =================================================================== --- trunk/LinuxBIOSv2/targets/bcom/winnet100/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/bcom/winnet100/Config.lb 2007-10-09 23:26:19 UTC (rev 2843) @@ -0,0 +1,53 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2007 Juergen Beisert <juergen(a)kreuzholzen.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +## See also: http://www.linuxbios.org/BCOM_WINNET100_Build_Tutorial + +target winnet100 +mainboard bcom/winnet100 + +option ROM_SIZE = 256 * 1024 + +## Enable VGA with a splash screen (only 640x480 to run on most monitors). +## We want to support up to 1024x768@16 so we need 2MiB video memory. +## Note: Higher resolutions might need faster SDRAM speed. +option CONFIG_GX1_VIDEO = 1 +option CONFIG_GX1_VIDEOMODE = 0 +option CONFIG_SPLASH_GRAPHIC = 1 +option CONFIG_VIDEO_MB = 2 + +option DEFAULT_CONSOLE_LOGLEVEL = 6 +option MAXIMUM_CONSOLE_LOGLEVEL = 6 + +romimage "normal" + option USE_FALLBACK_IMAGE = 0 + option ROM_IMAGE_SIZE = 64 * 1024 + option LINUXBIOS_EXTRA_VERSION = ".0Normal" + payload ../../../../../../../images/etherboot.elf +end + +romimage "fallback" + option USE_FALLBACK_IMAGE = 1 + option ROM_IMAGE_SIZE = 64 * 1024 + option LINUXBIOS_EXTRA_VERSION = ".0Fallback" + payload ../../../../../../../images/etherboot.elf +end + +buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

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[LinuxBIOS] General question about reset vectors
by Gabe Black 10 Oct '07

10 Oct '07

Hi. I'm extending the m5 simulator (www.m5sim.org) to support x86_64 and am trying to figure out exactly how the boot process should work. According to both the AMD and Intel manuals, the cpu resets with the CS base at 0xFFFF0000, the CS selector at 0xF000, and the IP at 0xFFF0 which means that the first instruction is fetched from physical memory address 0xFFFFFFF0. In all the other references I've found, however, the BIOS reset vector is described as being at 0xFFFF0. I used a hexeditor on a few BIOS images, and it seems that the first instruction at that reset vector is doing a far jump to CS selector 0xF000. This would keep the CS selector the same, but it would cause the CS base to be overwritten and instruction fetching to occur in the lower regions of memory. I'm assuming that the BIOS ROM is mapped into memory at both the top and bottom of the 32 bit address space, but there are very little information of this upper mapping. Could someone please explain to me how this is supposed to work? I need to know in enough detail to be able to implement it myself, but I also don't want to be too specific and limit the systems that I can simulate. Gabe Black

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[LinuxBIOS] [ANNOUNCE] superiotool -- Detect Super I/Os, dump register contents
by Uwe Hermann 09 Oct '07

09 Oct '07

Hi everyone, I'd like to announce a tool called 'superiotool' which was developed by a bunch of LinuxBIOS developers over at linuxbios.org: http://linuxbios.org/Superiotool Superiotool is a user-space utility which can - detect which Super I/O chip is soldered onto your mainboard, - at which configuration port it's located (usually 0x2e or 0x4e), and - dump all register contents of the Super I/O chip, together with the default values as per datasheet (to make comparing the values easy). Installation: $ svn co svn://linuxbios.org/repos/trunk/util/superiotool $ cd superiotool $ make $ sudo make install It's written in C and licensed under the GPL (version 2 or later). We're using it for LinuxBIOS development purposes (e.g. you need to properly init the Super I/O for early serial output support), but I guess this might be a useful tool for lm-sensors purposes, too. Yes, we're aware of sensors-detect and we considered merging our code into sensors-detect for a while, but decided to keep them two different tools for now. Some reasons (or differenceѕ between the tools): - superiotool is written in C, which allows (some) code copying into LinuxBIOS (which is also written in C). - superiotool _only_ supports and cares about Super I/Os, not other sensors, I2C, etc. etc. We don't intend to support anything other than Super I/Os in superiotool (hence the name :-) We don't need sensors et al in LinuxBIOS, that's mostly handled by the OS/userspace, e.g. lm-sensors. - The main difference to the sensors-detect Super I/O support is in the register dump feature, I guess. You can use 'superiotool -d' to get output like this: $ superiotool -d Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 88 63 ff 00 44 00 00 ff 50 04 00 00 9a 21 00 ff def 88 MM ff 00 MM 00 MM RR 50 04 00 RR 00 21 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 03 78 00 04 3c def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 00 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 00 02 f8 03 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 83 def 01 00 60 00 64 01 0c 83 LDN 0x06 (Serial flash interface) idx 30 62 63 val 00 ff ff def 00 00 00 LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f7 val 00 02 01 03 30 00 ff ff ff ff ff ff ff 00 def 00 02 01 03 30 09 ff 00 00 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED) idx 30 f5 f6 f7 val 00 ff 00 ff def 00 00 00 00 LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED) idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7 val 0f ff 21 00 ff 08 00 ff 0c 00 09 9f ff 00 00 def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 f2 f3 f4 f6 f7 val 01 00 00 00 ff 00 40 02 0c 10 09 7d 00 00 00 00 def 00 00 01 00 ff 08 00 RR 00 00 RR 7c 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 val 01 02 90 00 c1 3f def 00 00 00 00 c1 00 All numbers are in hex. idx is the register number, val is the current content of the register, def is the default value as per datasheet. I assume the dump feature might help with lm-sensors development, as you can easily dump the hardware monitor register contents (or have users send dumps) and compare values from different boards/chips etc. We currently detect a number of chips which are not detected by sensors-detect (and vice versa), I'll provide patches to sensors-detect to keep the number of detected Super I/Os in sync between the tools. This is open-source of course, so feel free to poke in the code and reuse whatever parts of it you need or want. Contributions to supertiotool are welcome, too, of course :) We also try to collect a number of example register dumps for various chips in the LinuxBIOS wiki for reference (any contributions are welcome here, too; just run 'superiotool -dV' and send the output to the LinuxBIOS mailing list, see http://linuxbios.org/Mailinglist). The list of currently supported chips, as well as links to sample dumps, is available here: http://linuxbios.org/Superiotool. HTH, Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http://www.unmaintained-free-software.org

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[LinuxBIOS] Phoenix Bios on Acer Aspire 5680
by diego 09 Oct '07

09 Oct '07

Hi, I run flashprom on my Linux Box (Fedora 7) and I have received this message Calibrating delay loop... ok No LinuxBIOS table found. Found chipset "ICH7M": Enabling flash write... OK. No EEPROM/flash device found. I send you the output of dmidecode and biosdecode commands for mi laptop Acer Aspire 5680. # dmidecode 2.7 SMBIOS 2.33 present. 25 structures occupying 808 bytes. Table at 0x000E3810. Handle 0x0000, DMI type 0, 24 bytes. BIOS Information Vendor: Acer Version: V3.23 Release Date: 12/09/2006 Address: 0xE6900 Runtime Size: 104192 bytes ROM Size: 1024 kB Characteristics: PCI is supported PC Card (PCMCIA) is supported PNP is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported AGP is supported Smart battery is supported BIOS boot specification is supported Targeted content distribution is supported BIOS Revision: 0.0 Firmware Revision: 0.0 Handle 0x0001, DMI type 1, 27 bytes. System Information Manufacturer: Acer Product Name: Aspire 5680 Version: V3.23 Serial Number: LXAFQ0J019641026CD1601 UUID: B083623A-8407-ECFB-45A6-0016D451DFBD Wake-up Type: Power Switch SKU Number: Not Specified Family: Not Specified Handle 0x0002, DMI type 2, 8 bytes. Base Board Information Manufacturer: Acer Product Name: Grapevine Version: N/A Serial Number: LXAFQ0J019641026CD1601 Handle 0x0003, DMI type 3, 17 bytes. Chassis Information Manufacturer: Acer Type: Notebook Lock: Not Present Version: N/A Serial Number: None Asset Tag: Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00001234 Handle 0x0004, DMI type 4, 35 bytes. Processor Information Socket Designation: U1 Type: Central Processor Family: Other Manufacturer: Intel ID: F6 06 00 00 FF FB EB BF Version: Intel(R) Core(TM)2 CPU T5 Voltage: 3.3 V External Clock: 166 MHz Max Speed: 1830 MHz Current Speed: 1830 MHz Status: Populated, Enabled Upgrade: ZIF Socket L1 Cache Handle: Not Provided L2 Cache Handle: 0x0005 L3 Cache Handle: Not Provided Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Handle 0x0005, DMI type 7, 19 bytes. Cache Information Socket Designation: L2 Cache Configuration: Enabled, Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 2048 KB Maximum Size: 2048 KB Supported SRAM Types: Burst Pipeline Burst Installed SRAM Type: Burst Speed: Unknown Error Correction Type: Unknown System Type: Unknown Associativity: Unknown Handle 0x0006, DMI type 9, 13 bytes. System Slot Information Designation: PCI Slot J1100 Type: 32-bit PCI Current Usage: In Use Length: Long ID: 0 Characteristics: 5.0 V is provided 3.3 V is provided PME signal is supported Handle 0x0007, DMI type 9, 13 bytes. System Slot Information Designation: PCI Slot J1101 Type: 32-bit PCI Current Usage: In Use Length: Long ID: 0 Characteristics: 5.0 V is provided 3.3 V is provided PME signal is supported Handle 0x0008, DMI type 10, 6 bytes. On Board Device Information Type: Sound Status: Disabled Description: HD-Audio Handle 0x0009, DMI type 14, 11 bytes. Group Associations Name: Cpu Module Items: 2 0x0015 (Processor) 0x0016 (Cache) Handle 0x000A, DMI type 16, 15 bytes. Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 2 GB Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x000B, DMI type 17, 27 bytes. Memory Device Array Handle: 0x000A Error Information Handle: No Error Total Width: 32 bits Data Width: 32 bits Size: 1024 MB Form Factor: SODIMM Set: 1 Locator: M1 Bank Locator: Bank 0 Type: DDR2 Type Detail: Synchronous Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Handle 0x000C, DMI type 17, 27 bytes. Memory Device Array Handle: 0x000A Error Information Handle: No Error Total Width: 32 bits Data Width: 32 bits Size: 1024 MB Form Factor: SODIMM Set: 2 Locator: M2 Bank Locator: Bank 1 Type: DDR2 Type Detail: Synchronous Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Handle 0x000D, DMI type 19, 15 bytes. Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0007FFFFFFF Range Size: 2 GB Physical Array Handle: 0x000A Partition Width: 0 Handle 0x000E, DMI type 20, 19 bytes. Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0007FFFFFFF Range Size: 2 GB Physical Device Handle: 0x000B Memory Array Mapped Address Handle: 0x000D Partition Row Position: 2 Interleave Position: 1 Interleaved Data Depth: 6 Handle 0x000F, DMI type 23, 13 bytes. System Reset Status: Enabled Watchdog Timer: Present Boot Option: Do Not Reboot Boot Option On Limit: Do Not Reboot Reset Count: Unknown Reset Limit: Unknown Timer Interval: Unknown Timeout: Unknown Handle 0x0010, DMI type 24, 5 bytes. Hardware Security Power-On Password Status: Disabled Keyboard Password Status: Unknown Administrator Password Status: Disabled Front Panel Reset Status: Unknown Handle 0x0011, DMI type 25, 9 bytes. System Power Controls Next Scheduled Power-on: 12-31 23:59:59 Handle 0x0012, DMI type 26, 20 bytes. Voltage Probe Description: Voltage Probe Location: Processor Status: OK Maximum Value: Unknown Minimum Value: Unknown Resolution: Unknown Tolerance: Unknown Accuracy: Unknown OEM-specific Information: 0x00000000 Handle 0x0013, DMI type 27, 12 bytes. Cooling Device Temperature Probe Handle: 0x0014 Type: Fan Status: OK OEM-specific Information: 0x00000000 Handle 0x0014, DMI type 28, 20 bytes. Temperature Probe Description: Temperature Probe Location: Processor Status: OK Maximum Value: Unknown Minimum Value Unknown Resolution: Unknown Tolerance: Unknown Accuracy: Unknown OEM-specific Information: 0x00000000 Handle 0x0015, DMI type 29, 20 bytes. Electrical Current Probe Description: Electrical Current Probe Location: Processor Status: OK Maximum Value: Unknown Minimum Value: Unknown Resolution: Unknown Tolerance: Unknown Accuracy: Unknown OEM-specific Information: 0x00000000 Handle 0x0016, DMI type 30, 6 bytes. Out-of-band Remote Access Manufacturer Name: Intel Inbound Connection: Enabled Outbound Connection: Disabled Handle 0x0017, DMI type 32, 20 bytes. System Boot Information Status: <OUT OF SPEC> Handle 0x0018, DMI type 127, 4 bytes. End Of Table # biosdecode 2.7 ACPI 1.0 present. OEM Identifier: ACRSYS RSD Table 32-bit Address: 0x7FE85192 SMBIOS 2.33 present. Structure Table Length: 808 bytes Structure Table Address: 0x000E3810 Number Of Structures: 25 Maximum Structure Size: 125 bytes BIOS32 Service Directory present. Revision: 0 Calling Interface Address: 0x000FD390 PNP BIOS 1.0 present. Event Notification: Not Supported Real Mode 16-bit Code Address: F000:A491 Real Mode 16-bit Data Address: 0040:0000 16-bit Protected Mode Code Address: 0x000FA4AF 16-bit Protected Mode Data Address: 0x00000400 PCI Interrupt Routing 1.0 present. Router ID: 00:1f.0 Exclusive IRQs: None Compatible Router: 8086:122e Slot Entry 1: ID 00:00, on-board Slot Entry 2: ID 00:07, on-board Slot Entry 3: ID 00:01, on-board Slot Entry 4: ID 01:00, slot number 6 Slot Entry 5: ID 00:02, on-board Slot Entry 6: ID 00:1b, on-board Slot Entry 7: ID 00:1c, on-board Slot Entry 8: ID 02:00, slot number 7 Slot Entry 9: ID 03:00, slot number 8 Slot Entry 10: ID 04:00, slot number 9 Slot Entry 11: ID 05:00, slot number 10 Slot Entry 12: ID 00:1d, on-board Slot Entry 13: ID 00:1e, on-board Slot Entry 14: ID 06:00, on-board Slot Entry 15: ID 06:01, on-board Slot Entry 16: ID 06:02, on-board Slot Entry 17: ID 06:04, on-board Slot Entry 18: ID 00:1f, on-board

1 0

[LinuxBIOS] emulator PIT setup
by Tom Sylla 09 Oct '07

09 Oct '07

Many moons ago I had a problem with an XGI VGA option ROM in the emulator: http://www.linuxbios.org/pipermail/linuxbios/2006-December/017568.html I poked at it again this week, and found that my PIT was not set up on my platform, so port 61 was not ticking, and the delay routines in the option ROM were getting stuck. It looks like the emulator attempts to set up something in the PIT: http://tracker.linuxbios.org/trac/LinuxBIOS/browser/trunk/LinuxBIOSv2/src/d… but that is timer 0, which is for the timer tick, not the refresh timer (port 61). To fix my problem, I just added LX's PIT counter 1 init I/Os: http://tracker.linuxbios.org/trac/LinuxBIOS/browser/trunk/LinuxBIOSv2/src/c… before the Counter 0 code, and the XGI ROM then loaded ok. My first question is about the current PIT code in the emulator. What is it trying to do? Is it supposed to be turning on counter 1, and just broken? Or is it really meant to be enabling the timer tick? The next question is where would be a good place for the Counter 1 init? It seems like it should be done generically in LB for any SB with a PIT.

5 6

[LinuxBIOS] The question about IDT.
by Feng, Libo 09 Oct '07

09 Oct '07

X86 architecture processor has an IDT to distribute the coming interrupts. I only found the default initialization of IDT in /src/arch/i386/lib/c_start.S. I thought that after device enumeration, the IDT also needs to be updated according to the enumeration result. Unfortunately, I can't find where the code is located. Who could give me a clue? Thank you in advance. Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

4 3

[LinuxBIOS] BIOS Savior
by Ed Swierk 09 Oct '07

09 Oct '07

I have an RD1-PMC4 (4 Mbit FWH/LPC) BIOS Savior that I no longer need. I would be happy to ship it to anyone who can find a use for it for LinuxBIOS work. --Ed

2 1

[LinuxBIOS] i845-zhu shi song-Are you out there?
by joe＠smittys.pointclark.net 09 Oct '07

09 Oct '07

Hello, Looking through the mail archive it looks like zhu shi song was able to get the i845 working with LinuxBIOS V1 back in 2004. How come the code was never commited? zhu shi song, if your out there could you send me your code so I can port it to V2 and possibly V3. This also may help me with my i82830 problem:-) Thanks - Joe

1 0

[LinuxBIOS] AMD Geode Lx/CS5536 crash after do_vsmbios.
by joeasy Chou 09 Oct '07

09 Oct '07

Hi, my platfrom: AMD Geode lx/cs5536 superio: w83627hf cat vsa.bin payload linuxbios.rom > mybios.rom The vsa.bin(36KB) download from AMD web site, payload is filo.elf. total flash rom size is 512KB, message out as fellowings, can anyone tell me what's happened! LinuxBIOS-2.0.0.0Fallback Mon Oct 8 02:50:13 PDT 2007 starting... _MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:0000180c Configuring PLL LinuxBIOS-2.0.0.0Fallback Mon Oct 8 02:50:13 PDT 2007 starting... _MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000392:07de000c Done cpuRegInit SMBUS READ ERROR:03 device:a2 Ram1.00 Ram2.00 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 SMBUS READ ERROR:03 device:a2 Ram3 DRAM controller init done. RAM DLL lock Ram4 Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-2.0.0.0Fallback Mon Oct 8 02:50:13 PDT 2007 booting... clocks_per_usec: 334 Enumerating buses... scan_static_bus for Root Device >> Entering northbridge.c: enable_dev with path 6 >> Entering northbridge.c: pci_domain_enable Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 writeglmsr: MSR 0x1000002c, val 0x20000000:0x00000003 sizeram: _MSR MC_CF07_DATA: 10076013:00003a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10076013:00003a40 sizeram: sizem 0x100MB SMMGL0Init: 268304384 bytes SMMGL0Init: offset is 0x80400000 SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 writeglmsr: MSR 0x4000002e, val 0x20000000:0x00000003 sizeram: _MSR MC_CF07_DATA: 10076013:00003a40 sizeram: sizem 0x100MB SysmemInit: enable for 256MBytes usable RAM: 268304383 bytes SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 L2 cache enabled Enabling cache GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 Exit northbridge_init_early Done cpubug fixes Not Doing ChipsetFlashSetup() Before VSA: do_vsmbios buf ilen 35441 olen60466 buf 00060000 *buf 186 buf[256k] 80 buf[0x20] signature is b0:10:e6:80 Call real_mode_switch_call_vsm into real_mode_switch_call_vsm Unexpected Exception: 13 @ 10:00016765 - Halting Code: 0 eflags: 00010006 eax: 00000020 ebx: 00000001 ecx: 10000026 edx: 10000028 edi: 0001a5e8 esi: 00000003 ebp: 00025ed4 esp: 00025ed4 Easy

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coreboot October 2007