coreboot December 2006

coreboot@coreboot.org

68 participants
183 discussions

[LinuxBIOS] #62: Wrong variable causes a compile error
by LinuxBIOS 14 Dec '06

14 Dec '06

#62: Wrong variable causes a compile error -----------------------------------------------------+---------------------- Reporter: Jon Dufresne <jon.dufresne(a)gmail.com> | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -----------------------------------------------------+---------------------- In the file mainboard/intel/i82801dbm/i82801dbm.c the variable southbridge_intel_i82801dbm_control should be named southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this device is included in Config.lb of the mainboard. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/62> LinuxBIOS <http://www.linuxbios.org/>

1 3

[LinuxBIOS] r2526 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm
by svn＠openbios.org 14 Dec '06

14 Dec '06

Author: stepan Date: 2006-12-14 15:54:00 +0100 (Thu, 14 Dec 2006) New Revision: 2526 Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm.c Log: In the file mainboard/intel/i82801dbm/i82801dbm.c the variable southbridge_intel_i82801dbm_control should be named southbridge_intel_i82801dbm_ops. Otherwise a compile error occurs if this device is included in Config.lb of the mainboard. Closes #62 Signed-off-by: Jon Dufresne <jon.dufresne(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm.c 2006-12-14 14:26:46 UTC (rev 2525) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801dbm/i82801dbm.c 2006-12-14 14:54:00 UTC (rev 2526) @@ -59,7 +59,7 @@ } } -struct chip_operations southbridge_intel_i82801dbm_control = { +struct chip_operations southbridge_intel_i82801dbm_ops = { CHIP_NAME("Intel 82801DBM Southbridge") .enable_dev = i82801dbm_enable, };

1 0

[LinuxBIOS] #59: Support for SMSC FDC37M60X Super I/O
by LinuxBIOS 14 Dec '06

14 Dec '06

#59: Support for SMSC FDC37M60X Super I/O ----------------------------------+----------------------------------------- Reporter: uwe | Owner: uwe Type: enhancement | Status: new Priority: major | Milestone: Component: code | Version: v2 Keywords: superio | Dependencies: Patchstatus: patch needs review | ----------------------------------+----------------------------------------- Add support for the SMSC FDC37M60x Super I/O (tested on FDC37M602). Serial output on serial port 1 is tested and works, the rest probably not yet. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> --- Patch is available at http://www.openbios.org/pipermail/linuxbios/2006-December/017494.html for now, as Trac currently has problems with attachments. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/59> LinuxBIOS <http://www.linuxbios.org/>

1 2

[LinuxBIOS] r2525 - in trunk/LinuxBIOSv2/src/superio/smsc: . fdc37m60x
by svn＠openbios.org 14 Dec '06

14 Dec '06

Author: uwe Date: 2006-12-14 15:26:46 +0100 (Thu, 14 Dec 2006) New Revision: 2525 Added: trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/ trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/Config.lb trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/chip.h trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x.h trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/superio.c Log: Add support for the SMSC FDC37M60x Super I/O (tested on FDC37M602). Serial output on serial port 1 is tested and works, the rest probably not yet. Closes #59. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/Config.lb (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/Config.lb 2006-12-14 14:26:46 UTC (rev 2525) @@ -0,0 +1,23 @@ +## +## This file is part of the LinuxBIOS project. +## +## Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object superio.o + Added: trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/chip.h (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/chip.h 2006-12-14 14:26:46 UTC (rev 2525) @@ -0,0 +1,36 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _SUPERIO_SMSC_FDC37M60X +#define _SUPERIO_SMSC_FDC37M60X + +#include <device/device.h> +#include <pc80/keyboard.h> +#include <uart8250.h> + +extern struct chip_operations superio_smsc_fdc37m60x_ops; + +struct superio_smsc_fdc37m60x_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; + +#endif /* _SUPERIO_SMSC_FDC37M60X */ + Added: trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x.h =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x.h (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x.h 2006-12-14 14:26:46 UTC (rev 2525) @@ -0,0 +1,39 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Datasheet: + * - Name: FDC37M60x Enhanced Super I/O Controller with Infrared Support. + * - URL: http://www.smsc.com/main/discfdc.html + * - PDF: http://www.smsc.com/main/tools/discontinued/37m602.pdf + * - Revision: 6/6/97 + */ + +/* Status: Serial port 1 is tested and works (tested on FDC37M602). */ + +/* Note: Logical devices 1, 2, 6, and 9 are reserved. */ + +#define FDC37M60X_FDC 0x00 /* Floppy */ +#define FDC37M60X_PP 0x03 /* Parallel port */ +#define FDC37M60X_SP1 0x04 /* Com1 */ +#define FDC37M60X_SP2 0x05 /* Com2 */ +#define FDC37M60X_KBCK 0x07 /* Keyboard */ +#define FDC37M60X_AUX 0x08 /* Auxiliary I/O */ + Added: trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c 2006-12-14 14:26:46 UTC (rev 2525) @@ -0,0 +1,78 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/romcc_io.h> +#include "fdc37m60x.h" + +/* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ +#define SIO_BASE 0x3f0 +#define SIO_INDEX SIO_BASE +#define SIO_DATA SIO_BASE+1 + +/* Global configuration registers. */ +#define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ +#define FDC37M60X_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define FDC37M60X_CONFIG_POWER_CONTROL 0x22 /* Power Control. */ +#define FDC37M60X_CONFIG_POWER_MGMT 0x23 /* Intelligent Power Mgmt. */ +#define FDC37M60X_CONFIG_OSC 0x24 /* OSC. */ + +#define FDC37M60X_CONFIGURATION_PORT 0x3f0 /* Write-only. */ + +/* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the + LDN the register belongs to, before you can access the register. */ +static void fdc37m60x_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +{ + outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); + outb(ldn, SIO_DATA); + outb(index, SIO_BASE); + outb(value, SIO_DATA); +} + +/* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ +static void fdc37m60x_enable_serial(device_t dev, unsigned iobase) +{ + /* (1) Enter the configuration state. */ + outb(0x55, FDC37M60X_CONFIGURATION_PORT); + + /* (2) Modify the data of configuration registers. */ + + /* Power on all devices by setting the respective bit. + Bits: 0 (FDC), 3 (PP), 4 (Com1), 5 (Com2). The rest is reserved. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_CONTROL, 0x39); + + /* Disable intelligent power management. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_POWER_MGMT, 0x00); + + /* Turn on OSC, turn on BRG clock. */ + fdc37m60x_sio_write(0x00, FDC37M60X_CONFIG_OSC, 0x04); + + /* Configure serial port 1. */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x60, 0x03); + fdc37m60x_sio_write(FDC37M60X_SP1, 0x61, 0xf8); /* I/O 0x3f8 */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x70, 0x04); /* IRQ 4 */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0xf0, 0x00); /* Normal */ + + /* Enable serial port 1. */ + fdc37m60x_sio_write(FDC37M60X_SP1, 0x30, 0x01); + + /* (3) Exit the configuration state. */ + outb(0xaa, FDC37M60X_CONFIGURATION_PORT); +} + Added: trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/superio.c =================================================================== --- trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/superio.c (rev 0) +++ trunk/LinuxBIOSv2/src/superio/smsc/fdc37m60x/superio.c 2006-12-14 14:26:46 UTC (rev 2525) @@ -0,0 +1,87 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include "chip.h" +#include "fdc37m60x.h" + +static void init(device_t dev) +{ + struct superio_smsc_fdc37m60x_config *conf; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + conf = dev->chip_info; + + switch (dev->path.u.pnp.device) { + case FDC37M60X_FDC: /* TODO. */ + break; + case FDC37M60X_PP: /* TODO. */ + break; + case FDC37M60X_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case FDC37M60X_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + case FDC37M60X_KBCK: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + init_pc_keyboard(res0->base, res1->base, &conf->keyboard); + break; + case FDC37M60X_AUX: /* TODO. */ + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_enable, + .init = init, +}; + +/* TODO: FDC, PP, AUX. */ +static struct pnp_info pnp_dev_info[] = { + { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, + sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); +} + +struct chip_operations superio_smsc_fdc37m60x_ops = { + CHIP_NAME("SMSC FDC37M60X Super I/O") + .enable_dev = enable_dev, +}; +

1 0

[LinuxBIOS] #44: ACPI collides with smbus/ide on i82801ca southbridge
by LinuxBIOS 14 Dec '06

14 Dec '06

#44: ACPI collides with smbus/ide on i82801ca southbridge ----------------------------------+----------------------------------------- Reporter: chn(a)virtutech.se | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: code | Version: v2 Keywords: | Due_close: MM/DD/YYYY Include_gantt: 0 | Dependencies: Due_assign: MM/DD/YYYY | Patchstatus: there is no patch ----------------------------------+----------------------------------------- In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o space offset 0x1000, and later is the acpi registers also mapped at 0x1000. I had to apply the attached patch to get it to work. Note: It is not tested on real h/w, just in a simulator. -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/44> LinuxBIOS <http://www.linuxbios.org/>

1 3

[LinuxBIOS] r2524 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 14 Dec '06

14 Dec '06

Author: uwe Date: 2006-12-14 01:59:41 +0100 (Thu, 14 Dec 2006) New Revision: 2524 Modified: trunk/LinuxBIOSv2/util/flashrom/Makefile Log: Add an install target to the flashrom Makefile which installs flashrom into /usr/local/bin. Closes #54. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/util/flashrom/Makefile =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/Makefile 2006-12-14 00:43:50 UTC (rev 2523) +++ trunk/LinuxBIOSv2/util/flashrom/Makefile 2006-12-14 00:59:41 UTC (rev 2524) @@ -8,6 +8,8 @@ CC = gcc STRIP = strip +INSTALL = /usr/bin/install +PREFIX = /usr/local #CFLAGS = -O2 -g -Wall -Werror CFLAGS = -Os -Wall -Werror -DDISABLE_DOC # -DTS5300 LDFLAGS = -lpci -lz -static @@ -45,6 +47,9 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test +install: $(PROGRAM) + $(INSTALL) flashrom $(PREFIX)/bin + .PHONY: all clean distclean dep pciutils -include .dependencies

1 0

[LinuxBIOS] r2523 - trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca
by svn＠openbios.org 14 Dec '06

14 Dec '06

Author: stepan Date: 2006-12-14 01:43:50 +0100 (Thu, 14 Dec 2006) New Revision: 2523 Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c Log: In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o space offset 0x1000, and later is the acpi registers also mapped at 0x1000. This patch fixes this behavior. Closes #44 Signed-off-by: <chn(a)virtutech.se> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2006-12-14 00:40:09 UTC (rev 2522) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82801ca/i82801ca_lpc.c 2006-12-14 00:43:50 UTC (rev 2523) @@ -121,8 +121,8 @@ // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); - // Set ACPI base address to 0x1000 (I/O space) - pci_write_config32(dev, PMBASE, 0x00001001); + // Set ACPI base address to 0x1100 (I/O space) + pci_write_config32(dev, PMBASE, 0x00001101); // Enable ACPI I/O and power management pci_write_config8(dev, ACPI_CNTL, 0x10);

1 0

[LinuxBIOS] r2522 - in trunk/LinuxBIOSv2/src/cpu/intel: model_69x model_6dx model_6xx
by svn＠openbios.org 14 Dec '06

14 Dec '06

Author: stepan Date: 2006-12-14 01:40:09 +0100 (Thu, 14 Dec 2006) New Revision: 2522 Modified: trunk/LinuxBIOSv2/src/cpu/intel/model_69x/model_69x_init.c trunk/LinuxBIOSv2/src/cpu/intel/model_6dx/model_6dx_init.c trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c Log: Add mtrr support for pentium m cpus For cache to work the x86_setup_mtrrs() must be called. Closes #61 Signed-off-by: Jon Dufresne <jon.dufresne(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/cpu/intel/model_69x/model_69x_init.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/intel/model_69x/model_69x_init.c 2006-12-14 00:31:38 UTC (rev 2521) +++ trunk/LinuxBIOSv2/src/cpu/intel/model_69x/model_69x_init.c 2006-12-14 00:40:09 UTC (rev 2522) @@ -24,6 +24,7 @@ { /* Turn on caching if we haven't already */ x86_enable_cache(); + x86_setup_mtrrs(36); x86_mtrr_check(); /* Update the microcode */ Modified: trunk/LinuxBIOSv2/src/cpu/intel/model_6dx/model_6dx_init.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/intel/model_6dx/model_6dx_init.c 2006-12-14 00:31:38 UTC (rev 2521) +++ trunk/LinuxBIOSv2/src/cpu/intel/model_6dx/model_6dx_init.c 2006-12-14 00:40:09 UTC (rev 2522) @@ -24,6 +24,7 @@ { /* Turn on caching if we haven't already */ x86_enable_cache(); + x86_setup_mtrrs(36); x86_mtrr_check(); /* Update the microcode */ Modified: trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c =================================================================== --- trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c 2006-12-14 00:31:38 UTC (rev 2521) +++ trunk/LinuxBIOSv2/src/cpu/intel/model_6xx/model_6xx_init.c 2006-12-14 00:40:09 UTC (rev 2522) @@ -30,6 +30,7 @@ { /* Turn on caching if we haven't already */ x86_enable_cache(); + x86_setup_mtrrs(36); x86_mtrr_check(); /* Update the microcode */

1 0

[LinuxBIOS] r2521 - trunk/LinuxBIOSv2/targets/iwill/dk8_htx
by svn＠openbios.org 14 Dec '06

14 Dec '06

Author: stepan Date: 2006-12-14 01:31:38 +0100 (Thu, 14 Dec 2006) New Revision: 2521 Modified: trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb Log: This is a typo that went into one of the abuild files. it will break abuild on this board for everyone but me. Closes #58 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> (trivial patch) Modified: trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb 2006-12-05 15:27:46 UTC (rev 2520) +++ trunk/LinuxBIOSv2/targets/iwill/dk8_htx/Config-abuild.lb 2006-12-14 00:31:38 UTC (rev 2521) @@ -13,13 +13,13 @@ option USE_FALLBACK_IMAGE=0 option ROM_IMAGE_SIZE=0x17000 option LINUXBIOS_EXTRA_VERSION=".0-normal" - payload /home/stepan/svn/LinuxBIOSv2/util/abuild/LinuxBIOS-payloads/payloads/default/filo-0.5.0.elf + payload PAYLOAD end romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=0x17000 option LINUXBIOS_EXTRA_VERSION=".0-fallback" - payload /home/stepan/svn/LinuxBIOSv2/util/abuild/LinuxBIOS-payloads/payloads/default/filo-0.5.0.elf + payload PAYLOAD end buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

1 0

Re: [LinuxBIOS] DK8-HTX: 8131 B-bus IRQ problem?
by Lu, Yinghai 14 Dec '06

14 Dec '06

-----Original Message----- From: mcqmcqmcq(a)fastmail.fm [mailto:mcqmcqmcq@fastmail.fm] Sent: Wednesday, December 13, 2006 3:54 PM > mptable.c has all this stuff about 8132s when the chip on the board > is actually an 8131 (or so says lspci in Iwill bios as well as all the > Iwill literature; I haven't pulled off the heatsink to verify). I > assume this doesn't matter? Just a symbol, the GSI for 8132 is 7, and 4 for 8131. > So what's the story on A/B naming? I thought that the A-bus was the > one that everybody runs at 133 and the B was the one that had some > problem that maxed it out at 100. The names appear to be used in the > opposite sense in the mptable.c -- can somebody correct my > misconception here? If you have two pcix device on one, you need to downgrade the speed from 133 to 100 by jump, or... YH

1 0

← Newer
1
...
5
6
7
8
9
10
11
...
19
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot December 2006