coreboot December 2006

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[LinuxBIOS] r2533 - in trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx: . dx
by svn＠openbios.org 20 Dec '06

20 Dec '06

Author: yhlu Date: 2006-12-20 21:21:05 +0100 (Wed, 20 Dec 2006) New Revision: 2533 Added: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/htx_no_ioapic.asl trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5.asl trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5_hc.asl Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c Log: htx card on io apic on htx slot of dk8_htx Signed-off-by: Yinghai Lu <yinghai.lu(a)amd.com> Acked-by: Yinghai Lu <yinghai.lu(a)amd.com> Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb 2006-12-20 20:15:33 UTC (rev 2532) +++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/Config.lb 2006-12-20 20:21:05 UTC (rev 2533) @@ -119,6 +119,13 @@ action "mv pci4.hex ssdt4.c" end object ./ssdt4.o + makerule ssdt5.c + depends "$(MAINBOARD)/dx/pci5.asl" + action "iasl -tc $(MAINBOARD)/dx/pci5.asl" + action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" + action "mv pci5.hex ssdt5.c" + end + object ./ssdt5.o end end Modified: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c 2006-12-20 20:15:33 UTC (rev 2532) +++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/acpi_tables.c 2006-12-20 20:21:05 UTC (rev 2533) @@ -44,6 +44,7 @@ extern unsigned char AmlCode_ssdt2[]; extern unsigned char AmlCode_ssdt3[]; extern unsigned char AmlCode_ssdt4[]; +extern unsigned char AmlCode_ssdt5[]; #endif #define IO_APIC_ADDR 0xfec00000UL @@ -286,7 +287,9 @@ p = AmlCode_ssdt4; break; default: - continue; + //HTX no io apic + p = AmlCode_ssdt5; + break; } current += ((acpi_header_t *)p)->length; memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length); Added: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/htx_no_ioapic.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/htx_no_ioapic.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/htx_no_ioapic.asl 2006-12-20 20:21:05 UTC (rev 2533) @@ -0,0 +1,20 @@ +/* + * Copyright 2006 AMD + */ + + Device (HTXA) + { + /* HTX */ + Method (_ADR, 0, NotSerialized) + { + Return (DADD(GHCD(HCIN, 0), 0x00000000)) + } + + Method (_PRW, 0, NotSerialized) + { + If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) } + Else { Return (Package (0x02) { 0x29, 0x01 }) } + } + + } + Added: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5.asl 2006-12-20 20:21:05 UTC (rev 2533) @@ -0,0 +1,68 @@ +/* + * Copyright 2005 AMD + */ +DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440) +{ + Scope (_SB) + { + External (DADD, MethodObj) + External (GHCE, MethodObj) + External (GHCN, MethodObj) + External (GHCL, MethodObj) + External (GHCD, MethodObj) + External (GNUS, MethodObj) + External (GIOR, MethodObj) + External (GMEM, MethodObj) + External (GWBN, MethodObj) + External (GBUS, MethodObj) + + External (PICF) + + External (\_SB.PCI0.LNKA, DeviceObj) + External (\_SB.PCI0.LNKB, DeviceObj) + External (\_SB.PCI0.LNKC, DeviceObj) + External (\_SB.PCI0.LNKD, DeviceObj) + + Device (PCIX) + { + + // BUS ? Second HT Chain + Name (HCIN, 0xcc) // HC2 0x01 + + Name (_UID, 0xdd) // HC 0x03 + + Name (_HID, "PNP0A03") + + Method (_ADR, 0, NotSerialized) //Fake bus should be 0 + { + Return (DADD(GHCN(HCIN), 0x00000000)) + } + + Method (_BBN, 0, NotSerialized) + { + Return (GBUS (GHCN(HCIN), GHCL(HCIN))) + } + + Method (_STA, 0, NotSerialized) + { + Return (\_SB.GHCE(HCIN)) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { }) + Store( GHCN(HCIN), Local4) + Store( GHCL(HCIN), Local5) + + Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) + Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) + Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) + Return (Local3) + } + + Include ("pci5_hc.asl") + } + } + +} + Added: trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5_hc.asl =================================================================== --- trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5_hc.asl (rev 0) +++ trunk/LinuxBIOSv2/src/mainboard/iwill/dk8_htx/dx/pci5_hc.asl 2006-12-20 20:21:05 UTC (rev 2533) @@ -0,0 +1 @@ + Include ("htx_no_ioapic.asl")

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[LinuxBIOS] r2532 - trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804
by svn＠openbios.org 20 Dec '06

20 Dec '06

Author: yhlu Date: 2006-12-20 21:15:33 +0100 (Wed, 20 Dec 2006) New Revision: 2532 Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_pci.c Log: ck804 pref mem 4G above support Signed-off-by: Yinghai Lu <yinghai.lu(a)amd.com> Acked-by: Yinghai Lu <yinghai.lu(a)amd.com> Modified: trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_pci.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_pci.c 2006-12-20 14:59:56 UTC (rev 2531) +++ trunk/LinuxBIOSv2/src/southbridge/nvidia/ck804/ck804_pci.c 2006-12-20 20:15:33 UTC (rev 2532) @@ -14,6 +14,10 @@ { uint32_t dword; +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + device_t pci_domain_dev; + struct resource *mem1, *mem2; +#endif /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -34,8 +38,27 @@ pci_write_config32(dev, 0x4c, dword); #endif +#if CONFIG_PCI_64BIT_PREF_MEM == 1 + pci_domain_dev = dev->bus->dev; + while(pci_domain_dev) { + if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; + pci_domain_dev = pci_domain_dev->bus->dev; + } + + if(!pci_domain_dev) return; // impossiable + mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit + mem2 = find_resource(pci_domain_dev, 2); // mem + if(mem1->base > mem2->base) { + dword = mem2->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); + } else { + dword = mem1->base & (0xffff0000UL); + printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base); + } +#else dword = dev_root.resource[1].base & (0xffff0000UL); - printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); + printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base); +#endif printk_debug("[0x50] <-- 0x%08x\n", dword); pci_write_config32(dev, 0x50, dword); //TOM

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[LinuxBIOS] #67: 24c02 support
by LinuxBIOS 20 Dec '06

20 Dec '06

#67: 24c02 support ---------------------------------+------------------------------------------ Reporter: puzzles | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ add support to flashrom for the Atmel 24c02 (24cXX, maybe?) see: http://www.cgsecurity.org/cmospwd.txt -- Ticket URL: <http://tracker.linuxbios.org/trac/LinuxBIOS/ticket/67> LinuxBIOS <http://www.linuxbios.org/>

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Re: [LinuxBIOS] IBM Netvista n2800
by michaelqiu1981＠voila.fr 20 Dec '06

20 Dec '06

> Message du 20/12/06 à 13h46 > De : "Jon Dufresne" <jon.dufresne(a)gmail.com> > A : michaelqiu1981(a)voila.fr > Copie à : "Stefan Reinauer" <stepan(a)coresystems.de>, linuxbios(a)linuxbios.org > Objet : Re: [LinuxBIOS] IBM Netvista n2800 > > > What is a socketed BIOS chip? I can only identify there are two ISSI chips like BIOS, they are: > > IS61LV6464-6TQ > > IS61LV256-12J > > A socketed chip means there is a literal socket that the chip fits > into. If the chip is socketed you are able to pull the chip out of the > motherboard. The alternative is that the chip is soldered directly to > the motherboard. If it is soldered it is very difficult (but not > impossible) to remove. It's soldered unfortunately. > > -- > linuxbios mailing list > linuxbios(a)linuxbios.org > http://www.openbios.org/mailman/listinfo/linuxbios > >

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[LinuxBIOS] Is Linux seeing my ACPI table?
by Jon Dufresne 20 Dec '06

20 Dec '06

I get the impression that LinuxBIOS is writing an ACPI table because I see this during the BIOS phase ACPI: Writing ACPI tables at f0400... ACPI: * FACS ACPI: * DSDT @ 000f04a2 Length 342 ACPI: * FADT ACPI: added table 1/6 Length now 40 ACPI: done. Then when the boot is handed over the Linux I see the following: ACPI: RSDP (v000 LXBIOS ) @ 0x000f0400 ACPI: RSDT (v001 LXBIOS RSDT 0x00000000 NONE 0x00000000) @ 0x000f0424 ACPI: FADT (v001 LXBIOS LXBACPI 0x00000000 LXB 0x00000000) @ 0x000f07e4 ACPI: DSDT (v001 LXBIOS LXB-DSDT 0x00000001 INTL 0x20061109) @ 0x00000000 ACPI: Disabling ACPI support It appears to me that Linux thinks DSDT is at address 0!? Am I interpreting this right? It worries me that it then disables ACPI support. I feel this disabling of ACPI might be affecting my irq routing. Any idea what this might mean? This is my first time getting into the details of ACPI and find some of the documentation confusing. Thanks for any help Jon

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Re: [LinuxBIOS] memory channels
by rami jiossy 20 Dec '06

20 Dec '06

do we already know that configuring single channel mode in BIOS is feasible? should it be a big overahead to do or might be trivial? Thanks ----- Original Message ---- From: Jon Dufresne <jon.dufresne(a)gmail.com> To: rami jiossy <sramij(a)yahoo.com> Cc: linuxbios(a)linuxbios.org Sent: Wednesday, December 20, 2006 5:30:35 PM Subject: Re: [LinuxBIOS] memory channels Poke around src/northbridge/intel/YOUR_NORTH_BRIDGE/raminit.c This is the code that sets up your ram. Jon On 12/20/06, rami jiossy <sramij(a)yahoo.com> wrote: > > Hi; > > Does any one knows how can i control memory channels on my machine from > LinuxBIOS? can you point me to the code dealing with this, like running in > single channel VS. dual channel? > is it configurable in the BIOS? > > i am talking about any Intel chipset, i'll try porting it to what i need i > guess. > > Thanks > __________________________________________________ > Do You Yahoo!? > Tired of spam? Yahoo! Mail has the best spam protection around > http://mail.yahoo.com > -- > linuxbios mailing list > linuxbios(a)linuxbios.org > http://www.openbios.org/mailman/listinfo/linuxbios > > __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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[LinuxBIOS] memory channels
by rami jiossy 20 Dec '06

20 Dec '06

Hi; Does any one knows how can i control memory channels on my machine from LinuxBIOS? can you point me to the code dealing with this, like running in single channel VS. dual channel? is it configurable in the BIOS? i am talking about any Intel chipset, i'll try porting it to what i need i guess. Thanks __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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[LinuxBIOS] r2531 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 20 Dec '06

20 Dec '06

Author: uwe Date: 2006-12-20 15:59:56 +0100 (Wed, 20 Dec 2006) New Revision: 2531 Modified: trunk/LinuxBIOSv2/util/flashrom/flashrom.1 Log: Improve flashrom description in the manpage a bit (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/util/flashrom/flashrom.1 =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/flashrom.1 2006-12-20 14:53:22 UTC (rev 2530) +++ trunk/LinuxBIOSv2/util/flashrom/flashrom.1 2006-12-20 14:59:56 UTC (rev 2531) @@ -1,12 +1,14 @@ -.TH FLASHROM 1 "November 22, 2006" +.TH FLASHROM 1 "December 20, 2006" .SH NAME -flashrom \- the universal LinuxBIOS flash utility +flashrom \- a universal flash programming utility .SH SYNOPSIS .B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR exclude_start] [\fB\-e\fR exclude_end] [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] [file] .SH DESCRIPTION .B flashrom -is the universal LinuxBIOS flash utility. +is a universal flash programming utility for flash chips +(e.g. in DIP or PLCC packaging). It can be used to flash BIOS images, +for example. .SH OPTIONS If no file is specified, then all that happens is that flash info is dumped and the flash chip is set to writable.

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[LinuxBIOS] r2530 - trunk/LinuxBIOSv2/util/flashrom
by svn＠openbios.org 20 Dec '06

20 Dec '06

Author: uwe Date: 2006-12-20 15:53:22 +0100 (Wed, 20 Dec 2006) New Revision: 2530 Modified: trunk/LinuxBIOSv2/util/flashrom/README Log: Update flashrom requirements in the README (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/LinuxBIOSv2/util/flashrom/README =================================================================== --- trunk/LinuxBIOSv2/util/flashrom/README 2006-12-15 12:56:28 UTC (rev 2529) +++ trunk/LinuxBIOSv2/util/flashrom/README 2006-12-20 14:53:22 UTC (rev 2530) @@ -11,7 +11,8 @@ installed on your Linux system: * pciutils -* pciutils-devel +* pciutils-devel / pciutils-dev +* zlib-devel / zlib1g-dev Usage

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Re: [LinuxBIOS] IBM Netvista n2800
by michaelqiu1981＠voila.fr 20 Dec '06

20 Dec '06

> Message du 19/12/06 à 13h24 > De : "Stefan Reinauer" <stepan(a)coresystems.de> > A : michaelqiu1981(a)voila.fr > Copie à : linuxbios(a)linuxbios.org > Objet : Re: [LinuxBIOS] IBM Netvista n2800 > > * michaelqiu1981(a)voila.fr <michaelqiu1981(a)voila.fr> [061219 11:52]: > > Hi, > > > > I have an IBM Netvista n2800, which is originally used as a network > > client. There is neither floppy driver nor cd-rom in it. Right now it > > runs Debian 3.1 very well. May I use LinuxBios in this machine? > > > > He uses Interl430TX, PIIX4E, Pentunm266MMX, with a SII 64k bios flash. > > Thanks in advance! > > a) Does the machine have a socketed BIOS chip? What is a socketed BIOS chip? I can only identify there are two ISSI chips like BIOS, they are: IS61LV6464-6TQ IS61LV256-12J > b) Can you send an lspci -vvv ? 0000:00:00.0 Host bridge: Intel Corp. 430TX - 82439TX MTXC (rev 01) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- Latency: 32 0000:00:01.0 VGA compatible controller: S3 Inc. Trio 64 3D (rev 01) (prog-if 00 [VGA]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 (1000ns min, 63750ns max) Interrupt: pin A routed to IRQ 11 Region 0: Memory at f4000000 (32-bit, non-prefetchable) [size=64M] Expansion ROM at fe000000 [disabled] [size=64K] Capabilities: [44] Power Management version 1 Flags: PMEClk- DSI+ D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 0000:00:02.0 Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 08) Subsystem: Intel Corp. EtherExpress PRO/100+ Management Adapter Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (2000ns min, 14000ns max), Cache Line Size: 0x08 (32 bytes) Interrupt: pin A routed to IRQ 10 Region 0: Memory at f3eff000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at 7c40 [size=64] Region 2: Memory at f3f00000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] [size=1M] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=2 PME- 0000:00:05.0 ISA bridge: Intel Corp. 82371AB/EB/MB PIIX4 ISA (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 0000:00:05.1 IDE interface: Intel Corp. 82371AB/EB/MB PIIX4 IDE (rev 01) (prog-if 80 [Master]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Region 4: I/O ports at fff0 [size=16] 0000:00:05.2 USB Controller: Intel Corp. 82371AB/EB/MB PIIX4 USB (rev 01) (prog-if 00 [UHCI]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 32 Interrupt: pin D routed to IRQ 6 Region 4: I/O ports at ff00 [size=32] 0000:00:05.3 Bridge: Intel Corp. 82371AB/EB/MB PIIX4 ACPI (rev 02) Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin ? routed to IRQ 9 > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: info(a)coresystems.de • http://www.coresystems.de/ > >

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coreboot December 2006