coreboot September 2005

coreboot@coreboot.org

45 participants
117 discussions

RE: [LinuxBIOS] Section Overlaps & Offset miscalculation
by Lu, Yinghai 13 Sep '05

13 Sep '05

Typically you need set ROM_IMAGE_SIZE to 0x15000 so you can leave some space (24Kbytes) for fallback payload. YH ________________________________ From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of San Mehat Sent: Monday, September 12, 2005 8:22 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] Section Overlaps & Offset miscalculation Greetings, I'm currently trying to build a ck804 based amd bios and am having the following issue: /usr/bin/ld: section .reset [fffdfff0 -> fffdffff] overlaps section .rom [fffd858b -> fffe263f] When i increase 'ROM_IMAGE_SIZE' from 0x10000 to 0x20000 the problem goes away, however it looks like the offsets are being incorrectly computed (the reset vector jump goes off into la-la land). Any ideas?.. thanks -san

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RE: [LinuxBIOS] Section Overlaps & Offset miscalculation
by Stephen.Kimball＠bench.com 13 Sep '05

13 Sep '05

What motherboard are you using? The first thing to check is the ROMSTRAP table. The CK804 may not allow the board to come out of reset if the ROMSTRAP is not in the proper location. I think it's at 0xFFFFFFE0 defined in ids.inc and it points to "2BIGDOGS" or 0x2B16D065. Steve -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of San Mehat Sent: Monday, September 12, 2005 11:22 PM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] Section Overlaps & Offset miscalculation Greetings, I'm currently trying to build a ck804 based amd bios and am having the following issue: /usr/bin/ld: section .reset [fffdfff0 -> fffdffff] overlaps section .rom [fffd858b -> fffe263f] When i increase 'ROM_IMAGE_SIZE' from 0x10000 to 0x20000 the problem goes away, however it looks like the offsets are being incorrectly computed (the reset vector jump goes off into la-la land). Any ideas?.. thanks -san

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[LinuxBIOS] E7501 Raminit rewrite
by Steven J. Magnani 13 Sep '05

13 Sep '05

This one ends up being a little more than a "patch". I ended up reorganizing the E7501 raminit code so I could follow it, and fixed some bugs along the way. Significant logical changes: * Added support for "fast" (64-clock) refresh * Added code to support remap window for 3 - 4 GB systems * Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html). * Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted. * Disabled subsystem (vendor) ID configuration * #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html) * Added optional run-time checking of dual-channel compatibility of installed DIMMs * Move JEDEC SPD and SDRAM definitions into reusable #include files Probably, the rewritten code should be reviewed as if it were new. My hope is that it is now easy enough to follow that this shouldn't be too bad. The original code is, of course, in Subversion. Since I reordered the functions as part of the rewrite, a 'diff' of of the new code against the original won't tell you much. I've attached a reordered copy of the Subversion code that won't compile, but should be a little easier to diff against the new code so you can see what's changed. I will hold off on committing this for awhile to give people time to look at it. I know that radical changes are a pain to review, but IMHO the improvement in maintainability is significant. New files that are part of this 'patch', but not included here (I committed these to Subversion): src/include/spd.h src/include/sdram_mode.h src/include/northbridge/intel/e7501/e7501.h Thanks, Steve ------------------------------------------------------------------------ Steven J. Magnani "I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator!" #include <standard.disclaimer>

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[LinuxBIOS] Section Overlaps & Offset miscalculation
by San Mehat 12 Sep '05

12 Sep '05

Greetings, I'm currently trying to build a ck804 based amd bios and am having the following issue: /usr/bin/ld: section .reset [fffdfff0 -> fffdffff] overlaps section .rom [fffd858b -> fffe263f] When i increase 'ROM_IMAGE_SIZE' from 0x10000 to 0x20000 the problem goes away, however it looks like the offsets are being incorrectly computed (the reset vector jump goes off into la-la land). Any ideas?.. thanks -san

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[LinuxBIOS] Via MII BIOS help, can pay!
by pj＠cassens.com 12 Sep '05

12 Sep '05

Hello, all! Before messing with my Via MII BIOS, I google'd my heart out and did not find any real specific info. I found many other peeps in the same boat as I am; I need CF boot for this VERY cool MB! In fact, I have committed to already buying qty 130 of them and will buy another qty 130 on my way to a total nearing 900 if I'm lucky. I won't bore you with the project details, But I will say that they are vehicle mounted PC's running Linux (of course). That's all well and good, but we are spending a fair amount on IDE-CF adapters and cables (times qty) AND we have to take the PC apart to put on a new boot image. So, part of the openbios docs indicate that "targets/via/epia-mii" exists for this board. It does not. I am trying to learn as quickly as possible about what I can do with openbios. I am willing to pay for some excelerated work/help in order to help my own cause. The payment could be money to a person or group or in hardware (to make sure it all works of course). I don't know how much is fair. I do know that http://www.esupport.com/ bios guys might be able to do it. That would suck, however... 1. enigineering cost fo $1000+++, 2. not opensource, 3. still have per bios cost nearing IDE-CF adapter cost... So, anyone interested?

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[LinuxBIOS] sc520
by Ronald G Minnich 12 Sep '05

12 Sep '05

support for the digitallogic sc520 is now in the svn tree. I have built it and it works. open issues - memory size still hardcoded - e100 insmod fails - vga bios fails ron

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[LinuxBIOS] LNXI Merge: modification to lnxi-patch-06/16
by jason schildt 12 Sep '05

12 Sep '05

DESCRIPTION: ---------------------------------------------- ## lnxi-patch-6 ## src/include/smp/spinlock.h src/cpu/x86/tsc/delay_tsc.c cpu_relax() gets called unconditionally. DIFFSTAT: ----------------------------------------------- cpu/x86/tsc/delay_tsc.c | 4 ---- include/smp/spinlock.h | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) PATCH: ----------------------------------------------- Index: lnxi-merge/src/include/smp/spinlock.h =================================================================== --- lnxi-merge/src/include/smp/spinlock.h (revision 1105) +++ lnxi-merge/src/include/smp/spinlock.h (working copy) @@ -19,6 +19,7 @@ #define spin_unlock_wait(lock) do {} while(0) #define spin_lock(lock) do {} while(0) #define spin_unlock(lock) do {} while(0) +#define cpu_relax() do {} while(0) #endif #endif /* SMP_SPINLOCK_H */ Index: lnxi-merge/src/cpu/x86/tsc/delay_tsc.c =================================================================== --- lnxi-merge/src/cpu/x86/tsc/delay_tsc.c (revision 1105) +++ lnxi-merge/src/cpu/x86/tsc/delay_tsc.c (working copy) @@ -159,11 +159,7 @@ count = rdtscll(); stop = clocks + count; while(stop > count) { -#ifdef CONFIG_SMP -#if CONFIG_SMP == 1 cpu_relax(); -#endif -#endif count = rdtscll(); } } ----------------------------------------------- --jason-- -- Jason W. Schildt LinuxBIOS Software Engineer Linux Networx

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[LinuxBIOS] PATCH: P64H2 cleanup
by Steven J. Magnani 12 Sep '05

12 Sep '05

This patch does the following: * Drops hard-coding of P64H2 vendor/subsystem ID * Replaces magic numbers with standard #defined tags * Attempts to improve clarity via comments and variable names * Releases <assert.h> for general use Except for the vendor/subsystem ID, the changes don't affect the operation of the code. PATCH: --- src/southbridge/intel/i82870/p64h2_ioapic.c.orig 2005-09-08 13:34:48.078125000 -0500 +++ src/southbridge/intel/i82870/p64h2_ioapic.c 2005-09-12 13:22:28.671875000 -0500 @@ -4,72 +4,81 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <assert.h> #include "82870.h" -static int ioapic_no = 0; +static int num_p64h2_ioapics = 0; static void p64h2_ioapic_enable(device_t dev) { - uint32_t dword; - uint16_t word; - /* We have to enable MEM and Bus Master for IOAPIC */ - word = 0x0146; - pci_write_config16(dev, PCICMD, word); - dword = 0x358015d9; - pci_write_config32(dev, SUBSYS, dword); + uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config16(dev, PCI_COMMAND, command); } +//--------------------------------------------------------------------- ------------- +// Function: p64h2_ioapic_init +// Parameters: dev - PCI bus/device/function of P64H2 IOAPIC +// NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0 +// Return Value: None +// Description: Configure one of the IOAPICs in a P64H2. +// Note that a PCI bus scan will detect both IOAPICs, so this function +// will be called twice for each P64H2 in the system. +// static void p64h2_ioapic_init(device_t dev) { - uint32_t dword; - uint16_t word; - int i, addr; + uint32_t memoryBase; + int apic_index, apic_id; - volatile uint32_t *ioapic_a; /* io apic io memory space command address */ - volatile uint32_t *ioapic_d; /* io apic io memory space data address */ + volatile uint32_t* pIndexRegister; /* io apic io memory space command address */ + volatile uint32_t* pWindowRegister; /* io apic io memory space data address */ - i = ioapic_no++; + apic_index = num_p64h2_ioapics; + num_p64h2_ioapics++; - if(i<3) /* io apic address numbers are 3,4,5,&8 */ - addr=i+3; + // A note on IOAPIC addresses: + // 0 and 1 are used for the local APICs of the dual virtual + // (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb). + // 6 and 7 are used for the local APICs of the dual virtual + // (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb). + // 2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c) + + // Map APIC index into APIC ID + // IDs 3, 4, 5, and 8+ are available (see above note) + + if (apic_index < 3) + apic_id = apic_index + 3; else - addr=i+5; - /* Read the MBAR address for setting up the io apic in io memory space */ - dword = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - ioapic_a = (uint32_t *) dword; - ioapic_d = ioapic_a +0x04; + apic_id = apic_index + 5; + + ASSERT(apic_id < 16); // ID is only 4 bits + + // Read the MBAR address for setting up the IOAPIC in memory space + // NOTE: this address was assigned during enumeration of the bus + + memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + pIndexRegister = (volatile uint32_t*) memoryBase; + pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); + printk_debug("IOAPIC %d at %02x:%02x.%01x MBAR = %x DataAddr = %x\n", - addr, dev->bus->secondary, - PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn), - ioapic_a, ioapic_d); + apic_id, dev->bus->secondary, PCI_SLOT(dev->path.u.pci.devfn), + PCI_FUNC(dev->path.u.pci.devfn), pIndexRegister, pWindowRegister); -#if 0 - dword = (u32)ioapic_a; - word = 0x8000 + ((dword >>8)&0x0fff); - pci_write_config_word(dev, ABAR, word); -#endif - /* Set up the io apic for the p64h2 - 1461 */ - *ioapic_a=0; - *ioapic_d=(addr<<24); /* Set the address number */ - *ioapic_a=3; - *ioapic_d=1; /* Enable the io apic */ + apic_id <<= 24; // Convert ID to bitmask - /* This code test the setup to see if we really found the io apic */ - *ioapic_a=0; - dword=*ioapic_d; - printk_debug("PCI %d apic id = %x\n",addr,dword); - if(dword!=(addr<<24)) - for(;;); - *ioapic_a=3; - dword=*ioapic_d; - printk_debug("PCI %d apic DT = %x\n",addr,dword); - if(dword!=1) - for(;;); + *pIndexRegister = 0; // Select APIC ID register + *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID + + if ((*pWindowRegister & (0xF<<24)) != apic_id) + die("p64h2_ioapic_init failed"); + *pIndexRegister = 3; // Select Boot Configuration register + *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts + if (!(*pWindowRegister & 1)) + die("p64h2_ioapic_init failed"); } static struct device_operations ioapic_ops = { --- src/southbridge/intel/i82870/82870.h.orig 2005-09-08 13:34:48.140625000 -0500 +++ src/southbridge/intel/i82870/82870.h 2005-07-25 09:40:35.109375000 -0500 @@ -1,6 +1,4 @@ /* for io apic 1461 */ -#define PCICMD 0x04 -#define SUBSYS 0x2c #define MBAR 0x10 #define ABAR 0x40 @@ -8,3 +6,10 @@ #define MTT 0x042 #define HCCR 0x0f0 #define ACNF 0x0e0 +#define STRP 0x44 // Strap status register + +#define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN) +#define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero) + +#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + --- src/include/assert.h.orig 1969-12-31 18:00:00.000000000 -0600 +++ src/include/assert.h 2005-07-11 11:03:54.000000000 -0500 @@ -0,0 +1,59 @@ +/* + * $Header: /home/cvs/BIR/ca-cpu/freebios/src/include/assert.h,v 1.1 2005/07/11 16:03:54 smagnani Exp $ + * + * assert.h: Debugging macros + * + * Copyright (C) 2005 Digital Design Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * $Log: assert.h,v $ + * Revision 1.1 2005/07/11 16:03:54 smagnani + * Initial revision. + * + * + */ + +#ifndef __ASSERT_H_DEFINED +#define __ASSERT_H_DEFINED + +// ROMCC doesn't support __FILE__ or __LINE__ :^{ + +#if DEBUG +#ifdef __ROMCC__ +#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); } +#else +#define ASSERT(x) { \ + if (!(x)) \ + { \ + printk_emerg("ASSERT failure: file '%s', line %d\n", __FILE__, __LINE__); \ + die(""); \ + } \ + } +#endif // __ROMCC__ +#else // !DEBUG +#define ASSERT(x) { } +#endif + +#ifdef __ROMCC__ +#define BUG() { die("BUG encountered: system halted\r\n"); } +#else +#define BUG() { \ + printk_emerg("BUG: file '%s', line %d\n", __FILE__, __LINE__); \ + die(""); \ + } +#endif + +#endif // __ASSERT_H_DEFINED ------------------------------------------------------------------------ Steven J. Magnani "I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator!" #include <standard.disclaimer>

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[LinuxBIOS] LNXI Merge: lnxi-patch-05/16
by jason schildt 12 Sep '05

12 Sep '05

DESCRIPTION: ------------------------------------------------- ## lnxi-patch-5 ## src/superio/NSC/pc87360/superio.c Bug fix from &pnp_ops to &ops DIFFSTAT: ------------------------------------------------- superio.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) PATCH: ------------------------------------------------- Index: superio/NSC/pc87360/superio.c =================================================================== --- superio/NSC/pc87360/superio.c (revision 1105) +++ superio/NSC/pc87360/superio.c (working copy) @@ -66,7 +66,7 @@ static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, + pnp_enable_devices(dev, &ops, sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info); } -- Jason W. Schildt LinuxBIOS Software Engineer Linux Networx

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[LinuxBIOS] PATCH: failure/race in secondary CPU startup
by Steven J. Magnani 12 Sep '05

12 Sep '05

This patch does two things: * Prints a failure message when a sibling CPU fails to start (currently, a message is printed only when a CPU enumerated in Config.lb fails to start). * Detects a race condition that results in secondary CPUs using the wrong CPU info. This can occur if the BSP times out waiting for a secondary CPU to respond, for example if the secondary startup code is modified so that an emulator can be used to debug the secondary CPU. PATCH: --- src/cpu/intel/hyperthreading/intel_sibling.c.orig 2005-09-08 13:35:05.578125000 -0500 +++ src/cpu/intel/hyperthreading/intel_sibling.c 2005-09-12 11:24:20.546875000 -0500 @@ -67,7 +67,11 @@ new->path.u.apic.apic_id); #endif /* Start the new cpu */ - start_cpu(new); + if (!start_cpu(new)) { + /* Record the error in cpu? */ + printk_err("CPU %u would not start!\n", + new->path.u.apic.apic_id); + } } } --- src/arch/i386/lib/cpu.c.orig 2005-09-08 13:35:40.875000000 -0500 +++ src/arch/i386/lib/cpu.c 2005-09-12 11:26:27.375000000 -0500 @@ -231,6 +231,14 @@ die("CPU: missing cpu device structure"); } + // Check that we haven't been passed bad information as the result of a race + // (i.e. BSP timed out while waiting for us to load secondary_stack) + + if (cpu->path.u.apic.apic_id != lapicid()) { + printk_err("CPU #%d Initialization FAILED: APIC ID mismatch (%u != %u)\n", + info->index, cpu->path.u.apic.apic_id, lapicid()); + // return without setting initialized flag + } else { /* Find what type of cpu we are dealing with */ identify_cpu(cpu); printk_debug("CPU: vendor %s device %x\n", @@ -247,6 +255,8 @@ } printk_info("CPU #%d Initialized\n", info->index); + } + return; } ------------------------------------------------------------------------ Steven J. Magnani "I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator!" #include <standard.disclaimer>

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coreboot September 2005