coreboot September 2005

coreboot@coreboot.org

45 participants
117 discussions

by Stephen.Kimball＠bench.com

> > Along the same lines, has anyone tried using different size SST chips? I > tried to duplicate the 256KB bios by putting it in a 512KB chip (SST > 28SF040A vs 39SF020A). This didn't seem to work (no beep or video but > didn't try port 80 parallel card yet). Perhaps someone knows if this > should work. Can someone recommend a good place to get a handful of SST > 39SF02A PLCC chips for these experiments? Look for the device data sheet on the SST Web site. If the device is pin compatible, it should work. Usually pin compatible devices have the same first 4 characters and the last 4 describe the capacity. Steve

15 years, 6 months

[LinuxBIOS] Disk Passwords

by Dave Feustel

Does the current Linux Bios support use of disk passwords at bootup as defined in the ATA specs? Thanks, Dave Feustel -- Tired of having to defend against Malware? You know: trojans, viruses, SPYWARE, ADWARE, KEYLOGGERS, rootkits, worms and popups. Then Switch to OpenBSD with a KDE desktop!!!

15 years, 6 months

RE: [LinuxBIOS] APIC IDs for Tyan s2735

by Lu, Yinghai

That is right...that is different to any other E7500 MB. YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Steven J. Magnani Sent: Wednesday, September 14, 2005 11:06 AM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] APIC IDs for Tyan s2735 YhLu - Can you check the mptable for the S2735? If I'm reading it correctly, APIC ID 8 is being used for the ICH, but it seems from the southbridge code that the ICH is hard-coded to 2. ------------------------------------------------------------------------ Steven J. Magnani "I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator!" #include <standard.disclaimer> -- LinuxBIOS mailing list LinuxBIOS(a)openbios.org http://www.openbios.org/mailman/listinfo/linuxbios

15 years, 6 months

RE: [LinuxBIOS] E7501 Raminit rewrite

by Lu, Yinghai

It's good to have spd.h there. But the name should be changed for support DDR2...etc. YH -----Original Message----- From: linuxbios-bounces(a)openbios.org [mailto:linuxbios-bounces@openbios.org] On Behalf Of Steven J. Magnani Sent: Tuesday, September 13, 2005 8:08 AM To: linuxbios(a)openbios.org Subject: [LinuxBIOS] E7501 Raminit rewrite This one ends up being a little more than a "patch". I ended up reorganizing the E7501 raminit code so I could follow it, and fixed some bugs along the way. Significant logical changes: * Added support for "fast" (64-clock) refresh * Added code to support remap window for 3 - 4 GB systems * Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html). * Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted. * Disabled subsystem (vendor) ID configuration * #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html) * Added optional run-time checking of dual-channel compatibility of installed DIMMs * Move JEDEC SPD and SDRAM definitions into reusable #include files Probably, the rewritten code should be reviewed as if it were new. My hope is that it is now easy enough to follow that this shouldn't be too bad. The original code is, of course, in Subversion. Since I reordered the functions as part of the rewrite, a 'diff' of of the new code against the original won't tell you much. I've attached a reordered copy of the Subversion code that won't compile, but should be a little easier to diff against the new code so you can see what's changed. I will hold off on committing this for awhile to give people time to look at it. I know that radical changes are a pain to review, but IMHO the improvement in maintainability is significant. New files that are part of this 'patch', but not included here (I committed these to Subversion): src/include/spd.h src/include/sdram_mode.h src/include/northbridge/intel/e7501/e7501.h Thanks, Steve ------------------------------------------------------------------------ Steven J. Magnani "I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator!" #include <standard.disclaimer>

15 years, 6 months

[LinuxBIOS] APIC IDs for Tyan s2735

by Steven J. Magnani

YhLu - Can you check the mptable for the S2735? If I'm reading it correctly, APIC ID 8 is being used for the ICH, but it seems from the southbridge code that the ICH is hard-coded to 2. ------------------------------------------------------------------------ Steven J. Magnani "I claim this network for MARS! www.digidescorp.com Earthling, return my space modulator!" #include <standard.disclaimer>

15 years, 6 months

[LinuxBIOS] RomCC chews forever (or seemingly forever)

by San Mehat

Hey all, I've been making some modifications to the ck804 early smbus code and i'm noticin that romcc appears to be chewing seemingly forever. Any ideas on how to diagnose this?

15 years, 6 months

[LinuxBIOS] PATCH: ICH bug fixes

by Steven J. Magnani

This patch fixes various LPC bugs in the ICH-4 and ICH-5 code that I noticed while working on the ICH-3: * DMA configuration read only half of the existing bits * 'posted memory write enable' code looks to have been mis-inherited from AMD * NMI/SERR configuration was done in PCI space instead of I/O space * Secondary IDE would be enabled whenever primary IDE was enabled * i82801xx_enable worked incorrectly when called for a PCI device without a corresponding disable bit I don't have any way to test that these do more than compile, although the identical ICH-3 code seems to work OK. The i82801xx_enable functions should be looked at closely since there are differences between the 'CA, 'DBM, and 'ER code. PATCH: --- src/southbridge/intel/i82801er/i82801er_lpc.c.orig 2005-09-08 13:34:49.312500000 -0500 +++ src/southbridge/intel/i82801er/i82801er_lpc.c 2005-09-14 11:07:02.588125000 -0500 @@ -8,9 +8,11 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <arch/io.h> #include "i82801er.h" -void isa_dma_init(void); /* from /pc80/isa-dma.c */ + #define NMI_OFF 0 @@ -52,7 +54,7 @@ { uint16_t word; int i; - word = pci_read_config8(dev, PCI_DMA_CFG); + word = pci_read_config16(dev, PCI_DMA_CFG); word &= ((1 << 10) - (1 << 8)); for(i = 0; i < 8; i++) { if (i == 4) @@ -124,9 +126,15 @@ i82801er_enable_serial_irqs(dev); +#ifdef SUSPICIOUS_LOOKING_CODE + // The ICH-5 datasheet does not mention this configuration register. + // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge, + // which *does* support this functionality. + /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); pci_write_config8(dev, 0x46, byte | (1<<0)); +#endif /* power after power fail */ /* FIXME this doesn't work! */ @@ -145,16 +153,16 @@ #endif /* Set up NMI on errors */ - byte = pci_read_config8(dev, 0x61); - byte |= (1 << 3); /* IOCHK# NMI Enable */ - byte |= (1 << 6); /* PCI SERR# Enable */ - pci_write_config8(dev, 0x61, byte); - byte = pci_read_config8(dev, 0x70); + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - byte |= (1 << 7); /* set NMI */ - pci_write_config8(dev, 0x70, byte); + byte &= ~(1 << 7); /* set NMI */ + outb(byte, 0x70); } /* Initialize the real time clock */ --- src/southbridge/intel/i82801dbm/i82801dbm_lpc.c.orig 2005-09-08 13:34:50.750000000 -0500 +++ src/southbridge/intel/i82801dbm/i82801dbm_lpc.c 2005-09-14 11:07:20.103750000 -0500 @@ -8,9 +8,11 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <arch/io.h> #include "i82801dbm.h" -void isa_dma_init(void); /* from /pc80/isa-dma.c */ + #define NMI_OFF 0 @@ -52,7 +54,7 @@ { uint16_t word; int i; - word = pci_read_config8(dev, PCI_DMA_CFG); + word = pci_read_config16(dev, PCI_DMA_CFG); word &= ((1 << 10) - (1 << 8)); for(i = 0; i < 8; i++) { if (i == 4) @@ -124,9 +126,15 @@ i82801dbm_enable_serial_irqs(dev); +#ifdef SUSPICIOUS_LOOKING_CODE + // The ICH-4 datasheet does not mention this configuration register. + // This code may have been inherited (incorrectly) from code for the AMD 766 southbridge, + // which *does* support this functionality. + /* posted memory write enable */ byte = pci_read_config8(dev, 0x46); pci_write_config8(dev, 0x46, byte | (1<<0)); +#endif /* power after power fail */ /* FIXME this doesn't work! */ @@ -145,16 +153,16 @@ #endif /* Set up NMI on errors */ - byte = pci_read_config8(dev, 0x61); - byte |= (1 << 3); /* IOCHK# NMI Enable */ - byte |= (1 << 6); /* PCI SERR# Enable */ - pci_write_config8(dev, 0x61, byte); - byte = pci_read_config8(dev, 0x70); + byte = inb(0x61); + byte &= ~(1 << 3); /* IOCHK# NMI Enable */ + byte &= ~(1 << 2); /* PCI SERR# Enable */ + outb(byte, 0x61); + byte = inb(0x70); nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - byte |= (1 << 7); /* set NMI */ - pci_write_config8(dev, 0x70, byte); + byte &= ~(1 << 7); /* set NMI */ + outb(byte, 0x70); } /* Initialize the real time clock */ --- src/southbridge/intel/i82801er/i82801er_ide.c.orig 2005-09-14 11:46:49.213125000 -0500 +++ src/southbridge/intel/i82801er/i82801er_ide.c 2005-09-14 11:21:59.916250000 -0500 @@ -26,7 +26,7 @@ word = pci_read_config16(dev, 0x42); word &= ~((1 << 15)); - if (enable_a) { + if (enable_b) { /* Enable secondary ide interface */ word |= (1<<15); printk_debug("IDE1 "); --- src/southbridge/intel/i82801dbm/i82801dbm_ide.c.orig 2005-09-14 11:45:41.197500000 -0500 +++ src/southbridge/intel/i82801dbm/i82801dbm_ide.c 2005-09-14 11:21:10.385000000 -0500 @@ -26,7 +26,7 @@ word = pci_read_config16(dev, 0x42); word &= ~((1 << 15)); - if (enable_a) { + if (enable_b) { /* Enable secondary ide interface */ word |= (1<<15); printk_debug("IDE1 "); --- src/southbridge/intel/i82801er/i82801er.c.orig 2005-09-08 13:34:49.343750000 -0500 +++ src/southbridge/intel/i82801er/i82801er.c 2005-09-14 11:56:26.666250000 -0500 @@ -6,48 +6,58 @@ void i82801er_enable(device_t dev) { - device_t lpc_dev; - unsigned int index; - uint16_t reg_old, reg; - -// all 82801er device ares in bus 0 - unsigned int devfn; - devfn = PCI_DEVFN(0x1f, 0); // lpc - lpc_dev = dev_find_slot(0, devfn); // 0 - if (!lpc_dev ) { - return; - } -#if 0 - if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || - (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) { - return; - } - } -#endif - - index = (dev->path.u.pci.devfn & 7); - if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f - if(index==0){ //1f0 - index = 14; - } - } else { // D=0x1d - index += 8; - } - - reg_old = pci_read_config16(lpc_dev, FUNC_DIS); - reg = reg_old; - reg &= ~(1<<index); // enable it - if (!dev->enabled) { - reg |= (1<<index); // disable it - } - if (reg != reg_old) { - pci_write_config16(lpc_dev, FUNC_DIS, reg); - } - reg = pci_read_config16(lpc_dev, FUNC_DIS); - + unsigned int index = 0; + uint8_t bHasDisableBit = 0; + uint16_t cur_disable_mask, new_disable_mask; + +// all 82801er devices are in bus 0 + unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc + device_t lpc_dev = dev_find_slot(0, devfn); // 0 + if (!lpc_dev) + return;Z + + // Calculate disable bit position for specified device:function + // NOTE: For ICH-5, only the following devices can be disabled: + // D31: F0, F1, F2, F3, F5, F6, + // D29: F0, F1, F2, F3, F7 + + if (PCI_SLOT(dev->path.u.pci.devfn) == 31) { + index = PCI_FUNC(dev->path.u.pci.devfn); + + switch (index) { + case 0: + case 1: + case 2: + case 3: + case 5: + case 6: + bHasDisableBit = 1; + break; + + default: + break; + }; + + if (index == 0) + index = 14; // D31:F0 bit is an exception + + } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) { + index = 8 + PCI_FUNC(dev->path.u.pci.devfn); + + if ((PCI_FUNC(dev->path.u.pci.devfn) < 4) || (PCI_FUNC(dev->path.u.pci.devfn) == 7)) + bHasDisableBit = 1; + } + + if (bHasDisableBit) { + cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); + new_disable_mask = cur_disable_mask & ~(1<<index); // enable it + if (!dev->enabled) { + new_disable_mask |= (1<<index); // disable it + } + if (new_disable_mask != cur_disable_mask) { + pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); + } + } } struct chip_operations southbridge_intel_i82801er_ops = { --- src/southbridge/intel/i82801dbm/i82801dbm.c.orig 2005-09-08 13:34:50.765625000 -0500 +++ src/southbridge/intel/i82801dbm/i82801dbm.c 2005-09-14 11:58:02.353750000 -0500 @@ -6,48 +6,57 @@ void i82801dbm_enable(device_t dev) { - device_t lpc_dev; - unsigned int index; - uint16_t reg_old, reg; - -// all 82801dbm device ares in bus 0 - unsigned int devfn; - devfn = PCI_DEVFN(0x1f, 0); // lpc - lpc_dev = dev_find_slot(0, devfn); // 0 - if (!lpc_dev ) { - return; - } -#if 0 - if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || - (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801DBM_1F0)) { - uint32_t id; - id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); - if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801DBM_1F0 << 16))) { - return; - } - } -#endif - - index = (dev->path.u.pci.devfn & 7); - if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f - if(index==0){ //1f0 - index = 14; - } - } else { // D=0x1d - index += 8; - } - - reg_old = pci_read_config16(lpc_dev, FUNC_DIS); - reg = reg_old; - reg &= ~(1<<index); // enable it - if (!dev->enabled) { - reg |= (1<<index); // disable it - } - if (reg != reg_old) { - pci_write_config16(lpc_dev, FUNC_DIS, reg); - } - reg = pci_read_config16(lpc_dev, FUNC_DIS); - + unsigned int index = 0; + uint8_t bHasDisableBit = 0; + uint16_t cur_disable_mask, new_disable_mask; + +// all 82801dbm devices are in bus 0 + unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc + device_t lpc_dev = dev_find_slot(0, devfn); // 0 + if (!lpc_dev) + return; + + // Calculate disable bit position for specified device:function + // NOTE: For ICH-4, only the following devices can be disabled: + // D31: F0, F1, F3, F5, F6, + // D29: F0, F1, F2, F7 + + if (PCI_SLOT(dev->path.u.pci.devfn) == 31) { + index = PCI_FUNC(dev->path.u.pci.devfn); + + switch (index) { + case 0: + case 1: + case 3: + case 5: + case 6: + bHasDisableBit = 1; + break; + + default: + break; + }; + + if (index == 0) + index = 14; // D31:F0 bit is an exception + + } else if (PCI_SLOT(dev->path.u.pci.devfn) == 29) { + index = 8 + PCI_FUNC(dev->path.u.pci.devfn); + + if ((PCI_FUNC(dev->path.u.pci.devfn) < 3) || (PCI_FUNC(dev->path.u.pci.devfn) == 7)) + bHasDisableBit = 1; + } + + if (bHasDisableBit) { + cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS); + new_disable_mask = cur_disable_mask & ~(1<<index); // enable it + if (!dev->enabled) { + new_disable_mask |= (1<<index); // disable it + } + if (new_disable_mask != cur_disable_mask) { + pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask); + } + } } struct chip_operations southbridge_intel_i82801dbm_control = {

15 years, 6 months

[LinuxBIOS] Awakening noop errors

by Dave Ashley

All, We're working on epia-sp standup and romcc is outputting streams of the following: serial.c:60.51: serial.c:70.29: console.c:6.21: console.c:16.26: console.c:52.36: console.c:72.71: bist.h:11.34: auto.c:175.28: 0x788530 noop Internal compile r warning: awakening noop? serial.c:54.34: serial.c:66.29: console.c:6.21: console.c:16.26: console.c:53.36: console.c:72.71: bist.h:11.34: auto.c:175.28: 0x78b060 noop Internal compile r warning: awakening noop?serial.c:60.51: serial.c:70.29: console.c:6.21: console.c:16.26: console.c:53.36: console.c:72.71: bist.h:11.34: auto.c:175.28: 0x78cfa0 noop Internal compile r warning: awakening noop? serial.c:54.34: serial.c:66.29: console.c:6.21: console.c:16.26: console.c:54.36: console.c:72.71: bist.h:11.34: auto.c:175.28: 0x78fad0 noop Internal compile r warning: awakening noop? What do I do to fix this? -Dave

15 years, 6 months

[LinuxBIOS] LinuxBIOS Summit: Draft Schedule

by Li-Ta Lo

Hi, We are working on the agenda for LinuxBIOS summit. Here is a draft version. Please give us any suggestion and help you have. We categorized the attendance into three parties, the vendors, the users and the developers. We hope the three parties can each describe their past experience, outstanding problems and future directions such that these three parties can help each other. The first day will be focus on current status report. We are going to have Oct. 11 Vendor Presentation 1. Richard Bruner from AMD will talk about AMD's plan on LinuxBIOS and their roadmap for their products. 2. LNXI will give us their experience on integrating LinuxBIOS in their cluster products. 3. Terra soft will give us their plan of using LinuxBIOS in their PPC 970 products. User Experience Users from Sandia and Los Alamos will talk on their experience of using LinuxBIOS in clusters. Developer Status Report Developers will give presentations and hands-on demo of recent development. Topics includes: 1. Dual Core support for AMD K8 2. Cache As Ram support for Intel and AMD processors. 3. Integrating VGA BIOS support in your LinuxBIOS. On the second day we will focus on making LinuxBIOS more friendly for people of the three parties: Oct. 12 User Friendly 1. User Interface: What kind of default payload and/or user interface are we going to use? Do we want it to be command line or menu style? 2. User's Manual. Developer Friendly 1. KConfig: Josaih England will show us his work on using KConfig to replace the current config tool. 2. Development Model: What is the svn commit and release process? 3. Device Object Model: People still complain about the complexity of the current device model. Can we make it easier to work with? What is the impact of a new config too like #1 on the device model? How are we going to generate PIRQ/ACPI etc. tables? 4. Programmer's Manual. Vendor Friendly 1. We need to discuss the possibility of signing N-party NDA with vendors for their unreleased products. 2. How can we ensure 3rd party that our code is clean and free of legal trouble? 3. Binary blob and EFI/Tiano Interface. How are we going to play nice with Intel? Hackathon If anyone get inspired during the discussion, start implement your idea immediately!! On the third day we will look forward further into the future: Oct. 13 Crazy Ideas 1. FreeFI: Possible name change and official FSF sponsorship. 2. LinuxBIOS as Linux: Ron just doesn't give up his old LinuxBIOS==Linux idea. He will show how he is recycling it. Homework Assignment Hey, you had a good time. It is time to do your homework now. -- Li-Ta Lo <ollie(a)lanl.gov> Los Alamos National Lab

15 years, 6 months

[LinuxBIOS] LinuxBIOS Summit: Call for Speaker from Embedded World

by Li-Ta Lo

Hi, While we are working on the agenda of LinuxBIOS summit, we found that we desperately need speakers from embedded device world. Current we have no speaker who can stand for them. We would like to hear from people who is currently deploying or trying to deploying LinuxBIOS in their products. What problems did you encounter when using LinuxBIOS? What kind of support do you need from vendors and the developer community? Could you give us a big picture of where and how many LinuxBIOS embedded systems you have deployed out there? People complained about that LinuxBIOS development was too slanted to cluster application. Now it is time for people to hear from you!!! So please, come up and speak!!! -- Li-Ta Lo <ollie(a)lanl.gov> Los Alamos National Lab

15 years, 6 months

← Newer
1
2
3
4
5
6
7
8
9
...
12
Older →

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot September 2005