On 6/27/05, yhlu <yinghailu(a)gmail.com> wrote:
> I can not tell if you don't post your MB Config.lb
>
> To use cache_as_ram you need to update your MB Config.lb and Option.lb
> and have your new cache_as_ram_auto.c
I referenced tyan s2885 codes to modify my Config.lb, Options.lb and
cache_as_ram_auto.c
I just tried to build tyan s2885 images form a clean updated tree and
met the same problem.
Regards,
Liu Tao
> Adam Talbot <talbotx(a)comcast.net> writes:
> Is ECC memory support a function of BIOS or hard ware?
Both. The memory controller and the DIMMs have to support it, and the BIOS
has to configure the memory controller to enable it.
Steve Magnani
www.digidescorp.com
I'm adding print_debug statements to tyan/s2891 and
now I get some code overlap messages
/usr/bin/ld: section .reset [00000000fffffff0 ->
00000000ffffffff] overlaps section .rom
[00000000ffff6770 -> 000000010000014f]
/usr/bin/ld: section .id [00000000ffffff69 ->
00000000ffffff7f] overlaps section .rom
[00000000ffff6770 -> 000000010000014f]
/usr/bin/ld: section .romstrap [00000000ffffffa0 ->
00000000ffffffef] overlaps section .rom
[00000000ffff6770 -> 000000010000014f]
I'm not quite sure where this comes from. I've
compiled this many times and it works great. Where
(options config) are the setting for this?
A document pointer or a quick explaination would be
great
Thanks
Steve
Hi all,
I've reached the point where LB is attempting to start the secondary CPU
on my custom board. As near as I can tell, LB thinks the secondary CPU
isn't responding. This could be a hardware problem, or a LB issue of some
sort.
CPU 6 would not start!
CPU 6 did not initialize!
First thing I wanted to check was that LB is using the right APIC ID in
the messages it's sending. But I haven't been able to find a good
explanation anywhere of how local APIC IDs are assigned in dual-Xeon
systems. All Intel says with any certainty is that the power-up sequence
includes setting a unique ID for each LAPIC. There is a format to the IDs
(i.e. some bits for logical processor, some for socket, some for APIC
cluster), but nothing that says (for instance) "One Xeon chip is assigned
LAPIC IDs 0 & 1 and the second is assigned LAPIC IDs 6 & 7".
Looking over the s2735 config, and anything I found on the Internet, it
seems that this is how dual-Xeon boards work. Does anyone know why? Do the
addresses come out like this any time you have a dual-Xeon board, and
every time you power it up? Or are there some pins that have to be
strapped a certain way to end up with these IDs? (Side note, some Xeons
support reset-time config of APIC cluster ID - mine don't). The way I'm
interpreting the Intel documentation, it looks like the only way to find
out a secondary CPU's LAPIC ID is to start it (via an IPI broadcast?) and
have it write it somewhere.
Thanks,
Steve
www.digidescorp.com
