coreboot January 2005

coreboot@coreboot.org

43 participants
155 discussions

Geode in Wyse Winterms
by Hamish Guthrie Maillists 17 Jan '05

17 Jan '05

Hi there, Has anyone looked at getting LinuxBIOS running in Wyse Winterms - I have a huge number of these devices (WT3350 and WT3360's) which are now virtually paperweights, but with Linux should still be very usable. Thanks in advance Hamish -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.300 / Virus Database: 265.6.12 - Release Date: 14/01/2005

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Installing the linuxbios
by Teodor Mircea Liviu Gordes 17 Jan '05

17 Jan '05

I'm right now trying to install the linuxbios on a DFI P4M266A-MLV board can somebody help me how to make this step by step...: I want to install by a boot floppy is it possible? Please help me!!!!!!!!!!!!!!!!! _________________________________________________________________ Del din verden med MSN Spaces http://spaces.msn.com

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RE: Running with VGA
by YhLu 17 Jan '05

17 Jan '05

I add the code to amd_earlymtrr.c but found two problem 1. in the cpu init, the second cpu cache can not be enabled. (still using value set by amd_earlymtrr.c). ( before the amd_mtrr.c called by init). 2. some slow in auto.c stage. Maybe because of before enable cache for LinuxBIOS rom flash, there is more instruction to enable fixed mtrrs. So I prefer to two phase dev_init loop. If you want me send the amd_earlymtrr.c with fixed mtrr enablement, please let me know. YH -----Original Message----- From: Li-Ta Lo [mailto:ollie@lanl.gov] Sent: Friday, January 14, 2005 2:13 PM To: YhLu Cc: Sagiv Yefet; LinuxBIOS Subject: RE: Running with VGA On Fri, 2005-01-14 at 12:45, YhLu wrote: > I check the amd_early_mtrr.c with old amd earymtrr.inc. It seems the only > difference is not enable SYSCFG_MSR_MtrrFixDramModEn before clear MTRR > fixed. > Probably I didn't commit all the old code I used to have. Anyway, the things we have to do in early_mtrr.c are: 1. enable SYSCFG_MSR_MtrrFixDramModEn 2. set fixed mtrrs for 0-0x9FFFF and 0xC0000-0xFFFFF as WB and READ_MEM and WRITE_MEM 3. set fixed mtrrs for 0xA0000-0xBFFF to UC 4. disable SYSCFG_MSR_MtrrFixDramModEn 5. enable SYSCFG_MSR_MtrrFixDramEn Ollie > I enable that, but the result shows no change.... > > YH

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RE: Running with VGA
by YhLu 17 Jan '05

17 Jan '05

Ok with me. -----Original Message----- From: Li-Ta Lo [mailto:ollie@lanl.gov] Sent: Monday, January 17, 2005 5:21 PM To: YhLu Cc: Sagiv Yefet; LinuxBIOS Subject: RE: Running with VGA On Mon, 2005-01-17 at 18:31, YhLu wrote: > You will create another member in dev? > in device_operations. Ollie > YH > > -----Original Message----- > From: Li-Ta Lo [mailto:ollie@lanl.gov] > Sent: Monday, January 17, 2005 5:18 PM > To: YhLu > Cc: Sagiv Yefet; LinuxBIOS > Subject: RE: Running with VGA > > On Fri, 2005-01-14 at 20:59, YhLu wrote: > > I add the code to amd_earlymtrr.c but found two problem > > 1. in the cpu init, the second cpu cache can not be enabled. (still using > > value set by amd_earlymtrr.c). ( before the amd_mtrr.c called by init). > > 2. some slow in auto.c stage. Maybe because of before enable cache for > > LinuxBIOS rom flash, there is more instruction to enable fixed mtrrs. > > > > So I prefer to two phase dev_init loop. > > > > That is fine by me. How do you think put the ROM post into > dev_post() and leave dev_init alone. > > Ollie > > > If you want me send the amd_earlymtrr.c with fixed mtrr enablement, please > > let me know. > > >

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RE: Running with VGA
by YhLu 17 Jan '05

17 Jan '05

You will create another member in dev? YH -----Original Message----- From: Li-Ta Lo [mailto:ollie@lanl.gov] Sent: Monday, January 17, 2005 5:18 PM To: YhLu Cc: Sagiv Yefet; LinuxBIOS Subject: RE: Running with VGA On Fri, 2005-01-14 at 20:59, YhLu wrote: > I add the code to amd_earlymtrr.c but found two problem > 1. in the cpu init, the second cpu cache can not be enabled. (still using > value set by amd_earlymtrr.c). ( before the amd_mtrr.c called by init). > 2. some slow in auto.c stage. Maybe because of before enable cache for > LinuxBIOS rom flash, there is more instruction to enable fixed mtrrs. > > So I prefer to two phase dev_init loop. > That is fine by me. How do you think put the ROM post into dev_post() and leave dev_init alone. Ollie > If you want me send the amd_earlymtrr.c with fixed mtrr enablement, please > let me know. >

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linkb_to_host and addon display adapter override onboard display card
by YhLu 17 Jan '05

17 Jan '05

linkb_to_host and addon display adapter override onboard display card committed. 1. linkb_to_host use bit 10 to find it if linkb to host. Please refer to in_coherent.c and hypertransport.c 2. Add vga_pri in device.c to make it = add on card instead of onboard vga, if add on card presents. Please refer to device.c and pci_rom.c YH

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print_spew() question
by Stephen.Kimball＠bench.com 17 Jan '05

17 Jan '05

I changed mainboard/vendor/board/Options.lb: ## Request this level of debugging output default DEFAULT_CONSOLE_LOGLEVEL=9 ## At a maximum only compile in this level of debugging default MAXIMUM_CONSOLE_LOGLEVEL=9 Then I did a buildtarget, "make clean" and a "make". Then romcc complains that auto.c:3.0: macro DEFAULT_CONSOLE_LOGLEVEL already defined make[1]: *** [auto.inc] Error 1 How are you suppose to change the DEFAULT_CONSOLE_LOGLEVEL to get print_spew() to print? Regards, Steve Kimball Banchmark Electronics

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superio connected to the PCI bus?
by Andreas Bach Aaen (AH/TED) 17 Jan '05

17 Jan '05

Hi, can I from the lspci output see where the superio chips is connected? My lspci -tv says: lspci -tv -[00]-+-00.0 Intel Corp. E7501 Memory Controller Hub +-00.1 Intel Corp. E7000 Series Host RASUM Controller +-02.0-[02-04]--+-1c.0 Intel Corp. 82870P2 P64H2 I/OxAPIC | +-1d.0-[04]-- | +-1e.0 Intel Corp. 82870P2 P64H2 I/OxAPIC | \-1f.0-[03]--+-02.0 Intel Corp. 82546GB Gigabit Ethernet Controller | +-02.1 Intel Corp. 82546GB Gigabit Ethernet Controller | +-03.0 Intel Corp. 82546GB Gigabit Ethernet Controller | +-03.1 Intel Corp. 82546GB Gigabit Ethernet Controller | \-04.0 LSI Logic / Symbios Logic 53c1010 66MHz Ultra3 SCSI Adapter +-02.1 Intel Corp. E7000 Series Hub Interface B RASUM Controller +-1e.0-[01]-- +-1f.0 Intel Corp. 82801DB/DBL (ICH4/ICH4-L) LPC Bridge +-1f.1 Intel Corp. 82801DB/DBL (ICH4/ICH4-L) UltraATA-100 IDE Controller \-1f.3 Intel Corp. 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller The superIO chip is PC87417 which in linuxbios context probably would look a lot like tha allready supported PC8736[06] chips. I would help me a lot if some of your configuration scripts contained output from lspci, so you could see the coupling between the PCI bus description in your configuration language and the lspci format. Regards, -- Andreas Bach Aaen System Developer, M. Sc. Ericsson Telebit A/S tel: +45 89 38 51 00 Skanderborgvej 232 fax: +45 89 38 51 01 8260 Viby J Denmark andreas.b.aaen(a)ericsson.com

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compilation of tyan2735 linuxbios2
by Andreas Bach Aaen (AH/TED) 16 Jan '05

16 Jan '05

Hi, I am looking at a board chipsetwise a lot like the Tyan2735. When I compile tyan2735 I get the following problem from a few days old CVS shapshot: --------------- cp linuxbios_ram.nrv2b linuxbios_ram.rom echo "INCLUDE ldoptions" > ldscript.ld ; for file in /home/tedaba/linuxbios/x/freebios2/src/arch/i386/init/ldscript.lb /home/tedaba/linuxbios/x/freebios2/src//cpu/x86/16bit/entry16.lds /home/tedaba/linuxbios/x/freebios2/src//cpu/x86/32bit/entry32.lds /home/tedaba/linuxbios/x/freebios2/src//cpu/x86/32bit/reset32.lds /home/tedaba/linuxbios/x/freebios2/src//arch/i386/lib/id.lds ; do echo "INCLUDE $file" >> ldscript.ld ; done gcc -m32 -nostdlib -nostartfiles -static -o linuxbios -T ldscript.ld crt0.o /usr/bin/ld: section .reset [00000000fffdfff0 -> 00000000fffdffff] overlaps section .rom [00000000fffdc6eb -> 00000000fffe3e2f] /usr/bin/ld: section .id [00000000fffdffd9 -> 00000000fffdffef] overlaps section .rom [00000000fffdc6eb -> 00000000fffe3e2f] collect2: ld returned 1 exit status make[1]: *** [linuxbios] Error 1 make[1]: Leaving directory `/home/tedaba/linuxbios/x/freebios2/targets/tyan/s2735/s2735/normal' ---------------------- Can you see what's wrong in this configuration. I have actually ordered a tyan2735 board for testing, so I would really like to get this up and running. Regards, -- Andreas Bach Aaen System Developer, M. Sc. Ericsson Telebit A/S tel: +45 89 38 51 00 Skanderborgvej 232 fax: +45 89 38 51 01 8260 Viby J Denmark andreas.b.aaen(a)ericsson.com

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Re: HP Vectra VLi8 (intel 440bx)
by Richard Smith 15 Jan '05

15 Jan '05

On Sat, 15 Jan 2005 14:04:49 +0200, Mike Jackson <mj(a)sci.fi> wrote: > Richard Smith wrote: > > > send us a lspci -v and then look on the board and find out what > > superIO you have. You look good on the chipsets. The superIO will probally have a name like, ITE, NSC, SMC, winbond. It will probally be in a quad flat pack so its a rectangular surface mount chip with gull wing pins on all sides. The bios will either be a 32pin DIP or PLCC or perhaps a TSOP. the DIP is very rectangular and has pins that come out of the chip bend 90 degrees and then extend past the chip. What you normally think of for a chip. It either has to be mounted in holes or in a socket. The PLCC will be a square and will have pins on the side that are kinda shaped like a D. It can be surface mounted or have a socket. The TSOP will be very wide and flat with pins on the sides. Gull wing but they will be really small and close together. TSOP are really low profile. Itgoing to be surface mounted. If you can take a high res picture(s) of the board I can probally find them for you. -- Richard A. Smith

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coreboot January 2005