Thanks. I suspected the HT frequency change needed the soft_reset.
I don't want to try LD_STOP so I'll need to get warm or soft reset to work.
Steve
-----Original Message-----
From: Stefan Reinauer [mailto:stepan@openbios.org]
Sent: Monday, January 24, 2005 12:57 PM
To: Kimball, Stephen
Cc: linuxbios(a)clustermatic.org
Subject: Re: HT initialization
* Stephen.Kimball(a)bench.com <Stephen.Kimball(a)bench.com> [050124 17:38]:
> I'm trying to port LinuxBIOS to a Opteron board with a CK804.
IIRC Yinghai Lu did some CK804 work as well.
http://www.clustermatic.org/pipermail/linuxbios/2004-August/008797.html
> In auto.c I notice that most boards call ht_setup_chain() and use the
> return code to see if a reset is needed. Since I can't seem to get
> soft_reset() to work with the CK804, can some on tell me why HT
> initialization needs a reset? Thanks.
The hypertransport links only change their speed after an LDTSTOP_L
signal or soft reset. Otherwise the values written to the registers are
not in charge.
Since LDTSTOP is more complicated, though it has less impact on the
system, LinuxBIOS uses soft reset all over the place.
You need to check where your southbridge is and adapt the soft_reset()
function in auto.c (bus,dev,fn number etc)
Stefan
I can not release the code now and it could take some time to get it
reviewed.
YH
> -----Original Message-----
> From: Stefan Reinauer [mailto:stepan@openbios.org]
> Sent: Monday, January 24, 2005 9:57 AM
> To: Stephen.Kimball(a)bench.com
> Cc: linuxbios(a)clustermatic.org
> Subject: Re: HT initialization
>
> * Stephen.Kimball(a)bench.com <Stephen.Kimball(a)bench.com>
> [050124 17:38]:
> > I'm trying to port LinuxBIOS to a Opteron board with a CK804.
>
> IIRC Yinghai Lu did some CK804 work as well.
> http://www.clustermatic.org/pipermail/linuxbios/2004-August/00
> 8797.html
>
> > In auto.c I notice that most boards call ht_setup_chain()
> and use the
> > return code to see if a reset is needed. Since I can't seem to get
> > soft_reset() to work with the CK804, can some on tell me why HT
> > initialization needs a reset? Thanks.
>
> The hypertransport links only change their speed after an
> LDTSTOP_L signal or soft reset. Otherwise the values written
> to the registers are not in charge.
>
> Since LDTSTOP is more complicated, though it has less impact
> on the system, LinuxBIOS uses soft reset all over the place.
>
> You need to check where your southbridge is and adapt the
> soft_reset() function in auto.c (bus,dev,fn number etc)
>
> Stefan
>
>
> _______________________________________________
> Linuxbios mailing list
> Linuxbios(a)clustermatic.org
> http://www.clustermatic.org/mailman/listinfo/linuxbios
>
Hi,
I'm trying to port LinuxBIOS to a Opteron board with a CK804.
In auto.c I notice that most boards call ht_setup_chain() and use the return code to see if a reset is needed. Since I can't seem to get soft_reset() to work with the CK804, can some on tell me why HT initialization needs a reset? Thanks.
Steve
* Yinghai Lu <yhlu(a)tyan.com> [050124 04:44]:
> what's other SPD about your DIMM? Brand & model....
>
> That bit means x4 DIMM.
>
> YH
I don't have the list at hand, but the only difference in SPD-ROM that
is actually read by LinuxBIOS is the "Primary SDRAM Width" byte.
As far as I see it, there are 8x and 16x DIMMs as well, and they also
need the x4 DIMM bit set in the DRAM controller to work.
With that bit set they do work nicely though.
Stefan.
Hi,
The following function in freebios2/src/northbridge/amd/amdk8/raminit.c
is obviously wrong.
static int update_dimm_x4(const struct mem_controller *ctrl, const
struct mem_param *param, int i)
{
uint32_t dcl;
int value;
int dimm;
value = spd_read_byte(ctrl->channel0[i], 13);
if (value < 0) {
return -1;
}
dimm = i;
dimm += DCL_x4DIMM_SHIFT;
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~(1 << dimm);
if (value == 4) {
dcl |= (1 << dimm);
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
return 1;
}
Especially the part that checks the Primary SDRAM Width for a value
of 4. The SPD roms I am using have the value 8 in there and memory
does not initialize correctly.
Checking (value == 4 || value == 8) or (value >= 0x4) helps, but I
have no idea whether that is correct. It appears that something else
has to be done. I've also seen RAMs with a value of 0x10.
Comments? Otherwise I am going to check (value >= 0x4) in somewhen next
week.
Stefan
Hi!
I was just wondering if it's possible to use linuxbios as a kind of
virtualisation machine, meaning that I could use linuxbios to snoop
windows drivers for register hunting (to get real 3D-gfx-support for
instance)? This means that windows would run as a virtual os.
Best regards
Peter K
--
We Can Put an End to Word Attachments:
http://www.fsf.org/philosophy/no-word-attachments.html
What's the functional purpose of auto.c? Obvously to turn on the ram
but what else?
Are the #includes distributed through the file for a romcc reason?
--
Richard A. Smith
> >
> > I changed mainboard/vendor/board/Options.lb:
> >
> > ## Request this level of debugging output
> > default DEFAULT_CONSOLE_LOGLEVEL=9
> > ## At a maximum only compile in this level of debugging
> > default MAXIMUM_CONSOLE_LOGLEVEL=9
>
> you don't change it there, you change it in your targets file.
>
OK, so do I change the targets/vendor/board/Config.lb file:
target board
mainboard vendor/board
romimage "normal"
option DEFAULT_CONSOLE_LOGLEVEL=7 <<=== add this line?
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x12000
option LINUXBIOS_EXTRA_VERSION=".0-Normal"
payload ../../../../../util/filo/filo.elf
end
romimage "fallback"
option DEFAULT_CONSOLE_LOGLEVEL=7 <<=== add this line?
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x12000
option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
payload ../../../../../util/filo/filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
where the levels are defined in include/console/loglevel.h
#define BIOS_EMERG 0 /* system is unusable */
#define BIOS_ALERT 1 /* action must be taken immediately */
#define BIOS_CRIT 2 /* critical conditions */
#define BIOS_ERR 3 /* error conditions */
#define BIOS_WARNING 4 /* warning conditions */
#define BIOS_NOTICE 5 /* normal but significant condition */
#define BIOS_INFO 6 /* informational */
#define BIOS_DEBUG 7 /* debug-level messages */
#define BIOS_SPEW 8 /* Way too many details */
Steve
Accoding to Eric's idea to move cpu init before pci_device.
Move apic cluster before pci_domain in MB Config.lb
add some lines in northbridge.c
So in the MB Config.lb
apic cluster can only have one child.
Also can remove the northbridge/amd/k8 there is incoherent device under it.
For my 8 way system can keep MB Config.lb shorter.
Regards
Yinghai Lu
With the log level up at 8, I have confirmed that my via/epia build is
not calling southbridge_init to set up the vt8231. I have confirmed
that the code from vt8231.c, is in the binary, it's just not getting
invoked. With the exception of enabling the serial console and boosting
the log level, my target Config.lb, mainboard Config.lb and Options.lb
files are identical to those in CVS (copied below).
Can anybody point me at some likely places to dive in and figure out
why the build is putting this code in the LB binary, but it's not
getting called at run time?
I believe this is the reason that once control is passed off to the
payload (filo), it can't see any ide devices. I'm working my way
through the config/build/boot paths, trying to understand how the config
tool uses the Config.lb and Options.lb files to assemble the build tree,
but it's really slow going. It's a very cool system that has been put
together, but like all cool systems that do hard stuff, it's got a
pretty serious learning curve.... 8^)=
Thanks!
-Al
------mainboard Config.lb-------
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
default ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE +
ROM_SECTION_OFFSET + 1)
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
##
## Compute where this copy of linuxBIOS will start in the boot rom
##
default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I.
$(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS)
$(MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where linuxBIOS is entered)
##
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/via/vt8601
device pci_domain 0 on
device pci 0.0 on
chip southbridge/via/vt8231
register "enable_usb" = "0"
register "enable_native_ide" = "0"
register "enable_com_ports" = "1"
register "enable_keyboard" = "0"
register "enable_nvram" = "1"
device pci 11.0 on # Southbridge
device pci 11.1 on end # Ide
device pci 11.2 off end # Usb
device pci 11.3 off end # Usb
device pci 11.4 off end # ACPI
device pci 11.5 off end # Audio
device pci 11.6 on # Com
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
register "com1" = "{1}"
end
end
device pci 12.0 on end # Ethernet
end
end
end
end
chip cpu/via/model_centaur
end
end
-------target Config.lb--------
# Sample config file for EPIA
# This will make a target directory of ./epia
target epia
mainboard via/epia
#
# Via Epia
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
# payload ../../../../../../filo.elf
payload ../../../../../../filo-0.4.2/filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
# payload ../../../../../../filo.elf
payload ../../../../../../filo-0.4.2/filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
-------mainboard Options.lb--------
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
uses CONFIG_ROM_STREAM
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses LINUXBIOS_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses HEAP_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_MP_TABLE
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
## ARH 01/19/05
uses CONFIG_CONSOLE_SERIAL8250
uses DEFAULT_CONSOLE_LOGLEVEL
default CONFIG_CONSOLE_SERIAL8250=1
default DEFAULT_CONSOLE_LOGLEVEL=8
## ARH 01/19/05
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
###
### Build options
###
##
## Build code for the fallback boot
##
default HAVE_FALLBACK_BOOT=1
##
## no MP table
##
default HAVE_MP_TABLE=0
##
## Build code to reset the motherboard from linuxBIOS
##
default HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=5
#object irq_tables.o
##
## Build code to export a CMOS option table
##
default HAVE_OPTION_TABLE=1
###
### LinuxBIOS layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
##
## Use a small 8K stack
##
default STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default USE_OPTION_TABLE = 0
default _RAMBASE = 0x00004000
default CONFIG_ROM_STREAM = 1
##
## The default compiler
##
default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
end
--
Al Hooton
al-at-hootons-dot-org
========
Maintainer of the linux-based open-source project Parapin.
http://www.sf.net/projects/parapin/
========
