coreboot March 2004

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166 discussions

Status AMD64 ram init
by Stefan Reinauer 20 Mar '04

20 Mar '04

Excerpt from current solo build: LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting... setting up resource map....done. ht reset - LinuxBIOS-1.1.6.0-Fallback Fr Mär 19 14:43:18 CET 2004 starting... setting up resource map....done. Ram1.00 Ram2.00 Bad SPD value Using the default hynix PC2100U 256MB DDR 266MHz CL2.5 modules. I'm building a debug image which dumps the spd roms... Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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Unions?
by Stefan Reinauer 19 Mar '04

19 Mar '04

./romcc -mcpu=k8 -O2 ./auto.E > auto.inc path.h:31.13: unions not yet supported Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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AMD K8 memory bug with more than 2 banks
by Craig C Forney 18 Mar '04

18 Mar '04

I ran into a problem with a Dual Opeteron cPCI board we developed with 4 banks of memory. It showed up when the third and fourth banks were populated. I narrowed it down to a problem in src/amd/amdk8/raminit.c. There is a '+' where there should be a '*', causing the SPD settings to get corrupted, which causes bizarre results which varies depending on the memory parameters read from the DIMMs. One possible result is that some DIMMs will work marginally because one or more of their settings has been corrupted. This patch seems to resolve the problem. I'm not sure if anybody else out there is accessing 4 banks of memory via the Opteron memory interface, so it might be just us, but it would probably be a good idea to commit this patch to the freebios2 source tree. Can someone take this on? Thanks, Craig Forney Opus Innovations LLC diff -Naur raminit.c.orig raminit.c --- raminit.c.orig 2004-03-16 13:25:05.000000000 -0800 +++ raminit.c 2004-03-16 13:42:30.000000000 -0800 @@ -924,7 +924,7 @@ sz.side2 = 0; } map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); - map &= ~(0xf << (index + 4)); + map &= ~(0xf << (index * 4)); /* For each base register. * Place the dimm size in 32 MB quantities in the bits 31 - 21.

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答复: AMD K8 memory bug with more than 2 banks
by YhLu 18 Mar '04

18 Mar '04

According to data sheet, should do the change. -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月18日 16:23 收件人: Craig C Forney 抄送: linuxbios(a)clustermatic.org 主题: Re: AMD K8 memory bug with more than 2 banks I have applied your fix and booted it up on a Tyan S2885 mainboard with four banks full, but have not noticed any change in non-reserved registers on the AMD 8111. Can you please elaborate on exactly what changes I might observe? I want to check out the specifications on the memory we're using and make sure we're getting the right values. On Tue, 16 Mar 2004, Craig C Forney wrote: > > I ran into a problem with a Dual Opeteron cPCI board we developed with 4 > banks of memory. It showed up when the third and fourth banks were > populated. I narrowed it down to a problem in src/amd/amdk8/raminit.c. > There is a '+' where there should be a '*', causing the SPD settings to > get corrupted, which causes bizarre results which varies depending on > the memory parameters read from the DIMMs. One possible result is that > some DIMMs will work marginally because one or more of their settings > has been corrupted. > > This patch seems to resolve the problem. I'm not sure if anybody else > out there is accessing 4 banks of memory via the Opteron memory > interface, so it might be just us, but it would probably be a good idea > to commit this patch to the freebios2 source tree. Can someone take > this on? > > Thanks, > > Craig Forney > Opus Innovations LLC > > diff -Naur raminit.c.orig raminit.c > --- raminit.c.orig 2004-03-16 13:25:05.000000000 -0800 > +++ raminit.c 2004-03-16 13:42:30.000000000 -0800 > @@ -924,7 +924,7 @@ > sz.side2 = 0; > } > map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP); > - map &= ~(0xf << (index + 4)); > + map &= ~(0xf << (index * 4)); > > /* For each base register. > * Place the dimm size in 32 MB quantities in the bits 31 - 21. > > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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SST49LF008A-WH
by Victor Berdin 18 Mar '04

18 Mar '04

Hi, I checked the device list section but failed to find the mentioned chip. The closest one however is an SST49LF004. I would like to know if I can use Linux BIOS project in order to replace the original BIOSware? And if so, where can I start? My target board is an AMD GX2 Geode (NatSemi) SBC. `lspci -v` results are listed below. Any help/advice are greately appreciated. P.S., I really don't mind trashing this company hardware ;o) ... but it's best if I can make Linux work wonders on this device without killing innocent transistors. TIA and best regards - Vic ------------------ 00:01.0 Host bridge: National Semiconductor Corporation: Unknown device 0028 (rev 21) Subsystem: National Semiconductor Corporation: Unknown device 0028 Flags: bus master, 66Mhz, medium devsel, latency 248 I/O ports at ac1c [size=4] 00:01.1 VGA compatible controller: National Semiconductor Corporation: Unknown device 0030 (prog-if 00 [VGA]) Subsystem: National Semiconductor Corporation: Unknown device 0030 Flags: 66Mhz, medium devsel Memory at 41000000 (32-bit, non-prefetchable) [size=16M] Memory at 40ffc000 (32-bit, non-prefetchable) [size=16K] Memory at 40ff8000 (32-bit, non-prefetchable) [size=16K] Memory at 40ff4000 (32-bit, non-prefetchable) [size=16K] 00:0e.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C (rev 10) Subsystem: Realtek Semiconductor Co., Ltd. RT8139 Flags: bus master, medium devsel, latency 64, IRQ 11 I/O ports at ee00 [size=256] Memory at efffdf00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 00:0f.0 ISA bridge: National Semiconductor Corporation: Unknown device 002b (rev 13) Subsystem: National Semiconductor Corporation: Unknown device 002b Flags: 66Mhz, medium devsel I/O ports at 6000 [size=8] I/O ports at 6100 [size=256] I/O ports at 6200 [size=64] I/O ports at 1000 [size=32] I/O ports at 9d00 [size=128] I/O ports at 9c00 [size=64] 00:0f.2 IDE interface: National Semiconductor Corporation: Unknown device 002d (prog-if 80 [Master]) Subsystem: National Semiconductor Corporation: Unknown device 002d Flags: bus master, 66Mhz, medium devsel, latency 0 I/O ports at eff0 [size=16] 00:0f.3 Multimedia audio controller: National Semiconductor Corporation: Unknown device 002e Subsystem: National Semiconductor Corporation: Unknown device 002e Flags: bus master, 66Mhz, medium devsel, latency 0, IRQ 11 I/O ports at ed80 [size=128] 00:0f.4 USB Controller: National Semiconductor Corporation: Unknown device 002f (rev 06) (prog-if 10 [OHCI]) Subsystem: National Semiconductor Corporation: Unknown device 002f Flags: bus master, 66Mhz, medium devsel, latency 0, IRQ 11 Memory at effff000 (32-bit, non-prefetchable) [size=4K] 00:0f.5 USB Controller: National Semiconductor Corporation: Unknown device 002f (rev 06) (prog-if 10 [OHCI]) Subsystem: National Semiconductor Corporation: Unknown device 002f Flags: bus master, 66Mhz, medium devsel, latency 0, IRQ 10 Memory at efffe000 (32-bit, non-prefetchable) [size=4K] ---------------

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答复: 答复: 答复: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64 [PMX:#]
by YhLu 18 Mar '04

18 Mar '04

Can you try by block instead of sector? YH -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月18日 13:16 收件人: YhLu 抄送: Li-Ta Lo; ron minnich; LinuxBIOS 主题: Re: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: flash_rom support for AMD64 [PMX:#] I should clarify that statement. The SST49LF040 part will flash with errors under 64-bit SuSE resulting in an unusable part. The PM part will flash properly in both 32-bit and 64-bit environments. On Thu, 18 Mar 2004, Hendricks David W. wrote: > Yes. The SST part will flash under 32-bit Gentoo, but not 64-bit SuSE. > > The PM part will flash using either 32-bit or 64-bit environments. > > On Thu, 18 Mar 2004, YhLu wrote: > > > Does it work in 32 bit? > > > > -----é‚®ä»¶åŽŸä»¶----- > > å‘ä»¶äºº: Hendricks David W. [mailto:dwh@lanl.gov] > > å‘é€æ—¶é—´: 2004å¹´3æœˆ18æ—¥ 13:06 > > æ”¶ä»¶äºº: YhLu > > æŠ„é€: Li-Ta Lo; ron minnich; LinuxBIOS > > ä¸»é¢˜: Re: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: flash_rom support for AMD64 > > > > I have verified this. > > > > The SST part still won't flash under 64-bit SuSE, however. > > > > On Thu, 18 Mar 2004, YhLu wrote: > > > > > It works with pm49lf004 under 64 bit. > > > > > > -----Ã“ÃŠÂ¼Ã¾Ã”ÂÂ¼Ã¾----- > > > Â·Â¢Â¼Ã¾ÃˆÃ‹: Li-Ta Lo [mailto:ollie@lanl.gov] > > > Â·Â¢Ã‹ÃÃŠÂ±Â¼Ã¤: 2004Ã„Ãª3Ã”Ã‚18ÃˆÃ• 11:50 > > > ÃŠÃ•Â¼Ã¾ÃˆÃ‹: YhLu > > > Â³ÂÃ‹Ã: ron minnich; Hendricks David W.; LinuxBIOS > > > Ã–Ã·ÃŒÃ¢: Re: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: Â´Ã°Â¸Â´: flash_rom support for AMD64 > > > > > > On Thu, 2004-03-18 at 12:13, YhLu wrote: > > > > Stuck after 3. > > > > > > > > It seems it doesn't allow write mmio. > > > > > > > > int probe_49fl004 (struct flashchip * flash) > > > > { > > > > volatile char * bios = flash->virt_addr; > > > > unsigned char id1, id2; > > > > printf("3\n"); > > > > *(volatile char *) (bios + 0x5555) = 0xAA; > > > > myusec_delay(10); > > > > printf("4\n"); > > > > *(volatile char *) (bios + 0x2AAA) = 0x55; > > > > myusec_delay(10); > > > > printf("5\n"); > > > > *(volatile char *) (bios + 0x5555) = 0x90; > > > > > > > > > > > > > There is some arithmeatic error in old flash_rom, please > > > cvs update. > > > > > > Ollie > > > > > > _______________________________________________ > > > Linuxbios mailing list > > > Linuxbios(a)clustermatic.org > > > http://www.clustermatic.org/mailman/listinfo/linuxbios > > > > > > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: 答复: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64
by YhLu 18 Mar '04

18 Mar '04

Does it work in 32 bit? -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月18日 13:06 收件人: YhLu 抄送: Li-Ta Lo; ron minnich; LinuxBIOS 主题: Re: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: flash_rom support for AMD64 I have verified this. The SST part still won't flash under 64-bit SuSE, however. On Thu, 18 Mar 2004, YhLu wrote: > It works with pm49lf004 under 64 bit. > > -----ÓÊ¼þÔ¼þ----- > ·¢¼þÈË: Li-Ta Lo [mailto:ollie@lanl.gov] > ·¢ËÍÊ±¼ä: 2004Äê3ÔÂ18ÈÕ 11:50 > ÊÕ¼þÈË: YhLu > ³ËÍ: ron minnich; Hendricks David W.; LinuxBIOS > Ö÷Ìâ: Re: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: ´ð¸´: flash_rom support for AMD64 > > On Thu, 2004-03-18 at 12:13, YhLu wrote: > > Stuck after 3. > > > > It seems it doesn't allow write mmio. > > > > int probe_49fl004 (struct flashchip * flash) > > { > > volatile char * bios = flash->virt_addr; > > unsigned char id1, id2; > > printf("3\n"); > > *(volatile char *) (bios + 0x5555) = 0xAA; > > myusec_delay(10); > > printf("4\n"); > > *(volatile char *) (bios + 0x2AAA) = 0x55; > > myusec_delay(10); > > printf("5\n"); > > *(volatile char *) (bios + 0x5555) = 0x90; > > > > > There is some arithmeatic error in old flash_rom, please > cvs update. > > Ollie > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64
by YhLu 18 Mar '04

18 Mar '04

It works with pm49lf004 under 64 bit. -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月18日 11:50 收件人: YhLu 抄送: ron minnich; Hendricks David W.; LinuxBIOS 主题: Re: 答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64 On Thu, 2004-03-18 at 12:13, YhLu wrote: > Stuck after 3. > > It seems it doesn't allow write mmio. > > int probe_49fl004 (struct flashchip * flash) > { > volatile char * bios = flash->virt_addr; > unsigned char id1, id2; > printf("3\n"); > *(volatile char *) (bios + 0x5555) = 0xAA; > myusec_delay(10); > printf("4\n"); > *(volatile char *) (bios + 0x2AAA) = 0x55; > myusec_delay(10); > printf("5\n"); > *(volatile char *) (bios + 0x5555) = 0x90; > There is some arithmeatic error in old flash_rom, please cvs update. Ollie

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[COMMIT] linuxbios 1.1.6....
by ebiederman＠lnxi.com 18 Mar '04

18 Mar '04

I have needed to sync my code base with the main tree for a while, and I finally find a little bit of time. While what I have is not quite perfect it is the best I can do and should not be too hard to keep up with. I will try to keep things in smaller steps next round. freebios2 is stabilizing so it getting harder to implement a big disruptive change :) The radical changes are how the K8 early setup and memory initialization is accomplished. The whole processes normally only needs a single reset at the very begging of the boot now. I suspect I have broken several Opteron platforms with the changes needed to support this. The hdama and solo ports should still work. The other radical change is I have finally written some generic super code in place and I removed the place holder structures com_ports and lpt_ports from chip.h. I think this only affects ports using the winbond w83627thf chip. It looked like an exact clone of the pc87360 code and I don't believe the two chips are identical. The pc87360/superio.c is not fully functional at only 78 lines of code so it should be simple enough to fix. The other big user visible change is that it is now possible to specify static resource assignments in Config.lb generically. A snippet of the hdama/Config.lb is: superio NSC/pc87360 link 1 pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 pnp 2e.2 off # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 pnp 2e.3 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 pnp 2e.4 off # SWC pnp 2e.5 off # Mouse pnp 2e.6 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 pnp 2e.7 off # GPIO pnp 2e.8 off # ACB pnp 2e.9 off # FSCM pnp 2e.a off # WDT My full commit comments are below. Holler and I will help fix the breakage I have caused. - Moved hlt() to it's own header. - Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type TODO update romcc so I can pass in values from assembly code TODO irq routing in the device tree. Eric Modified Files: src/arch/i386/include/arch/romcc_io.h src/arch/i386/lib/cpu.c src/arch/i386/smp/start_stop.c src/arch/ppc/boot/linuxbios_table.c src/config/Config.lb src/config/Options.lb src/cpu/i386/entry16.inc src/cpu/i386/entry32.inc src/cpu/k8/cpufixup.c src/cpu/k8/earlymtrr.c src/cpu/k8/earlymtrr.inc src/cpu/k8/enable_mmx_sse.inc src/cpu/p6/Config.lb src/cpu/p6/boot_cpu.c src/cpu/p6/earlymtrr.c src/cpu/p6/mtrr.c src/devices/Config.lb src/devices/chip.c src/devices/device.c src/devices/device_util.c src/devices/hypertransport.c src/devices/pci_device.c src/include/string.h src/include/uart8250.h src/include/cpu/k8/mtrr.h src/include/cpu/p6/mtrr.h src/include/device/chip.h src/include/device/device.h src/include/device/hypertransport.h src/include/device/pci_def.h src/include/device/pnp.h src/include/device/resource.h src/include/pc80/mc146818rtc.h src/lib/Config.lb src/lib/memcpy.c src/lib/uart8250.c src/mainboard/amd/quartet/Config.lb src/mainboard/amd/solo/Config.lb src/mainboard/amd/solo/auto.c src/mainboard/amd/solo/cmos.layout src/mainboard/amd/solo/failover.c src/mainboard/amd/solo/mptable.c src/mainboard/arima/hdama/Config.lb src/mainboard/arima/hdama/auto.c src/mainboard/arima/hdama/cmos.layout src/mainboard/arima/hdama/failover.c src/mainboard/arima/hdama/irq_tables.c src/mainboard/arima/hdama/mainboard.c src/mainboard/newisys/khepri/Config.lb src/mainboard/newisys/khepri/auto.c src/mainboard/tyan/s2881/hypertransport.c src/northbridge/amd/amdk8/Config.lb src/northbridge/amd/amdk8/amdk8.h src/northbridge/amd/amdk8/coherent_ht.c src/northbridge/amd/amdk8/cpu_rev.c src/northbridge/amd/amdk8/early_ht.c src/northbridge/amd/amdk8/misc_control.c src/northbridge/amd/amdk8/northbridge.c src/northbridge/amd/amdk8/raminit.c src/northbridge/amd/amdk8/raminit.h src/northbridge/amd/amdk8/reset_test.c src/pc80/Config.lb src/pc80/keyboard.c src/pc80/mc146818rtc_early.c src/pc80/serial.c src/pc80/serial.inc src/southbridge/amd/amd8111/Config.lb src/southbridge/amd/amd8111/amd8111.c src/southbridge/amd/amd8111/amd8111_acpi.c src/southbridge/amd/amd8111/amd8111_early_smbus.c src/southbridge/amd/amd8111/amd8111_ide.c src/southbridge/amd/amd8111/amd8111_lpc.c src/southbridge/amd/amd8111/amd8111_usb.c src/southbridge/amd/amd8111/amd8111_usb2.c src/southbridge/amd/amd8131/amd8131_bridge.c src/superio/NSC/pc87360/chip.h src/superio/NSC/pc87360/superio.c util/newconfig/config.g util/options/build_opt_tbl.c util/romcc/Makefile util/romcc/romcc.c Added Files: src/arch/i386/include/arch/hlt.h src/arch/i386/include/arch/smp/lapic.h src/cpu/i386/bist32.inc src/cpu/i386/bist32_fail.inc src/cpu/p6/pgtbl.c src/devices/pnp_device.c src/include/cpu/p6/pgtbl.h src/include/device/hypertransport_def.h src/include/device/pnp_def.h src/include/pc80/keyboard.h src/lib/memmove.c src/northbridge/amd/amdk8/incoherent_ht.c src/northbridge/amd/amdk8/raminit_test.c src/pc80/isa-dma.c src/southbridge/amd/amd8111/amd8111_pci.c src/superio/NSC/pc87360/pc87360.h src/superio/NSC/pc87360/pc87360_early_serial.c util/romcc/tests/fail_test6.c util/romcc/tests/fail_test7.c util/romcc/tests/fail_test8.c Removed Files: src/mainboard/arima/hdama/example-fallback.config src/mainboard/arima/hdama/example-normal.config src/mainboard/tyan/s2880/static_devices.c.orig src/northbridge/amd/amdk8/mcf0_control.c ----------------------------------------------------------------------

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答复: 答复: 答复: 答复: 答复: flash_rom support for AMD64
by YhLu 18 Mar '04

18 Mar '04

Stuck after 3. It seems it doesn't allow write mmio. int probe_49fl004 (struct flashchip * flash) { volatile char * bios = flash->virt_addr; unsigned char id1, id2; printf("3\n"); *(volatile char *) (bios + 0x5555) = 0xAA; myusec_delay(10); printf("4\n"); *(volatile char *) (bios + 0x2AAA) = 0x55; myusec_delay(10); printf("5\n"); *(volatile char *) (bios + 0x5555) = 0x90; -----邮件原件----- 发件人: ron minnich [mailto:rminnich@lanl.gov] 发送时间: 2004年3月18日 10:35 收件人: Li-Ta Lo 抄送: YhLu; Hendricks David W.; LinuxBIOS 主题: Re: 答复: 答复: 答复: 答复: flash_rom support for AMD64 On Thu, 18 Mar 2004, Li-Ta Lo wrote: > You have to install it from source, I believe. be sure to enable intel configuration types 1 and 2. The standard bios hides the 8151 bridge. ron

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coreboot March 2004