coreboot March 2004

coreboot@coreboot.org

54 participants
166 discussions

Asus Cusi-FX
by Christian Gmeiner 15 Mar '04

15 Mar '04

Hi Mailinglist. I find the project very good and it could speed up the starting of my Video Disc Recorder - VDR - dramaticly. But before i spend money i want to know, if the ASUS Cusi-Fx Mainboard is supported. Thanks, Christian Gmeiner

4 5

linuxbios on epia
by Matt Jarvis 15 Mar '04

15 Mar '04

Hi I'm having a small problem getting Linuxbios to run on an epia 5000. Everything appears to work fine, and I can load my payload of either Etherboot or Filo, but once it gets to actually booting my kernel, the output on the serial console stops at : Jumping to entry point... Is this a problem with my kernel ( the same kernel boots fine with the standard epia bios ) ? I've tried booting both a standard kernel and an elf image of the kernel, with the same outcome. The full output from Linuxbios is below, I hope someone can help with this problem. Thanks in advance Matt LinuxBIOS-1.0.0 Mon Mar 15 12:50:20 GMT 2004 starting... Enabled first bank of RAM: 0x04000000 bytes Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Mon Mar 15 12:50:20 GMT 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:11.0 [1106/8231] PCI: 00:11.1 [1106/0571] PCI: 00:11.2 [1106/3038] PCI: 00:11.3 [1106/3038] PCI: 00:11.4 [1106/8235] PCI: 00:11.5 [1106/3058] PCI: 00:11.6 [1106/3068] PCI: 00:12.0 [1106/3065] PCI: pci_scan_bus for bus 1 PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem PCI: 00:11.1 20 <- [0x00001c40 - 0x00001c4f] io PCI: 00:11.2 20 <- [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 <- [0x00001c20 - 0x00001c3f] io PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:11.5 14 <- [0x00001c50 - 0x00001c53] io PCI: 00:11.5 18 <- [0x00001c60 - 0x00001c63] io PCI: 00:11.6 10 <- [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 <- [0x00001800 - 0x000018ff] io PCI: 00:12.0 14 <- [0xfeb00000 - 0xfeb000ff] mem ASSIGNED RESOURCES, bus 0 done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:11.0 cmd <- 87 PCI: 00:11.1 cmd <- 81 PCI: 00:11.2 cmd <- 01 PCI: 00:11.3 cmd <- 01 PCI: 00:11.4 cmd <- 00 PCI: 00:11.5 cmd <- 01 PCI: 00:11.6 cmd <- 01 PCI: 00:12.0 cmd <- 83 done. Initializing PCI devices... PCI devices initialized Disable Cache Bank2 64MB (MA type 0x8) bank 4 MA 0x0: 0 bytes bank 4 MA 0x8: 0 bytes bank 4 MA 0xe: 0 bytes Enable Cache Total 64MB + frame buffer 0MB Enabling shadow DRAM at 0xC0000-0xFFFFF: done totalram: 64M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB Setting fixed MTRRs(24-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Mainboard fixup IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 Ethernet fixup Configuring VIA LAN 0 LinuxBIOS-1.0.0 Mon Mar 15 12:58:49 GMT 2004 starting... Enabled first bank of RAM: 0x04000000 bytes Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.0.0 Mon Mar 15 12:58:49 GMT 2004 booting... Finding PCI configuration type. PCI: Using configuration type 1 Scanning PCI bus...PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/0601] PCI: 00:01.0 [1106/8601] PCI: 00:11.0 [1106/8231] PCI: 00:11.1 [1106/0571] PCI: 00:11.2 [1106/3038] PCI: 00:11.3 [1106/3038] PCI: 00:11.4 [1106/8235] PCI: 00:11.5 [1106/3058] PCI: 00:11.6 [1106/3068] PCI: 00:12.0 [1106/3065] PCI: pci_scan_bus for bus 1 PCI: pci_scan_bus returning with max=01 PCI: pci_scan_bus returning with max=01 done Allocating PCI resources... PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it PCI: 00:00.0 register 10(00000008), read-only ignoring it ASSIGN RESOURCES, bus 0 PCI: 00:01.0 1c <- [0x00001000 - 0x00000fff] bus 1 io PCI: 00:01.0 24 <- [0xfeb00000 - 0xfeafffff] bus 1 prefmem PCI: 00:01.0 20 <- [0xfeb00000 - 0xfeafffff] bus 1 mem PCI: 00:11.1 20 <- [0x00001c40 - 0x00001c4f] io PCI: 00:11.2 20 <- [0x00001c00 - 0x00001c1f] io PCI: 00:11.3 20 <- [0x00001c20 - 0x00001c3f] io PCI: 00:11.5 10 <- [0x00001000 - 0x000010ff] io PCI: 00:11.5 14 <- [0x00001c50 - 0x00001c53] io PCI: 00:11.5 18 <- [0x00001c60 - 0x00001c63] io PCI: 00:11.6 10 <- [0x00001400 - 0x000014ff] io PCI: 00:12.0 10 <- [0x00001800 - 0x000018ff] io PCI: 00:12.0 14 <- [0xfeb00000 - 0xfeb000ff] mem ASSIGNED RESOURCES, bus 0 done. Enabling PCI resourcess...PCI: 00:00.0 cmd <- 06 PCI: 00:01.0 cmd <- 07 PCI: 00:11.0 cmd <- 87 PCI: 00:11.1 cmd <- 81 PCI: 00:11.2 cmd <- 01 PCI: 00:11.3 cmd <- 01 PCI: 00:11.4 cmd <- 00 PCI: 00:11.5 cmd <- 01 PCI: 00:11.6 cmd <- 01 PCI: 00:12.0 cmd <- 83 done. Initializing PCI devices... PCI devices initialized Disable Cache Bank2 64MB (MA type 0x8) bank 4 MA 0x0: 0 bytes bank 4 MA 0x8: 0 bytes bank 4 MA 0xe: 0 bytes Enable Cache Total 64MB + frame buffer 0MB Enabling shadow DRAM at 0xC0000-0xFFFFF: done totalram: 64M Initializing CPU #0 Enabling cache... Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) type: WB Setting fixed MTRRs(24-88) type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 64MB, type WB DONE variable MTRRs Clear out the extra MTRR's call intel_enable_fixed_mtrr() call intel_enable_var_mtrr() Leave setup_mtrrs done. Max cpuid index : 1 Vendor ID : CentaurHauls Processor Type : 0x00 Processor Family : 0x06 Processor Model : 0x07 Processor Mask : 0x00 Processor Stepping : 0x03 Feature flags : 0x00803035 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Disabling local apic...done. CPU #0 Initialized Mainboard fixup IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 enables in reg 0x40 0x8 enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8f enables in reg 0x9 read back as 0x8a command in reg 0x4 0x81 command in reg 0x4 reads back as 0x7 Ethernet fixup Configuring VIA LAN RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum Final mainboard fixup Southbridge fixup IDE enable in reg. 50 is 0x7 set IDE reg. 50 to 0x7 IRQs in reg. 4c are 0x4 setting reg. 4c to 0x4 enables in reg 0x40 0xb enables in reg 0x40 read back as 0xb enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 Ethernet fixup Configuring VIA LAN RTC Init Invalid CMOS LB checksum setting southbridge Assigning IRQ 12 to 0:11.2 Readback = 12 Assigning IRQ 12 to 0:11.3 Readback = 12 Assigning IRQ 10 to 0:11.5 Readback = 10 Assigning IRQ 10 to 0:11.6 Readback = 10 setting ethernet Assigning IRQ 11 to 0:12.0 Readback = 11 setting pci slot Checking IRQ routing tables... /home/matt/freebios/src/arch/i386/lib/pirq_routing.c: 30:check_pirq_routing_table() - irq_routing_table located at: 0x00009a20 done. Copying IRQ routing tables to 0xf0000...done. Verifing priq routing tables copy at 0xf0000...succeed Wrote linuxbios table at: 00000500 - 000006a0 checksum 7bb5 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.2 37:init_bytes() - zkernel_start:0xfff00000 zkernel_mask:0x0000ffff Found ELF candiate at offset 0 New segment addr 0x100000 size 0x25f20 offset 0xc0 filesize 0xbea8 (cleaned up) New segment addr 0x100000 size 0x25f20 offset 0xc0 filesize 0xbea8 New segment addr 0x125f20 size 0x48 offset 0xbf80 filesize 0x48 (cleaned up) New segment addr 0x125f20 size 0x48 offset 0xbf80 filesize 0x48 Dropping non PT_LOAD segment Dropping non PT_LOAD segment Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000025f20 filesz: 0x000000000000bea8 Clearing Segment: addr: 0x000000000010bea8 memsz: 0x000000000001a078 Loading Segment: addr: 0x0000000000125f20 memsz: 0x0000000000000048 filesz: 0x0000000000000048 Jumping to boot code at 0x1088dc FILO version 0.4.1 (root(a)fedora.rolec.ltd.uk) Mon Mar 15 12:57:54 GMT 2004 collect_sys_info: boot eax = 0xe1fb007 collect_sys_info: boot ebx = 0x3fb9df4 collect_sys_info: boot arg = 0x3fb9df4 malloc_diag: alloc: 0 bytes (0 blocks), free: 16376 bytes (1 blocks) malloc_diag: alloc: 24 bytes (1 blocks), free: 16352 bytes (1 blocks) collect_elfboot_info: Bootloader: elfboot collect_elfboot_info: Version: 1.2 malloc_diag: alloc: 40 bytes (2 blocks), free: 16336 bytes (1 blocks) collect_linuxbios_info: Searching for LinuxBIOS tables... find_lb_table: Found canidate at: 00000500 find_lb_table: header checksum o.k. find_lb_table: table checksum o.k. find_lb_table: record count o.k. collect_linuxbios_info: Found LinuxBIOS table at: 00000500 malloc_diag: alloc: 128 bytes (3 blocks), free: 16248 bytes (1 blocks) convert_memmap: 0x00000000000000 0x00000000000700 16 convert_memmap: 0x00000000000700 0x0000000009f900 1 convert_memmap: 0x000000000c0000 0x00000000030000 1 convert_memmap: 0x000000000f0000 0x00000000000400 16 convert_memmap: 0x000000000f0400 0x00000003f0fc00 1 collect_sys_info: 0000000000000700-00000000000a0000 collect_sys_info: 00000000000c0000-00000000000f0000 collect_sys_info: 00000000000f0400-0000000004000000 collect_sys_info: RAM 64 MB relocate: Current location: 0x100000-0x125f67 relocate: Relocating to 0x3fda090-0x3fffff7... ok setup_timers: CPU 533 MHz pci_init: Scanning PCI: found 10 devices malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks) pci_init: 00:00.0 1106:0601 0600 00 pci_init: 00:01.0 1106:8601 0604 00 pci_init: 00:11.0 1106:8231 0601 00 pci_init: 00:11.1 1106:0571 0101 8a pci_init: 00:11.2 1106:3038 0c03 00 pci_init: 00:11.3 1106:3038 0c03 00 pci_init: 00:11.4 1106:8235 0000 00 pci_init: 00:11.5 1106:3058 0401 00 pci_init: 00:11.6 1106:3068 0780 00 pci_init: 00:12.0 1106:3065 0200 00 Press <Enter> for default boot, or <Esc> for boot prompt... timed out boot: hda1:/boot/rolecsplash console=tty0 console=ttyS0,115200 malloc_diag: alloc: 328 bytes (5 blocks), free: 16048 bytes (1 blocks) malloc_diag: alloc: 344 bytes (6 blocks), free: 16032 bytes (1 blocks) file_open: dev=hda1, path=/boot/rolecsplash find_ide_controller: found PCI IDE controller 1106:0571 prog_if=0x8a find_ide_controller: primary channel: compatibility mode find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4 ide_software_reset: Waiting for ide0 to become ready for reset... ok init_drive: Testing for hda init_drive: Probing for hda init_drive: LBA mode, sectors=39102336 init_drive: Init device params... ok hda: LBA 20GB: ST320014A devopen: Partition 1 start 32 length 3127264 Mounted ext2fs malloc_diag: alloc: 328 bytes (5 blocks), free: 16048 bytes (1 blocks) elf_load: Not a bootable ELF image malloc_diag: alloc: 344 bytes (6 blocks), free: 16032 bytes (1 blocks) file_open: dev=hda1, path=/boot/rolecsplash devopen: already open malloc_diag: alloc: 328 bytes (5 blocks), free: 16048 bytes (1 blocks) Found Linux version 2.4.24splash (root@rolec) #5 Thu Jan 15 12:13:33 GMT 2004 (protocol 0x203) (loadflags 0x1) bzImage. init_linux_params: Setting up paramters at 0x90000 set_memory_size: 0000000000000700 - 00000000000a0000 set_memory_size: 00000000000c0000 - 00000000000f0000 set_memory_size: 00000000000f0400 - 0000000004000000 set_memory_size: ramtop=0x4000000 set_memory_size: ext_mem_k=64512, alt_mem_k=64512 parse_command_line: original command line: "console=tty0 console=ttyS0,115200" parse_command_line: kernel command line at 0x91000 parse_command_line: kernel command line (33 bytes): "console=tty0 console=ttyS0,115200" load_linux_kernel: offset=0x1600 addr=0x100000 size=0xe667d Loading kernel... ok start_linux: eip=0x100000 Jumping to entry point...

3 3

Re: OEM looking at LinuxBIOS
by ebiederman＠lnxi.com 14 Mar '04

14 Mar '04

"Anthony Winner" <awinner(a)walkabout-comp.com> writes: > Eric, > > Thanks, will start with the freebios2 tree. Which of the howto's is a good > 'from scratch' roadmap to get me started.... I really don't know the state of the howto's at this point. Generally good advice is to examine another port that is similar. Eric > Anthony Winner > WalkAbout Computers > awinner(a)walkabout-comp.com > (561)712-1200 x221 > > > -----Original Message----- > From: linuxbios-admin(a)clustermatic.org > [mailto:linuxbios-admin@clustermatic.org]On Behalf Of Eric W. Biederman > Sent: Thursday, March 11, 2004 11:06 AM > To: Hendricks David W. > Cc: Anthony Winner; linuxbios(a)clustermatic.org > Subject: Re: OEM looking at LinuxBIOS > > > "Hendricks David W." <dwh(a)lanl.gov> writes: > > > There is already 82803 and 82801ca code in the freebios1 tree, might as > > well put it to good use :) I think Eric Beiderman was even able to fix > > SPD, at least on the MCH4 (Or something). > > > > On Tue, 9 Mar 2004, Anthony Winner wrote: > > > > > Hello all, > > > > > > I work for a OEM and I'm playing with the idea of using linuxBIOS, I > have > > > all of the technical info for the machine short of the actual source > code to > > > the Phoenix BIOS we use now as it was done by a contractor before I > joined > > > the company. > > > > > > Are there any pointers for a 'from scratch', implementation? > > > > > > Should I start with the old code or start fresh from the new freebios2 > tree? > > > > > > For reference, the machine is a Intel PIII with a 82830 Northbridge, a > > > 82801ca Southbridge, TI pci1450 card bus controller, and a pair of SMC > SIO > > > chips.... > > I don't think we have good support for th 82830 at this time so the > freebios2 > tree would be the one to work with. You get romcc so you can code the > memory initialization in C. If you know what you are doing a huge chunk of > assembly is tolerable. But doing things in C prevents a lot of stupid > typos. > > I just looked the code in the freebios1 tree for the 82830 does not even > attempt to do SPD based memory initialization so it will not work with > arbitrary memory. So definitely freebios2 using some of the freebios1 > code as reference. > > I don't think the freebios1 tree can code with a pair of superio chips > either. > > The freebios2 tree comes with multiple devices of the same type trivially. > > Eric > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios

3 2

BCC...
by ebiederman＠lnxi.com 13 Mar '04

13 Mar '04

The PCBIOS compatibility code in rombios.c has quite a few warts. Primary among them is that it written in a nasty mix of asm and 16bit C code. With the biggest problem seeming to be that bcc is a limited 16bit compiler. In real mode there is 256K that we can place a real mode BIOS in. If all we do is stick to what a PCBIOS can do now, and don't attempt to extend it, but just be a good implementation 256K should be enough to do whatever is needed. I don't know if gcc using 32bit overrides in 16bit mode would be better than a pure 16bit C compiler. Just looking at rombios.c earlier today the worst of it appears to be that rombios.c is a nasty mess, and that rombios.c does not support pci. So most of it to me does not appear to be a compiler issue at all, just that rombios.c needs to be rewritten in a more maintainable style. I need to look a little more closely but I suspect getting bcc to accept a fairly complete gcc syntax including inline asm support would not be hard. Nor do I think getting bcc to output to gas assembly instead of it's own assembler would be to bad. Except possibly that gas 16bit support is quite limited. So if the issues keeping us from using 16bit C compiler are primarily cosmetic I don't see why they can't be fixed. Long term I don't even want to touch a compatibility layer. I want to use something much simpler and much more powerful. Eric

3 6

re: Tyan Changes for 1.1.6
by YhLu 12 Mar '04

12 Mar '04

Eric, It seems all the pnp_device init are not called. Regards YH. Finding PCI configuration type. PCI: Using configuration type 1 Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Northbridge Enumerating: AMD K8 Enumerating: AMD K8 Enumerating: AMD 8111 Enumerating: Winbond w83627hf Enumerating buses...PCI: pci_scan_bus for bus 0 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled amdk8_scan_chains max: 0 starting... Hyper transport scan link: 0 max: 1 PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 HyperT reset not needed PCI: pci_scan_bus for bus 1 PCI: 01:01.0 [1022/7450] bus ops PCI: 01:01.0 [1022/7450] enabled PCI: 01:01.1 [1022/7451] ops PCI: 01:01.1 [1022/7451] enabled PCI: 01:02.0 [1022/7450] bus ops PCI: 01:02.0 [1022/7450] enabled PCI: 01:02.1 [1022/7451] ops PCI: 01:02.1 [1022/7451] enabled PCI: 01:03.0 [1022/7460] bus ops PCI: 01:03.0 [1022/7460] enabled PCI: 01:04.0 [1022/7468] bus ops PCI: 01:04.0 [1022/7468] enabled PCI: 01:04.1 [1022/7469] ops PCI: 01:04.1 [1022/7469] enabled PCI: 01:04.2 [1022/746a] enabled PCI: 01:04.3 [1022/746b] ops PCI: 01:04.3 [1022/746b] enabled PCI: 01:04.5 [1022/746d] ops PCI: 01:04.5 [1022/746d] disabled PCI: 01:04.6 [1022/746e] ops PCI: 01:04.6 [1022/746e] disabled PCI: pci_scan_bus for bus 2 PCI: 02:06.0 [9005/801f] enabled PCI: 02:06.1 [9005/801f] enabled PCI: 02:09.0 [14e4/16a7] enabled PCI: 02:09.1 [14e4/16a7] enabled PCI: pci_scan_bus returning with max=02 PCI: pci_scan_bus for bus 3 PCI: pci_scan_bus returning with max=03 PCI: pci_scan_bus for bus 4 PCI: 04:00.0 [1022/7464] ops PCI: 04:00.0 [1022/7464] enabled PCI: 04:00.1 [1022/7464] ops PCI: 04:00.1 [1022/7464] enabled PCI: 04:00.2 [1022/7463] ops PCI: 04:00.2 [1022/7463] enabled PCI: 04:01.0 [1022/7462] ops PCI: 04:01.0 [1022/7462] disabled PCI: 04:06.0 [1002/4752] enabled PCI: pci_scan_bus returning with max=04 PNP: 002e.0 disabled PNP: 002e.1 disabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.5 enabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled PNP: 002e.b disabled PCI: pci_scan_bus returning with max=04 Hyper transport scan link: 0 new max: 4 Hypertransport scan link done amdk8_scan_chains max: 4 done amdk8_scan_chains max: 4 starting... amdk8_scan_chains max: 4 done PCI: pci_scan_bus returning with max=04 done Allocating resources... PNP: 002e.8 missing read_resources PNP: 002e.9 missing read_resources Allocating VGA resource ASSIGN RESOURCES, bus 0 PCI: 00:18.0 c0 <- [0x00001000 - 0x00003fff] node 0 link 0 io PCI: 00:18.0 b8 <- [0xfc000000 - 0xfd2fffff] node 0 link 0 mem ASSIGN RESOURCES, bus 1 PCI: 01:01.0 1c <- [0x00001000 - 0x00001fff] bus 2 io PCI: 01:01.0 24 <- [0xfd200000 - 0xfd1fffff] bus 2 prefmem PCI: 01:01.0 20 <- [0xfd100000 - 0xfd1fffff] bus 2 mem ASSIGN RESOURCES, bus 2 PCI: 02:06.0 10 <- [0x00001000 - 0x000010ff] io PCI: 02:06.0 14 <- [0xfd140000 - 0xfd141fff] mem PCI: 02:06.0 1c <- [0x00001400 - 0x000014ff] io PCI: 02:06.1 10 <- [0x00001800 - 0x000018ff] io PCI: 02:06.1 14 <- [0xfd142000 - 0xfd143fff] mem PCI: 02:06.1 1c <- [0x00001c00 - 0x00001cff] io PCI: 02:09.0 10 <- [0xfd100000 - 0xfd10ffff] mem PCI: 02:09.0 18 <- [0xfd110000 - 0xfd11ffff] mem PCI: 02:09.1 10 <- [0xfd120000 - 0xfd12ffff] mem PCI: 02:09.1 18 <- [0xfd130000 - 0xfd13ffff] mem ASSIGNED RESOURCES, bus 2 PCI: 01:01.1 10 <- [0xfd200000 - 0xfd200fff] mem PCI: 01:02.0 1c <- [0x00003000 - 0x00002fff] bus 3 io PCI: 01:02.0 24 <- [0xfd200000 - 0xfd1fffff] bus 3 prefmem PCI: 01:02.0 20 <- [0xfd200000 - 0xfd1fffff] bus 3 mem PCI: 01:02.1 10 <- [0xfd201000 - 0xfd201fff] mem PCI: 01:03.0 1c <- [0x00002000 - 0x00002fff] bus 4 io PCI: 01:03.0 24 <- [0xfd200000 - 0xfd1fffff] bus 4 prefmem PCI: 01:03.0 20 <- [0xfc000000 - 0xfd0fffff] bus 4 mem ASSIGN RESOURCES, bus 4 PCI: 04:00.0 10 <- [0xfd000000 - 0xfd000fff] mem PCI: 04:00.1 10 <- [0xfd001000 - 0xfd001fff] mem PCI: 04:00.2 10 <- [0xfd003000 - 0xfd0030ff] mem PCI: 04:00.2 14 <- [0xfd004000 - 0xfd00401f] mem PCI: 04:06.0 10 <- [0xfc000000 - 0xfcffffff] mem PCI: 04:06.0 14 <- [0x00002000 - 0x000020ff] io PCI: 04:06.0 18 <- [0xfd002000 - 0xfd002fff] mem ASSIGNED RESOURCES, bus 4 PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] io PCI: 01:04.0 00 <- [0x00000000 - 0xffffffff] mem ASSIGN RESOURCES, bus 0 PNP: 002e.2 60 <- [0x000003f8 - 0x000003ff] io PNP: 002e.2 70 <- [0x00000004 - 0x00000004] irq PNP: 002e.5 60 <- [0x00000060 - 0x00000060] io PNP: 002e.5 62 <- [0x00000064 - 0x00000064] io PNP: 002e.5 70 <- [0x00000001 - 0x00000001] irq PNP: 002e.5 72 <- [0x0000000c - 0x0000000c] irq PNP: 002e.8 missing set_resources PNP: 002e.9 missing set_resources ASSIGNED RESOURCES, bus 0 PCI: 01:04.1 20 <- [0x00003420 - 0x0000342f] io PCI: 01:04.2 10 <- [0x00003400 - 0x0000341f] io PCI: 01:04.3 58 <- [0x00003000 - 0x000030ff] io ASSIGNED RESOURCES, bus 1 PCI: 00:18.3 94 <- [0xf8000000 - 0xfbffffff] mem <gart> PCI: 00:19.3 94 <- [0xf8000000 - 0xfbffffff] mem <gart> ASSIGNED RESOURCES, bus 0 done. Enabling resourcess... PCI: 00:18.0 cmd <- 140 PCI: 01:01.0 bridge ctrl <- 0003 PCI: 01:01.0 cmd <- 147 PCI: 02:06.0 cmd <- 143 PCI: 02:06.1 cmd <- 143 PCI: 02:09.0 cmd <- 142 PCI: 02:09.1 cmd <- 142 PCI: 01:01.1 cmd <- 146 PCI: 01:02.0 bridge ctrl <- 0003 PCI: 01:02.0 cmd <- 147 PCI: 01:02.1 cmd <- 146 PCI: 01:03.0 bridge ctrl <- 000b PCI: 01:03.0 cmd <- 147 PCI: 04:00.0 cmd <- 142 PCI: 04:00.1 cmd <- 142 PCI: 04:00.2 cmd <- 142 PCI: 04:06.0 cmd <- 1c3 PCI: 01:04.0 cmd <- 14f PNP: 002e.8 missing enable_resources PNP: 002e.9 missing enable_resources PCI: 01:04.1 cmd <- 141 PCI: 01:04.2 cmd <- 141 PCI: 01:04.3 cmd <- 141 PCI: 00:18.1 cmd <- 140 PCI: 00:18.2 cmd <- 140 PCI: 00:18.3 cmd <- 140 PCI: 00:19.0 cmd <- 140 PCI: 00:19.1 cmd <- 140 PCI: 00:19.2 cmd <- 140 PCI: 00:19.3 cmd <- 140 done. Initializing devices... PCI: 00:18.0 init NB: Function 0 Misc Control.. done. PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:19.0 init NB: Function 0 Misc Control.. done. PCI: 00:19.3 init NB: Function 3 Misc Control.. done. PCI: 01:01.0 init PCI: 01:02.0 init PCI: 01:03.0 init PCI: 01:04.0 init RTC Init enabling HPET @0xfed00000 PCI: 01:04.1 init IDE1 IDE0 PCI: 01:04.3 init set power on after power fail PCI: 04:00.0 init PCI: 04:00.1 init PCI: 04:00.2 init Devices initialized

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[Fwd: Re: Asus Cusi-FX]
by Bari Ari 12 Mar '04

12 Mar '04

-------- Original Message -------- Subject: Re: Asus Cusi-FX Date: Sat, 13 Mar 2004 01:28:11 +0100 From: Christian Gmeiner <christian(a)visual-page.de> To: Bari Ari <bari(a)onelabs.com> References: <001f01c4088f$568a3460$0600a8c0@blackbox> <40525471.5020704(a)onelabs.com> > Christian Gmeiner wrote: > > > Hi Mailinglist. > > > > I find the project very good and it could speed up the starting of my > > Video Disc Recorder - VDR - dramaticly. > > But before i spend money i want to know, if the ASUS Cusi-Fx Mainboard > > is supported. > > Send LSPCI. vdr root # lspci 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 630 Host (rev 21) 00:00.1 IDE interface: Silicon Integrated Systems [SiS] 5513 [IDE] (rev d0) 00:01.0 ISA bridge: Silicon Integrated Systems [SiS] 85C503/5513 00:01.1 Ethernet controller: Silicon Integrated Systems [SiS] SiS900 10/100 Ethernet (rev 83) 00:01.2 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 07) 00:01.3 USB Controller: Silicon Integrated Systems [SiS] USB 1.0 Controller (rev 07) 00:02.0 PCI bridge: Silicon Integrated Systems [SiS] SiS 530 Virtual PCI-to-PCI bridge (AGP) 00:0d.0 Multimedia controller: Sigma Designs, Inc. REALmagic Hollywood Plus DVD Decoder (rev 02) 00:0e.0 Multimedia controller: Philips Semiconductors SAA7146 (rev 01) 01:00.0 VGA compatible controller: Silicon Integrated Systems [SiS] SiS630 GUI Accelerator+3D (rev 21) Greets, Christian

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答复: 答复: Tyan Changes for 1.1.6
by YhLu 12 Mar '04

12 Mar '04

Increase heap size will make it work. -----邮件原件----- 发件人: YhLu 发送时间: 2004年3月12日 15:15 收件人: Hendricks David W.; ron minnich 抄送: Eric W. Biederman; 'linuxbios(a)clustermatic.org' 主题: 答复: 答复: Tyan Changes for 1.1.6 With 1.1.5 is OK, but failed with 1.1.6. -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月12日 11:06 收件人: ron minnich 抄送: Eric W. Biederman; YhLu; 'linuxbios(a)clustermatic.org' 主题: Re: 答复: Tyan Changes for 1.1.6 Oh yeah, I've been using 2.6.3 on the S2885 for a while now. The AGPGART driver has an issue that requires it to be compiled statically into the kernel, so that sort of breaks functionality of your FIXGART script that does the magic with IORRs and such. I'll attach my .config, tested on the S2885, in case others want to skip through the configuration process with a 'make oldconfig.' On Fri, 12 Mar 2004, ron minnich wrote: > On 12 Mar 2004, Eric W. Biederman wrote: > > > 2.6 is fun because the option names have changed, so it is easy > > to leave things like serial console disabled. > > > > I think David Hendricks tried this. David? > ron > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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答复: 答复: Tyan Changes for 1.1.6
by YhLu 12 Mar '04

12 Mar '04

With 1.1.5 is OK, but failed with 1.1.6. -----邮件原件----- 发件人: Hendricks David W. [mailto:dwh@lanl.gov] 发送时间: 2004年3月12日 11:06 收件人: ron minnich 抄送: Eric W. Biederman; YhLu; 'linuxbios(a)clustermatic.org' 主题: Re: 答复: Tyan Changes for 1.1.6 Oh yeah, I've been using 2.6.3 on the S2885 for a while now. The AGPGART driver has an issue that requires it to be compiled statically into the kernel, so that sort of breaks functionality of your FIXGART script that does the magic with IORRs and such. I'll attach my .config, tested on the S2885, in case others want to skip through the configuration process with a 'make oldconfig.' On Fri, 12 Mar 2004, ron minnich wrote: > On 12 Mar 2004, Eric W. Biederman wrote: > > > 2.6 is fun because the option names have changed, so it is easy > > to leave things like serial console disabled. > > > > I think David Hendricks tried this. David? > ron > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: 答复: 答复: S2885 failing on 1.1.6
by YhLu 12 Mar '04

12 Mar '04

After the ht-scan in devices/hypertransport.c, Ams8131/amd8111 will be in bus 3. bus 1 will be used by 8151. YH. -----邮件原件----- 发件人: YhLu 发送时间: 2004年3月12日 14:44 收件人: 'Li-Ta Lo' 抄送: ron minnich; Eric W. Biederman; LinuxBIOS 主题: 答复: 答复: 答复: S2885 failing on 1.1.6 Maybe after the ht-scan in auto.c Amd8131 and amd8111 is in bus 1. and bus 0 is used by 8151. YH -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月12日 14:41 收件人: YhLu 抄送: ron minnich; Eric W. Biederman; LinuxBIOS 主题: Re: 答复: 答复: S2885 failing on 1.1.6 On Fri, 2004-03-12 at 15:45, YhLu wrote: > 0 should be bus. > Then why change it to bus 1 fix the problem ? Ollie

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答复: 答复: 答复: S2885 failing on 1.1.6
by YhLu 12 Mar '04

12 Mar '04

Maybe after the ht-scan in auto.c Amd8131 and amd8111 is in bus 1. and bus 0 is used by 8151. YH -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月12日 14:41 收件人: YhLu 抄送: ron minnich; Eric W. Biederman; LinuxBIOS 主题: Re: 答复: 答复: S2885 failing on 1.1.6 On Fri, 2004-03-12 at 15:45, YhLu wrote: > 0 should be bus. > Then why change it to bus 1 fix the problem ? Ollie

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coreboot March 2004