coreboot March 2004

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LinuxBIOS Featured on Slashdot Yet Again
by Bari Ari 24 Mar '04

24 Mar '04

LinuxBIOS featured on Slashdot yet again this evening: http://developers.slashdot.org/developers/04/03/24/2327229.shtml -Bari

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EPIA "always-on" system
by Joshua Wise 24 Mar '04

24 Mar '04

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, I am considering building a "backpack computer" that does MP3 playing, etcetera... I was planning on using the EPIA because LinuxBIOS supports it. Is the EPIA in a state right now where it would be usable for such activity? Thanks, joshua - -- Joshua Wise | www.joshuawise.com GPG Key | 0xEA80E0B3 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.2 (GNU/Linux) iD8DBQFAYlNvPn9tWOqA4LMRAi44AJ9yBjGNJXLfDOrOAZmQcdbGGOuwEgCdGwjG Jskcoo0MCSpABsxHvgA9ArE= =Xjf2 -----END PGP SIGNATURE-----

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答复: S4882 support
by YhLu 24 Mar '04

24 Mar '04

It is in 00:4.0 Even you are using 0x80, you got the same result, because auto.c only use that optimize link speed/width, and 8131 and 8151 has the same speed/cap. At this time, ht_setup_chain only can scan one ht-chain. If want to optimize link to 8151, need to move code from northbridge.c to init 0xe0.... to assign unitid to 8151. Regards YH. -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月24日 14:08 收件人: YhLu 抄送: Stefan Reinauer; ebiederman(a)lnxi.com; ron minnich; LinuxBIOS 主题: Re: S4882 support On Wed, 2004-03-24 at 14:54, YhLu wrote: > That is up to scan sequence. In S2885, CPU0 link0 is linked AMD8151, and > link2 is connected to ADM8131. > > If scan from link 0, bus 1 will be used by AMD851 AGP device and bridge, and > bus 2 will be used by AGP adapter. > > So amd8131/amd111 will start from bus 3. > > I will check that in S2885 if it is in 1:4.0 > And it is never bus 1, right ? Why I have to access it on bus 1 ? Doesn't it go to the AGP bridge ? Ollie

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Re: S4882 support
by YhLu 24 Mar '04

24 Mar '04

That is up to scan sequence. In S2885, CPU0 link0 is linked AMD8151, and link2 is connected to ADM8131. If scan from link 0, bus 1 will be used by AMD851 AGP device and bridge, and bus 2 will be used by AGP adapter. So amd8131/amd111 will start from bus 3. I will check that in S2885 if it is in 1:4.0 Regards YH -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2004年3月24日 13:25 收件人: Li-Ta Lo 抄送: YhLu; ebiederman(a)lnxi.com; ron minnich; LinuxBIOS 主题: Re: ??????: ??????: S4882 support * Li-Ta Lo <ollie(a)lanl.gov> [040324 21:37]: > That why I don't understand of this magic. In the log, LPC was 0:4.0 and > than changed to 3:4.0 and it's never 1:4.0. But I have to change the > reset code to 1:4.0. Commercial bioses have it easy.. for some reason they always map that device on 0:7.0. It looks less elegant, but it does a cheap job. Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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答复: 答复: ????: coherent_ht_mainboard()
by YhLu 24 Mar '04

24 Mar '04

Eric, CPU0 Link0 is connected to CPU1, and CPU0 Link1 is connected to amd8131. Before needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); The link is 16x800, After that it change to 16x600, What's the 0x80 for? Do need to change that 0xa0, because CPU0 link1 is to amd8131. Regards YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年3月24日 11:28 收件人: YhLu 抄送: Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: 答复: ????: coherent_ht_mainboard() YhLu <YhLu(a)tyan.com> writes: > The optimize_link make > The link CPU0 to CPU1: in CPU0 side(link0) is 16x800 and CPU1 side(link0) > is 16x800 I don't know if 1Ghz is actually supported between cpus. AMD never mentions it, at least I had not seen that it was supported when I wrote that code. So I erred on the side of caution and limited things to what is documented as supported. > but the scan_ht_chain change CPU0 side(link0) is 16x600 An 8131 does not operate reliably at over 600Mhz. Read the errata. The 8131 does advertise that it can go at 800Mhz though. > it must think it is connected to 8111 or something. I believe these cap come from ht_read_freq_cap. And they are explicitly set: Here is the general version in devices/hypertransport.c. The amdk8 versions are a little more abbreviated. static unsigned ht_read_freq_cap(device_t dev, unsigned pos) { /* Handle bugs in valid hypertransport frequency reporting */ unsigned freq_cap; freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ /* AMD 8131 Errata 48 */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) { freq_cap &= ~(1 << HT_FREQ_800Mhz); } /* AMD 8151 Errata 23 */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) { freq_cap &= ~(1 << HT_FREQ_800Mhz); } /* AMD K8 Unsupported 1Ghz? */ if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) { freq_cap &= ~(1 << HT_FREQ_1000Mhz); } return freq_cap; } I hope this helps, Eric

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答复: 答复: S4882 support
by YhLu 24 Mar '04

24 Mar '04

There is some dump_pci_devices in auto.c of s2885, you can enable that to see if amd8111 LPC is 1:4.0 Regards YH -----邮件原件----- 发件人: Li-Ta Lo [mailto:ollie@lanl.gov] 发送时间: 2004年3月24日 8:05 收件人: YhLu 抄送: ebiederman(a)lnxi.com; Stefan Reinauer; ron minnich; LinuxBIOS 主题: Re: 答复: S4882 support On Tue, 2004-03-23 at 20:57, YhLu wrote: > It seems the soft reset didn't rest the MB and ... > > Ollie, > > Can you check that in S2885? And I think if you changed the hard_reset and > soft_reset to bus 1, it may not rest the ht. > What ?? I have to change it to bus 1 to make the reset work on S2885. Ollie > Regards > > Yinghai Lu > > -----邮件原件----- > 发件人: YhLu > 发送时间: 2004年3月23日 19:22 > 收件人: ebiederman(a)lnxi.com; Stefan Reinauer; ron minnich > 抄送: linuxbios(a)clustermatic.org > 主题: S4882 support > > Eric, > > The ht reset in auto.c seems not thoroughly. > > And it will stuck at hard_reset in amdk8_scan_chains. ( at this time can not > access 8111 yet). > > Regards > > YH > > LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:33:50 PST 2004 starting... > setting up resource map....done. > 04 nodes initialized. > ht reset -Ram1.00 > XÀm1.01 > Ram1.02 > Ram1.03 > Ram2.00 > Ram2.01 > Ram2.02 > Ram2.03 > Ram3 > Initializing memory: done > Initializing memory: done > Initializing memory: done > Initializing memory: done > Clearing LinuxBIOS memory: done > Ram4 > Copying LinuxBIOS to ram. > Jumping to LinuxBIOS. > LinuxBIOS-1.1.62.0_Normal Tue Mar 23 17:46:40 PST 2004 booting... > Finding PCI configuration type. > PCI: Using configuration type 1 > Enumerating: AMD K8 Northbridge > Enumerating: AMD K8 Northbridge > Enumerating: AMD K8 Northbridge > Enumerating: AMD K8 Northbridge > Enumerating: AMD K8 > Enumerating: AMD K8 > Enumerating: AMD K8 > Enumerating: AMD K8 > Enumerating: AMD 8111 > Enumerating: Winbond w83627hf > Enumerating buses...PCI: pci_scan_bus for bus 0 > PCI: 00:18.0 [1022/1100] enabled > PCI: 00:18.1 [1022/1101] enabled > PCI: 00:18.2 [1022/1102] enabled > PCI: 00:18.3 [1022/1103] ops > PCI: 00:18.3 [1022/1103] enabled > PCI: 00:19.0 [1022/1100] enabled > PCI: 00:19.1 [1022/1101] enabled > PCI: 00:19.2 [1022/1102] enabled > PCI: 00:19.3 [1022/1103] ops > PCI: 00:19.3 [1022/1103] enabled > PCI: 00:1a.0 [1022/1100] enabled > PCI: 00:1a.1 [1022/1101] enabled > PCI: 00:1a.2 [1022/1102] enabled > PCI: 00:1a.3 [1022/1103] ops > PCI: 00:1a.3 [1022/1103] enabled > PCI: 00:1b.0 [1022/1100] enabled > PCI: 00:1b.1 [1022/1101] enabled > PCI: 00:1b.2 [1022/1102] enabled > PCI: 00:1b.3 [1022/1103] ops > PCI: 00:1b.3 [1022/1103] enabled > amdk8_scan_chains max: 0 starting... > Hyper transport scan link: 1 max: 1 > PCI: 01:01.0 [1022/7450] enabled next_unitid: 0003 > PCI: 01:03.0 [1022/7460] enabled next_unitid: 0007 > HyperT reset needed > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios >

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答复: ????: coherent_ht_mainboard()
by YhLu 24 Mar '04

24 Mar '04

The optimize_link make The link CPU0 to CPU1: in CPU0 side(link0) is 16x800 and CPU1 side(link0) is 16x800 but the scan_ht_chain change CPU0 side(link0) is 16x600 it must think it is connected to 8111 or something. YH. -----邮件原件----- 发件人: YhLu 发送时间: 2004年3月24日 9:56 收件人: Stefan Reinauer 抄送: linuxbios(a)clustermatic.org 主题: 答复: ????: coherent_ht_mainboard() The CPU0->AMD8131->AMD8111 is right. The link CPU0 to CPU1: in CPU0 side(link0) is 16x600 and CPU1 side(link0) is 16x800 All others is 8x200. The coherent should be all 16x1000 I will try your patch and dig it out. Regards YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2004年3月24日 9:37 收件人: YhLu 抄送: linuxbios(a)clustermatic.org 主题: Re: ????: coherent_ht_mainboard() * YhLu <YhLu(a)tyan.com> [040324 18:39]: > The dynamic code does not work on 4 way MB, I have found out why the s4882 > can not soft_reset. > > The HT-link between is not properly init properly. Which link is this? CPU0->AMD8111? I seemed to have no problems on quartet with 1.1.5, which is 4 way as well. Have you been able to track the problem down to a certain function/flaw? > If the dynamic code can init the coherent-ht properly, We can remove > hypertransport.c good. Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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答复: 答复: ????: coherent_ht_mainboard()
by YhLu 24 Mar '04

24 Mar '04

In the normal BIOS, We are using 16x1000 YH -----邮件原件----- 发件人: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] 发送时间: 2004年3月24日 11:20 收件人: YhLu 抄送: Stefan Reinauer; linuxbios(a)clustermatic.org 主题: Re: 答复: ????: coherent_ht_mainboard() YhLu <YhLu(a)tyan.com> writes: > The CPU0->AMD8131->AMD8111 is right. > > The link CPU0 to CPU1: in CPU0 side(link0) is 16x600 and CPU1 side(link0) > is 16x800 > > All others is 8x200. > > The coherent should be all 16x1000 Does AMD really support 1Ghz Operation between CPUs? If so I am fine with this. Otherwise I have not seen any significant benchmarking differences so I would mask out the 1Ghz capability... Eric

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答复: ????: coherent_ht_mainboard()
by YhLu 24 Mar '04

24 Mar '04

The CPU0->AMD8131->AMD8111 is right. The link CPU0 to CPU1: in CPU0 side(link0) is 16x600 and CPU1 side(link0) is 16x800 All others is 8x200. The coherent should be all 16x1000 I will try your patch and dig it out. Regards YH. -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2004年3月24日 9:37 收件人: YhLu 抄送: linuxbios(a)clustermatic.org 主题: Re: ????: coherent_ht_mainboard() * YhLu <YhLu(a)tyan.com> [040324 18:39]: > The dynamic code does not work on 4 way MB, I have found out why the s4882 > can not soft_reset. > > The HT-link between is not properly init properly. Which link is this? CPU0->AMD8111? I seemed to have no problems on quartet with 1.1.5, which is 4 way as well. Have you been able to track the problem down to a certain function/flaw? > If the dynamic code can init the coherent-ht properly, We can remove > hypertransport.c good. Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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答复: coherent_ht_mainboard()
by YhLu 24 Mar '04

24 Mar '04

The dynamic code does not work on 4 way MB, I have found out why the s4882 can not soft_reset. The HT-link between is not properly init properly. If the dynamic code can init the coherent-ht properly, We can remove hypertransport.c Regards YH -----邮件原件----- 发件人: Stefan Reinauer [mailto:stepan@suse.de] 发送时间: 2004年3月24日 8:41 收件人: YhLu 抄送: linuxbios(a)clustermatic.org 主题: coherent_ht_mainboard() Yinghai, tyan/*/hypertransport.c contain some fixed hypertransport register values poked into the AMD K8 northbridge. This code was earlier called by coherent_ht.c:setup_coherent_ht_domain() but I removed the call some time ago, since I could not see why it is still needed. Does this code provide any crucial functionality that can't be realized in the dynamic code of the current CVS tree? If not, I suggest we drop this code. The same thing could btw work for the different versions of resourcemap.c. The biggest reason for the split off here was that the default resource map did always assume the AMD8111 southbridge on link0 which is not always true. This is fixed by now. The bus numbers should meanwhile be entered correctly by the generic code. So, we could reduce the amount of involved code a lot, flattening out all the nasty exceptions we invented to bend the rules.. Stefan -- Stefan Reinauer, SUSE LINUX AG Head of Architecture Development

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coreboot March 2004