coreboot November 2004

coreboot@coreboot.org

31 participants
183 discussions

mtrr
by YhLu 11 Nov '04

11 Nov '04

I just found the mtrr after booting is not right. ~ # cat /proc/mtrr reg00: base=0x00000000 ( 0MB), size=985088MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=984064MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=983296MB: write-back, count=1 and it should be reg00: base=0x00000000 ( 0MB), size=2048MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=1024MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=256MB: write-back, count=1 and it is has 98340MB more = 0xf0 0000 0000. Regards YH

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RE: autobuild statistics
by YhLu 11 Nov '04

11 Nov '04

Someone (who recent format the coherent_ht.c) need to static void fill_row(u8 node, u8 row, u32 value) { pci_write_config32(NODE_HT(node), 0x40+(row<<2), value); } Before #if CONFIG_MAX_CPUS > 1 to support ONE AMD K8 YH -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Thursday, November 11, 2004 1:11 PM To: linuxbios(a)clustermatic.org Subject: autobuild statistics Hi, The abuild script checks for new checkins now every 4h and logs are placed at: http://snapshots.linuxbios.org/stats/ BTW, the latest changes made things a little more dramatic again. In size, compile time and compile success. Stefan _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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RE: Tyan/s2735
by YhLu 11 Nov '04

11 Nov '04

YES -----Original Message----- From: Gin [mailto:ginlin@nexcom.com.tw] Sent: Wednesday, November 10, 2004 11:03 PM To: 'Steven James' Cc: linuxbios(a)clustermatic.org Subject: Tyan/s2735 Steven, Thanks for the info. I've got the ram up by filling the some values in North Bridge(I reference a regular bios). I have an essential question about the code base for Tyan/s2735. Has it ever successfully built and run on that board? I have to make sure the code I am currently building our board on is good. Thanks -----Original Message----- From: linuxbios-admin(a)clustermatic.org [mailto:linuxbios-admin@clustermatic.org] On Behalf Of Steven James Sent: Friday, November 05, 2004 10:40 PM To: Gin Lin Cc: linuxbios(a)clustermatic.org Subject: Re: ram init Greetings, It's been a while since I've looked at it, but when I last looked, it did sometimes need power cycled to restart. I worked around that by making the kernel reboot by writing 0x0e to port 0xcf9. That causes the southbridge to do a 3 second power off. G'day, sjames On Fri, 5 Nov 2004, Gin Lin wrote: > Does anyone know if the raminit.c under intel/E7501 is stable enough? I am > having a problem with the system reseting when it jumps to the first address > in the ram. Could the procedures of writing NorthBrige registers have > problems? > > thanks, > Gin > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > ||||| |||| ||||||||||||| ||| by Linux Labs International, Inc. Steven James, CTO 55 Marietta Street Suite 1830 Atlanta, Ga 30303 866 824 9737 support _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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minor changes
by Ronald G. Minnich 11 Nov '04

11 Nov '04

in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it. Set adl855pc ROM_SIZE to 1M Other minor debug prints until we get this fixed. We're almost as far along as we were before the Change :-) CVS: ---------------------------------------------------------------------- CVS: Enter Log. Lines beginning with `CVS:' are removed automatically CVS: CVS: Committing in . CVS: CVS: Modified Files: CVS: include/console/loglevel.h CVS: mainboard/digitallogic/adl855pc/Options.lb CVS: mainboard/digitallogic/adl855pc/auto.c CVS: northbridge/intel/i855pm/raminit.c CVS: southbridge/intel/i82801dbm/i82801dbm_early_smbus.c CVS: ----------------------------------------------------------------------

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[Davide <louigi600@yahoo.it>] Freebios and unsupported hardware ?
by ebiederman＠lnxi.com 10 Nov '04

10 Nov '04

Perhaps the list can help. At the moment I don't have time.... Eric

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RE: Problem with AMD HDT setup for Tyan S2885 - LinuxBIOS debuggi ng
by YhLu 09 Nov '04

09 Nov '04

HW engineer said "on S2885, put jumper caps on J94 pin2 and pin3; J95 pin1 and pin2 to make HDT and MP HDT work. J94 and J95 are in middle of the area between bootable CPU memory modules and secondary CPU socket. the pin1 is the pin more close to the board edge and power connectors." Regards YH -----Original Message----- From: Ken Fuchs [mailto:kfuchs@winternet.com] Sent: Tuesday, November 09, 2004 12:35 PM To: LinuxBIOS(a)clustermatic.org Subject: Problem with AMD HDT setup for Tyan S2885 - LinuxBIOS debugging Purpose: To use AMD's HDT hardware/software to debug LinuxBIOS on various mainboards and chipsets. Two HDT headers were added to a commercial Tyan S2885 board. Here's my hardware setup: S2885 with HDT CPU0 header <-> HDT ribbon cable and HDT CPU1 header <-> HDT ribbon cable HDT ribbon cable <-> HDT Multiprocessor Adapter HDT ribbon cable <-> | HDT Multiprocessor Adapter <-> Macraigor Systems' OCDemon (Raven) OCDemon (Raven) <-> parallel cable <-> host EPP mode port Power up sequence: 1) Host 2) Target 3) OCDemon (Raven) 4) HDT MP Adapter Symptoms of the problem: 1) OCDemon host and target lights never go on. 2) When using the host HDT software to open a new workspace, only 1 processor is shown as available. 3) While completing the opening of this single processor workspace, a warning window with the text below pops open: +--------------------------------------------+ |Communication between HDT and | |Processor No. 0 has problem! | | | |Please check your HDT host | |and target TAP connections. | | | |Do you want to continue with incorrect info?| +--------------------------------------------+ Possible clue to the solution: Missing TDI/TDO jumpers or jumper headers? There is a 2x3 header pad (no header) directly between the P1 socket and the P0 DIMM sockets that could be the correct place for these jumper headers. Maybe all I need to do is add a 2x3 header there and trace the routes of the six pins, hopefully back to the P0's HDT connector? (I don't have access to the S2885's schematics.) It seems that MP HDT must be enabled in this way. I know that reference boards have toggle switches for this purpose. Please respond with your suggestions. Thank you very much! Sincerely, Ken Fuchs <kfuchs(a)winternet.com> _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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RE: Using Suse 9.1 pro for AMD64 as dev server.
by YhLu 09 Nov '04

09 Nov '04

>Which version of Etherboot? I think I ran into a version with 5.2.4 >where ELF/ZELF images were corrupt no matter which GCC I tried. In the Old RH 9, gcc-3.2.2 works well. [root@tst2723-rh9 xx]# /usr/bin/gcc --version gcc (GCC) 3.2.2 20030222 (Red Hat Linux 3.2.2-5) Copyright (C) 2002 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

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RE: tyan S2850 - optimal performance
by Sagiv Yefet 09 Nov '04

09 Nov '04

Where can I get a list of those parameters and there values ? Sagiv -----Original Message----- From: Stefan Reinauer [mailto:stepan@openbios.org] Sent: Sunday, November 07, 2004 6:53 PM To: Sagiv Yefet Cc: linuxbios(a)clustermatic.org Subject: Re: tyan S2850 - optimal performance * Sagiv Yefet <sagivy(a)3vium.com> [041107 17:52]: > Hello, > I have the TYAN s2850 board and I am running with Linux bios. > I want to use it in optimal performance. > Are there any parameters that I could change? > Does someone know about the optimal parameters in TYAN S2850 board? LinuxBIOS ought to configure the board with optimal performance parameters already. Is there anything you are missing? Stefan

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romcc quesiton
by Ronald G. Minnich 09 Nov '04

09 Nov '04

I'm seeing that with the new built-in preprocessor the following types of things work incorrectly: #if 0 blha blha #endif The #if 0 is ignored, the romcc tries to compile the code. Is this the expected behavior? ron p.s. cvs update as of this morning.

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Using Suse 9.1 pro for AMD64 as dev server.
by YhLu 09 Nov '04

09 Nov '04

I'm planning to use Suse 9.1 pro for AMD64 as my dev server. I have encountered some problems: 1. vi color, the Old RH 9 vi can high lighten the C grammar. But the Suse don't how to enable it? 2. can not compiled gcc 3.4.2 under Suse 9.1 pro for AMD 64. 3. Etherboot doesn't like gcc 3.3.3, the tg3.zelf produced is corrupted, only 17k. Regards YH

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coreboot November 2004