coreboot November 2004

coreboot@coreboot.org

31 participants
183 discussions

RE: romcc quesiton
by YhLu 15 Nov '04

15 Nov '04

I met that too, and I have remove some un converted code in E7501 raminit.c YH -----Original Message----- From: Ronald G. Minnich [mailto:rminnich@lanl.gov] Sent: Tuesday, November 09, 2004 6:44 AM To: linuxbios(a)clustermatic.org Subject: romcc quesiton I'm seeing that with the new built-in preprocessor the following types of things work incorrectly: #if 0 blha blha #endif The #if 0 is ignored, the romcc tries to compile the code. Is this the expected behavior? ron p.s. cvs update as of this morning. _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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ram init
by Gin Lin 14 Nov '04

14 Nov '04

Does anyone know if the raminit.c under intel/E7501 is stable enough? I am having a problem with the system reseting when it jumps to the first address in the ram. Could the procedures of writing NorthBrige registers have problems? thanks, Gin

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i845 MB progress
by zhu shi song 14 Nov '04

14 Nov '04

Now I can boot my i845 MB successfully with kernel 2.4.27. please see content of /proc/pci: PCI devices found: Bus 0, device 0, function 0: Host bridge: Intel Corp. 82845G/GL [Brookdale-G] Chipset Host Bridge (rev 3) . Prefetchable 32 bit memory at 0xe0000000 [0xe3ffffff]. Bus 0, device 2, function 0: VGA compatible controller: Intel Corp. 82845G/GL [Brookdale-G] Chipset Integ rated Graphics Device (rev 3). IRQ 11. Prefetchable 32 bit memory at 0xd0000000 [0xd7ffffff]. Non-prefetchable 32 bit memory at 0xdff80000 [0xdfffffff]. Bus 3, device 10, function 0: Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ ( rev 16). IRQ 3. Master Capable. Latency=32. Min Gnt=32.Max Lat=64. I/O at 0xcc00 [0xccff]. Non-prefetchable 32 bit memory at 0xdfdfff00 [0xdfdfffff]. It seemed that linux assigned correct irq to rtl8139. But there was some trouble with ethernet. (1)insmod 8139too ---> ok (2)ifconfig eth0 192.12.10.167 ---> error linux box hangup and the driver output "rtl8139: exiting interrupt, intr_status=0000" continuously. my settings: (1)don't set FEC0__xxxx regs (2) 0x4d0=28 0x4d1=1c 0x21=e8 0xA1=3f who has met the same problem and can give some glues to solve it? tks zhu __________________________________ Do you Yahoo!? Check out the new Yahoo! Front Page. www.yahoo.com

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ppc targets
by Stefan Reinauer 14 Nov '04

14 Nov '04

The ppc targets fail because of src/cpu/ppc/ppc4xx/mem.c struct mem_range is never ever defined. Is it struct lb_memory?! I have a bunch of other patches lying around that I will commit if nobody complains Stefan

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Problem with AMD HDT setup for Tyan S2885 - LinuxBIOS debugging
by Ken Fuchs 12 Nov '04

12 Nov '04

Purpose: To use AMD's HDT hardware/software to debug LinuxBIOS on various mainboards and chipsets. Two HDT headers were added to a commercial Tyan S2885 board. Here's my hardware setup: S2885 with HDT CPU0 header <-> HDT ribbon cable and HDT CPU1 header <-> HDT ribbon cable HDT ribbon cable <-> HDT Multiprocessor Adapter HDT ribbon cable <-> | HDT Multiprocessor Adapter <-> Macraigor Systems' OCDemon (Raven) OCDemon (Raven) <-> parallel cable <-> host EPP mode port Power up sequence: 1) Host 2) Target 3) OCDemon (Raven) 4) HDT MP Adapter Symptoms of the problem: 1) OCDemon host and target lights never go on. 2) When using the host HDT software to open a new workspace, only 1 processor is shown as available. 3) While completing the opening of this single processor workspace, a warning window with the text below pops open: +--------------------------------------------+ |Communication between HDT and | |Processor No. 0 has problem! | | | |Please check your HDT host | |and target TAP connections. | | | |Do you want to continue with incorrect info?| +--------------------------------------------+ Possible clue to the solution: Missing TDI/TDO jumpers or jumper headers? There is a 2x3 header pad (no header) directly between the P1 socket and the P0 DIMM sockets that could be the correct place for these jumper headers. Maybe all I need to do is add a 2x3 header there and trace the routes of the six pins, hopefully back to the P0's HDT connector? (I don't have access to the S2885's schematics.) It seems that MP HDT must be enabled in this way. I know that reference boards have toggle switches for this purpose. Please respond with your suggestions. Thank you very much! Sincerely, Ken Fuchs <kfuchs(a)winternet.com>

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Re: ppc targets
by ebiederman＠lnxi.com 12 Nov '04

12 Nov '04

Greg Watson <g.watson(a)computer.org> writes: > On Nov 11, 2004, at 7:27 PM, Eric W. Biederman wrote: > > > Stefan Reinauer <stepan(a)openbios.org> writes: > > > >> The ppc targets fail because of src/cpu/ppc/ppc4xx/mem.c > >> struct mem_range is never ever defined. Is it struct lb_memory?! > > > > That is because of the big change where sizeram was removed. > > I think the definition originally sat in src/include/mem.h > > Which has been removed, because it is no longer used. > > > > So where/how is this done now? read_resources of an appropriate device now returns the information. > What else has been changed? Everything (short of interrupts) is now done through the device tree. The static device tree now uses the same nodes as the dynamic device tree. > It would be nice if a change like this was accompanied by a > description of what has been done, particularly if targets are left > for someone else to update. It was not the intention to leave this for someone else to update. The ppc ports were simply at the end of the list. And beyond that their structure does not much resemble the structure of the other ports on x86. Just glancing at the ppc code I have not seen an appropriate device to attach the code to. I was planning on looking into the powerpc code in the next couple of days. To see if I could sort this out. Eric

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RE: mtrr
by YhLu 11 Nov '04

11 Nov '04

x86_setup_mtrrs should be split to x86_setup_fixed_mtrrs x86_setup_var_mtrrs x86_setup_enable_mtrrs and for Opteron it can reuse x86_setup_var_mtrrs x86_setup_enable_mtrrs and x86_setup_var_mtrrs can take the cupid or sth as parameter to find out 40bit or 32 bit. YH -----Original Message----- From: ebiederman(a)lnxi.com [mailto:ebiederman@lnxi.com] Sent: Thursday, November 11, 2004 6:20 PM To: YhLu Cc: 'Ronald G. Minnich'; 'linuxbios(a)clustermatic.org' Subject: Re: mtrr YhLu <YhLu(a)tyan.com> writes: > In the cpu/x86/mtrr/mtrr.c > > #warning "FIXME I do not properly handle address more than 36 physical > address bits" > #ifdef k8 > # define ADDRESS_BITS 40 > #else > # define ADDRESS_BITS 36 > #endif > #define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32) > #define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1) > > It seems someone already remove k8 from Option.lb > > Then .... > > Regards Interesting. The mtrr's actually work and the kernel is confused. However what we need to do is call the appropriate cpuid function to compute it or pass in the number of address bits. It should not be a compile time option, at least not in the generic code. What happens when we get can plug in cpus with different address bit limits. Eric

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autobuild statistics
by Stefan Reinauer 11 Nov '04

11 Nov '04

Hi, The abuild script checks for new checkins now every 4h and logs are placed at: http://snapshots.linuxbios.org/stats/ BTW, the latest changes made things a little more dramatic again. In size, compile time and compile success. Stefan

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RE: mtrr
by YhLu 11 Nov '04

11 Nov '04

In the cpu/x86/mtrr/mtrr.c #warning "FIXME I do not properly handle address more than 36 physical address bits" #ifdef k8 # define ADDRESS_BITS 40 #else # define ADDRESS_BITS 36 #endif #define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32) #define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1) It seems someone already remove k8 from Option.lb Then .... Regards YH -----Original Message----- From: YhLu Sent: Thursday, November 11, 2004 6:00 PM To: YhLu; ebiederman(a)lnxi.com; Ronald G. Minnich Cc: linuxbios(a)clustermatic.org Subject: RE: mtrr On 2.4.22 it becomes to ~ # cat /proc/mtrr reg00: base=0x00000000 ( 0MB), size=32768MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=16384MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=4096MB: write-back, count=1 x 16 -----Original Message----- From: YhLu Sent: Thursday, November 11, 2004 5:24 PM To: ebiederman(a)lnxi.com; Ronald G. Minnich Cc: linuxbios(a)clustermatic.org Subject: mtrr I just found the mtrr after booting is not right. ~ # cat /proc/mtrr reg00: base=0x00000000 ( 0MB), size=985088MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=984064MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=983296MB: write-back, count=1 and it should be reg00: base=0x00000000 ( 0MB), size=2048MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=1024MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=256MB: write-back, count=1 and it is has 98340MB more = 0xf0 0000 0000. Regards YH _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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RE: mtrr
by YhLu 11 Nov '04

11 Nov '04

On 2.4.22 it becomes to ~ # cat /proc/mtrr reg00: base=0x00000000 ( 0MB), size=32768MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=16384MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=4096MB: write-back, count=1 x 16 -----Original Message----- From: YhLu Sent: Thursday, November 11, 2004 5:24 PM To: ebiederman(a)lnxi.com; Ronald G. Minnich Cc: linuxbios(a)clustermatic.org Subject: mtrr I just found the mtrr after booting is not right. ~ # cat /proc/mtrr reg00: base=0x00000000 ( 0MB), size=985088MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=984064MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=983296MB: write-back, count=1 and it should be reg00: base=0x00000000 ( 0MB), size=2048MB: write-back, count=1 reg01: base=0x80000000 (2048MB), size=1024MB: write-back, count=1 reg02: base=0xc0000000 (3072MB), size=256MB: write-back, count=1 and it is has 98340MB more = 0xf0 0000 0000. Regards YH _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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coreboot November 2004