coreboot November 2004

coreboot@coreboot.org

31 participants
183 discussions

i845gv MB progress
by zhu shi song 19 Nov '04

19 Nov '04

Now I can set sma correctly. But still can't execute vgabios successfully. After executing testbios, the following message prompted: **************************** [root@localhost /app]# ./testbios -s 65536 ./i845.vga running file ./i845.vga No base specified. defaulting to 0xc0000 No initial code segment specified. defaulting to 0xc000 No initial instruction pointer specified. defaulting to 0x0003 c000:015a: 62 ILLEGAL X86 OPCODE! halt_sys: file ops.c, line 94 halted ************************************* what can I do to solve the problem? tks zhu __________________________________ Do you Yahoo!? The all-new My Yahoo! - Get yours free! http://my.yahoo.com

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i845GV VGA progress
by zhu shi song 18 Nov '04

18 Nov '04

I use intelfb in linux-2.4.27. VGA of i845 can work correctly except that there is no cursor. So if there is no cursor, it's almost nothing for practical usage. Now I hope I can find some way to fix it up in intelfb. tks zhu __________________________________ Do you Yahoo!? Meet the all-new My Yahoo! - Try it today! http://my.yahoo.com

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Re: reset loop??
by Stefan Reinauer 18 Nov '04

18 Nov '04

* Jay Miller <jmiller(a)actuality-systems.com> [041119 00:13]: > I thought it might be an ht issue because needs_reset gets set by the > ht_setup_chain, and our board is unique in that it has 8151->8131->8111 > all on link 0. But I adjusted the position passed into that function > and saw no improvement. Perhaps the position I chose was wrong (0xa0 vs > the default 0x80)? 80 is ldt0, a0 is ldt1, c0 is ldt2 Stefan

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reset loop??
by Jay Miller 18 Nov '04

18 Nov '04

Has anyone seen a situation where the BIOS appears stuck in a reset loop on cold boot? On cold boot our board continually loops through the reset path. We had apparently "worked around" this problem by pointing HARD_RESET_DEVICE to the 8131, which meant that nothing actually got reset. But now we're running into interrupt problems caused by the "work around" that doesn't. HDT loses it's mind in the protected_start section, just prior to the reset, but I have stopped it to see that there is only the 8151 on the PCI bus scan. This is more that likely a red herring... I thought it might be an ht issue because needs_reset gets set by the ht_setup_chain, and our board is unique in that it has 8151->8131->8111 all on link 0. But I adjusted the position passed into that function and saw no improvement. Perhaps the position I chose was wrong (0xa0 vs the default 0x80)? Any other thoughts? Thanks, Jay Miller 781-229-7812x117 Actuality Systems, Inc. jmiller(a)actuality-systems.com

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Re: ppc targets
by ebiederman＠lnxi.com 17 Nov '04

17 Nov '04

Ok I am starting to dig into these and figure out what needs to happen to get the ppc targets working again. The hardest case currently appears to be the sandpointx3 with pmc processor modules, so I will get to it last. The whole northboard/southboard thing is interesting. But something we need to handle. I think I have heard of the same thing with a few hypertransport based systems as well. Which board is the bootrom that the systems starts executing with on. The few schematics I have looked up so far have a bootrom on the sandpoint and the MPCxxx pmc module. The other datapoint I need to track down is are there other boards the processor pmc modules can plug into. Or there tighter coupling than that. I have not been able to track down documentation on cpu the embeddedplanet epc405 is using. In fact I'm not even certain which cpu it is using which is part of the problem. Does that board use a northbridge at all or is the memory controller and pci bus built into the cpu? But it looks like I have tracked down enough information on the totalipact/briq, to understand what is going on. Or at least well enough that I can get something that will build and will be close to working built. So I am starting there despite the fact it does not look like that port was ever quite finished, or at least it was never built to handle the general case as it has a hardcoded memory size. One of the cases the northboard/southboard thing brings up is that we don't have good infrastructure for handling plugin boards with lots of chips that need special handling. If we can identify them we can do something, the code is just not very general yet. It is likely we want to be able to build a static device tree that describes a pluging board that we can just graft to the main tree when we detect that board. It is something to think about anyway. Eric

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i845 progress
by zhu shi song 17 Nov '04

17 Nov '04

At last , rtl8139 work correctly. Now I'm working on VGA(internal graphic device). I set 0x52(graphic control register) to 0x40 to let IGD enable and SMA size to 8M, but filo reset MB. I need to set some other things? tks zhu __________________________________ Do you Yahoo!? The all-new My Yahoo! - Get yours free! http://my.yahoo.com

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Re: boot from ide
by Gin 17 Nov '04

17 Nov '04

Thanks, I got an error while specifying the fall back rom image size of larger than 64K. See below: 1. When ROM_IMAGE_SIZE = 0x2000 ./buildrom linuxbios.strip linuxbios.rom /opt/filo/fallback/filo.elf 0x20000 0x40000 linuxbios image is 131087 bytes; only 131072 allowed Linuxbios input file larger than allowed size! : Success make: *** [linuxbios.rom] Error 2 2.When ROM_IMAGE_SIZE = 0x3000 ./buildrom linuxbios.strip linuxbios.rom /opt/filo/fallback/filo.elf 0x30000 0x40000 linuxbios image is 196623 bytes; only 196608 allowed Linuxbios input file larger than allowed size! : Success make: *** [linuxbios.rom] Error 2 -----Original Message----- From: linuxbios-admin(a)clustermatic.org [mailto:linuxbios-admin@clustermatic.org] On Behalf Of Greg Watson Sent: Thursday, November 18, 2004 10:21 AM To: Gin Cc: 'LinuxBIOS' Subject: Re: boot from ide Actually, don't set CONFIG_FS_STREAM if you're using Filo as a payload. Use the CONFIG_IDE_STREAM instead. Greg On Nov 17, 2004, at 7:05 PM, Gin wrote: > Hello, > I've got my linuxbios run to the point it tries to load the image from > an IDE drive. I use FILO as the payload. > > 1. What do I have to add in the Config.lb file to make it use filo? I > know CONFIG_FS_STREAM should be set to true. What else? > > 2. I remembered linuxbios supports ROM image size larger than 64K now. > But when got compiler errors when specifies it as 128K. Do I miss > anything? > > > Gin > > _______________________________________________ > Linuxbios mailing list > Linuxbios(a)clustermatic.org > http://www.clustermatic.org/mailman/listinfo/linuxbios > _______________________________________________ Linuxbios mailing list Linuxbios(a)clustermatic.org http://www.clustermatic.org/mailman/listinfo/linuxbios

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pci_operations for amd8111_ac97.c
by Li-Ta Lo 16 Nov '04

16 Nov '04

Eric, The lpci_set_subsystem() in amd8111_ac97.c is exactly the same as the default pci_dev_set_subsystem(), why do you define it instead of using the default one? BTW, why can't the set_subsystem() method be set at runtime ? Ollie

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Re: Flash_rom
by Ronald G. Minnich 15 Nov '04

15 Nov '04

On Mon, 15 Nov 2004, Yinghai Lu wrote: > It should use SB name and model... SB? ron

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Can't remember if I mentioned this for abuild.
by Ronald G. Minnich 15 Nov '04

15 Nov '04

You should see the adl855pc building just fine again. If not, well, tell me :-) ron

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coreboot November 2004