coreboot April 2013

coreboot@coreboot.org

42 participants
125 discussions

#95: Run coreboot in VirtualBox
by coreboot 09 Dec '14

09 Dec '14

#95: Run coreboot in VirtualBox ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: misc | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+---------------… [View More]

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EHCI debug port finder
by Carl-Daniel Hailfinger 30 May '14

30 May '14

I wanted to know which physical port of my multiple USB controllers have the debug capability. There was no way to find that easily, so I created a tool which will do most of the work for the user. Example output: The following PCI devices support a USB debug port (says lspci): 0000:00:1d.7 The following PCI devices support a USB debug port (says the kernel): 0000:00:1d.7 PCI device 0000:00:1d.7, USB bus 3, USB physical port 1 Currently connected high-speed devices: /: Bus 03.Port 1: Dev 1, … [View More]

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Dual SPI Flash adapter attempt 2.0
by Oliver Schinagl 09 Mar '14

09 Mar '14

Hi list(s), Here's my second attempt at routing the previously mailed png of my schema. It was a lot trickier to route then my previous version, but I think it worked out! As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1 should be 10k or ideally 100k, as Peter mentioned earlier. Hopefully there's no obvious mistakes and can start working on alternative layouts (so it is insert-able in different angles). DRC Check fails on S1, S2 and U3. It thinks the distance is to … [View More]

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fixed AMD SPI speed settings (leading to problems on E350M1/USB3)
by Stefan Tauner 02 Feb '14

02 Feb '14

Hi, andor reported a problem where flashrom does reproducibly not work with coreboot but does with the vendor BIOS http://paste.flashrom.org/view.php?id=1614 Apparently it is related to fast reads and/or the frequency. We have forced the fastReadEnable bit in the SPI_Cntrl0 from 1 to 0 and also set NormSpeed in SPI_Cntrl1 to 16.5 Mhz (previously was 0 i.e. 66 MHz) in flashrom and the problem vanished. Coreboot hard codes the fast read setting in src/southbridge/amd/cimx/sb800/bootblock.c: … [View More]

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#186: 3com 3c905tx / gpxe boot problem
by coreboot 10 Jan '14

10 Jan '14

#186: 3com 3c905tx / gpxe boot problem -----------------------------------+---------------------------------- Reporter: jeroenkrabbendam@… | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: coreboot | Keywords: gpxe Dependencies: | Patch Status: there is no patch -----------------------------------+---------------------------------- Although (or: … [View More]

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#191: Coreboot:libpayload-size_t conflicting types compiler error
by coreboot 05 Nov '13

05 Nov '13

#191: Coreboot:libpayload-size_t conflicting types compiler error ---------------------------+---------------------------------- Reporter: Pradish | Owner: uwe@… Type: defect | Status: new Priority: blocker | Milestone: Component: libpayload | Keywords: Dependencies: | Patch Status: there is no patch ---------------------------+---------------------------------- Hi I have question related to libpayload, which I am … [View More]

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unsupported mb questions (amd fam10h)
by Roman Elshin 21 Jul '13

21 Jul '13

I try to get coreboot working with asrock 880g pro3 board. First problem: spd eprom say that memory ddr1600 capable, but it is not so, is there are right way to limit memory frequency at ddr1333? Other problem, may be related as machine with broken memory are very unpredictable: boot process stop with "It is not SB800 or SB810" message. I try to enable sb850 by this patch, but looks like it is not enough, most of time coreboot does not detect hdd. Sometimes in very rare case it is possible … [View More]

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Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer)
by darkdefende＠gmail.com 04 Jul '13

04 Jul '13

Idwer Vollering writes: > Done. Thanks for attaching the log for me. Some recent commits to coreboot master seems to have solved my problem with the pci scan hang. Now I don't have to hack around it any more. However it still freezes after it's done (?) loading seabios. I have uploaded my changes to https://github.com/DarkDefender/coreboot if anyone want's to look at them. I've tried to enable more debugging options in the "OptionsIds.h" for AGESA but it doesn't seem to do anything. The … [View More]

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ASRock E350M1: Linux reports `piix4_smbus 0000:00:14.0: SMBus base address index region 0xcd6 already in use!`
by Paul Menzel 23 May '13

23 May '13

Dear coreboot folks, since [1] commit df729d7778a7e5878fac5545883f68e42372456a Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 14:46:31 2013 +0100 AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead of `0xB00` which I expanded to the ASRock E350M1, overlooking the new error message, Linux complains about an already used base address index region. calling i2c_piix4_init+0x0/0x1000 [… [View More]

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Re: [coreboot] On loongson CPU or MIPS ARCH
by ron minnich 30 Apr '13

30 Apr '13

OK, I took a look at the code. Nice to see such a simple startup, reminds of linuxbios v1 days. At least if this is the right one: http://fossies.org/linux/misc/grub-2.00.tar.gz:a/grub-2.00/grub-core/boot/m… I don't see a problem pulling this in to coreboot. We'd probably trim some bits out and let ramstage take over, but for a first cut it could be used as is. This code is very similar in how it works to many linuxbios/coreboot platforms and hence should fit into the coreboot structure with … [View More]

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coreboot April 2013