Hi,
attached patch disables failover for K8 based boards and makes them use the more usual fallback/normal style. Fam10h requires some reduction in size, or other tricks as the ROM part exceeds 64k (the original ROM mapping) by just a bit. I'll work on that soon.
The {HAVE,USE}_FAILOVER stuff still stays in the code itself as it might be useful as a reference (ie. what is strictly necessary to configure ROM mapping) for later work.
Signed-off-by: Patrick Georgi patrick.georgi@coresystems.de
Patrick
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Config.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -107,7 +107,7 @@ default CONFIG_ROM_SIZE=524288 ##
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -116,7 +116,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/asus/a8n_e/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Config.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Config.lb @@ -23,7 +23,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end driver mainboard.o Index: coreboot-v2/src/mainboard/asus/a8n_e/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/Options.lb +++ coreboot-v2/src/mainboard/asus/a8n_e/Options.lb @@ -102,9 +102,9 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 * CONFIG_HAVE_FAILOVER_BOOT default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 0 default CONFIG_HAVE_HARD_RESET = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 default CONFIG_IRQ_SLOT_COUNT = 13 Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -70,7 +70,6 @@ #include <cpu/amd/model_fxx_rev.h>
#include "southbridge/sis/sis966/sis966_early_smbus.c" -#include "southbridge/sis/sis966/sis966_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Config.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb @@ -23,7 +23,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -135,7 +135,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -144,7 +144,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Config.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/Options.lb +++ coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb @@ -136,7 +136,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -150,7 +150,7 @@ default CONFIG_HAVE_FANCTL=1 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Config.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/Options.lb +++ coreboot-v2/src/mainboard/iwill/dk8_htx/Options.lb @@ -109,7 +109,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-8K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 8K -default CONFIG_FAILOVER_SIZE=0x02000 +default CONFIG_FAILOVER_SIZE=0x02000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -118,7 +118,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/msi/ms7135/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Config.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Config.lb @@ -24,7 +24,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/msi/ms7135/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7135/Options.lb @@ -115,7 +115,7 @@ default CONFIG_ROM_SIZE=(512*1024) default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
#FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=(4*1024) +default CONFIG_FAILOVER_SIZE=(4*1024) * CONFIG_HAVE_FAILOVER_BOOT
### ### Build options @@ -125,7 +125,7 @@ default CONFIG_FAILOVER_SIZE=(4*1024) ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/msi/ms7260/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Config.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Config.lb @@ -20,7 +20,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/msi/ms7260/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/Options.lb +++ coreboot-v2/src/mainboard/msi/ms7260/Options.lb @@ -102,10 +102,10 @@ uses CONFIG_USE_PRINTK_IN_CAR
default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 +default CONFIG_FAILOVER_SIZE = 4 * 1024 * CONFIG_HAVE_FAILOVER_BOOT default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 +default CONFIG_HAVE_FAILOVER_BOOT = 0 default CONFIG_HAVE_HARD_RESET = 1 default CONFIG_HAVE_PIRQ_TABLE = 1 default CONFIG_IRQ_SLOT_COUNT = 11 # TODO: Check if correct. Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Config.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/Options.lb +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -133,7 +133,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,7 +142,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Config.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb @@ -18,7 +18,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dme/Options.lb @@ -137,7 +137,7 @@ default CONFIG_MULTIBOOT=0 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -146,7 +146,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Config.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb @@ -130,7 +130,7 @@ default CONFIG_ROM_SIZE=0x100000 ## default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -139,7 +139,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot @@ -252,7 +252,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_D ###
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0xf000 +default CONFIG_ROM_IMAGE_SIZE = 0x10000 - CONFIG_FAILOVER_SIZE
## Index: coreboot-v2/src/mainboard/tyan/s2895/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Config.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Config.lb @@ -1,6 +1,6 @@ ## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/tyan/s2895/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2895/Options.lb @@ -95,7 +95,7 @@ default CONFIG_ROM_SIZE=1024*1024 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -104,7 +104,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/src/mainboard/tyan/s2912/Config.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Config.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Config.lb @@ -21,7 +21,7 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2. default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb +include /config/nofailovercalculation.lb
arch i386 end
Index: coreboot-v2/src/mainboard/tyan/s2912/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/Options.lb +++ coreboot-v2/src/mainboard/tyan/s2912/Options.lb @@ -133,7 +133,7 @@ default CONFIG_ROM_SIZE=524288 #FALLBACK: 256K-4K default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #FAILOVER: 4K -default CONFIG_FAILOVER_SIZE=0x01000 +default CONFIG_FAILOVER_SIZE=0x01000 * CONFIG_HAVE_FAILOVER_BOOT
#more 1M for pgtbl default CONFIG_LB_MEM_TOPK=2048 @@ -142,7 +142,7 @@ default CONFIG_LB_MEM_TOPK=2048 ## Build code for the fallback boot ## default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_HAVE_FAILOVER_BOOT=1 +default CONFIG_HAVE_FAILOVER_BOOT=0
## ## Build code to reset the motherboard from coreboot Index: coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/amd/serengeti_cheetah/Config-abuild.lb +++ coreboot-v2/targets/amd/serengeti_cheetah/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/asus/a8n_e/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/asus/a8n_e/Config-abuild.lb +++ coreboot-v2/targets/asus/a8n_e/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/gigabyte/ga_2761gxdk/Config-abuild.lb +++ coreboot-v2/targets/gigabyte/ga_2761gxdk/Config-abuild.lb @@ -45,13 +45,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-Failover" -end - - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/gigabyte/m57sli/Config-abuild.lb +++ coreboot-v2/targets/gigabyte/m57sli/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/iwill/dk8_htx/Config-abuild.lb +++ coreboot-v2/targets/iwill/dk8_htx/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/msi/ms7135/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/msi/ms7135/Config-abuild.lb +++ coreboot-v2/targets/msi/ms7135/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/msi/ms7260/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/msi/ms7260/Config-abuild.lb +++ coreboot-v2/targets/msi/ms7260/Config-abuild.lb @@ -42,13 +42,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE = 1 - option CONFIG_USE_FALLBACK_IMAGE = 0 - option CONFIG_ROM_IMAGE_SIZE = CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE = CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION = ".0Failover" -end - -# buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/nvidia/l1_2pvv/Config-abuild.lb +++ coreboot-v2/targets/nvidia/l1_2pvv/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dme/Config-abuild.lb +++ coreboot-v2/targets/supermicro/h8dme/Config-abuild.lb @@ -24,12 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/supermicro/h8dmr/Config-abuild.lb +++ coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb @@ -21,10 +21,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option COREBOOT_EXTRA_VERSION=".0-failover" -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/tyan/s2895/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/tyan/s2895/Config-abuild.lb +++ coreboot-v2/targets/tyan/s2895/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" Index: coreboot-v2/targets/tyan/s2912/Config-abuild.lb =================================================================== --- coreboot-v2.orig/targets/tyan/s2912/Config-abuild.lb +++ coreboot-v2/targets/tyan/s2912/Config-abuild.lb @@ -24,11 +24,4 @@ romimage "fallback" payload __PAYLOAD__ end
-romimage "failover" - option CONFIG_USE_FAILOVER_IMAGE=1 - option CONFIG_USE_FALLBACK_IMAGE=0 - option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE - option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE -end - -buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover" +buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
On Wed, Aug 12, 2009 at 1:08 PM, Patrick Georgi patrick@georgi-clan.dewrote:
Hi,
attached patch disables failover for K8 based boards and makes them use the more usual fallback/normal style. Fam10h requires some reduction in size, or other tricks as the ROM part exceeds 64k (the original ROM mapping) by just a bit. I'll work on that soon.
The {HAVE,USE}_FAILOVER stuff still stays in the code itself as it might be useful as a reference (ie. what is strictly necessary to configure ROM mapping) for later work.
My understanding was that we wanted to go the other way and have all boards have failover.
Myles
Myles Watson schrieb:
On Wed, Aug 12, 2009 at 1:08 PM, Patrick Georgi <patrick@georgi-clan.de mailto:patrick@georgi-clan.de> wrote:
Hi, attached patch disables failover for K8 based boards and makes them use the more usual fallback/normal style. Fam10h requires some reduction in size, or other tricks as the ROM part exceeds 64k (the original ROM mapping) by just a bit. I'll work on that soon. The {HAVE,USE}_FAILOVER stuff still stays in the code itself as it might be useful as a reference (ie. what is strictly necessary to configure ROM mapping) for later work.My understanding was that we wanted to go the other way and have all boards have failover.
Kconfig doesn't support >1 image per build right now. This merely moves abuild to the same state, to simplify development.
We might want to have "something like failover". We might want to have "something like fallback and normal". But we will have to reconsider what exactly we want.
In my opinion such changes are easier if the tree is as uniform as possible. Right now, there's failover style (k8 and fam10) and fallback/normal style (everything else). Moving from the latter to the former is harder than the other way around.
Patrick
My understanding was that we wanted to go the other way and have all boards have failover.
Kconfig doesn't support >1 image per build right now. This merely moves abuild to the same state, to simplify development.
If Koenig doesn't support fallback and normal yet, maybe that should come first.
We might want to have "something like failover". We might want to have "something like fallback and normal". But we will have to reconsider what exactly we want.
I like the cleanliness of having the early setup and image selection done separately. It made the s2895 code much easier for me to follow.
In my opinion such changes are easier if the tree is as uniform as possible.
Agreed.
Right now, there's failover style (k8 and fam10) and fallback/normal style (everything else). Moving from the latter to the former is harder than the other way around.
In general removing features is easier than adding them. Will this make it easier to add it later?
Thanks, Myles
On Wed, Aug 12, 2009 at 2:02 PM, Myles Watson mylesgw@gmail.com wrote:
My understanding was that we wanted to go the other way and have all boards have failover.
Kconfig doesn't support >1 image per build right now. This merely moves abuild to the same state, to simplify development.
If Koenig doesn't support fallback and normal yet, maybe that should come first.
Kconfig. I hit the wrong button on the spell check.
Myles
Myles Watson schrieb:
If Koenig doesn't support fallback and normal yet, maybe that should come first.
fallback/normal was a fine solution for pre-CBFS images. I'm not convinced it still is.
A safe update method is the main use case for fallback/normal I've heard about so far. With CBFS, updating an image is harder than before. pre-CBFS, you could simply dd(1) the old and the new image in some ways and get a new image with a new normal image and an old fallback image. With CBFS, you don't have such a clean alignment of the data inside the image, so you'll have to extract the pieces and add them to the other image.
I propose this approach instead: - You can configure the build to create a new ROM image, or append to an existing one - You can configure the build to add the newly created code as "fallback" or "normal" - You can configure the build to rename pre-existing "normal" CBFS files to "fallback" - There's a switch somewhere in the code that runs "fallback" if it exists and the previous boot didn't succeed, and runs "normal" otherwise. - The bootblock is usually not touched on update (which also means that we have to move more code from there to CBFS to make any update process more useful)
That way, the build process builds only one variant of the code. When you update, the existing variant is renamed (so it can act as fallback if the new code breaks).
The other thing fallback/normal is used for is CMOS-aware code with recovery if CMOS is invalid. But it's flawed as it is: When the "normal image" bit is set correctly, and everything else is wrong, normal is run, and probably hangs (it did for me). What _should_ happen (in my opinion) is that we use the CMOS checksum, and have the same code use a static field (somewhere in ROM) as a backup if the CMOS values can't be trusted.
That could work by extending the cmos.layout file with defaults that are written to some static C array, which is linked in. get_option (I think that's what the CMOS access code is called) switches between CMOS and this table based on the CMOS checksum. This is more stable than the current approach and gets rid of a second binary (probably with different behaviour beyond the config values!), too.
What other use cases for fallback/normal are there that must be accounted for?
In general removing features is easier than adding them. Will this make it easier to add it later?
The change can be reverted with little effort: set CONFIG_HAVE_FAILOVER_BOOT to 1, add failover to the Config-abuild.lb again, and it works as it does now. I didn't remove the #ifs for FAILOVER etc. to easily figure out what parts of the code are "early setup" and what's later code, so we can reuse it, should we want to.
Patrick
fallback/normal was a fine solution for pre-CBFS images. I'm not convinced it still is.
In that case what you're proposing is moving to fallback-only. That's one more step, right?
A safe update method is the main use case for fallback/normal I've heard about so far.
Another use case is hardware (an FPGA in my case) that might be misconfigured. If it is, the boot fails several times and uses the fallback.
It seems like both Ron and Stefan thought the dual image solution was necessary at one point. I don't remember their rationale.
With CBFS, updating an image is harder than before. pre-CBFS, you could simply dd(1) the old and the new image in some ways and get a new image with a new normal image and an old fallback image. With CBFS, you don't have such a clean alignment of the data inside the image, so you'll have to extract the pieces and add them to the other image.
That's fine as long as cbfstool works.
The other thing fallback/normal is used for is CMOS-aware code with recovery if CMOS is invalid. But it's flawed as it is: When the "normal image" bit is set correctly, and everything else is wrong, normal is run, and probably hangs (it did for me).
Then if you reboot enough times it goes to fallback as long as the failover code isn't broken.
What _should_ happen (in my opinion) is that we use the CMOS checksum, and have the same code use a static field (somewhere in ROM) as a backup if the CMOS values can't be trusted.
That could work by extending the cmos.layout file with defaults that are written to some static C array, which is linked in. get_option (I think that's what the CMOS access code is called) switches between CMOS and this table based on the CMOS checksum. This is more stable than the current approach and gets rid of a second binary
This seems orthogonal to me, but it seems like a good idea.
(probably with different behaviour beyond the config values!)
By design, right?
What other use cases for fallback/normal are there that must be accounted for?
I don't know. Fallback only is definitely simpler.
In general removing features is easier than adding them. Will this make
it
easier to add it later?
The change can be reverted with little effort: set CONFIG_HAVE_FAILOVER_BOOT to 1, add failover to the Config-abuild.lb again, and it works as it does now. I didn't remove the #ifs for FAILOVER etc. to easily figure out what parts of the code are "early setup" and what's later code, so we can reuse it, should we want to.
No problem. I think this is the right time to have this discussion.
Thanks, Myles
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Myles Watson -
Patrick Georgi