-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 05/18/2018 07:53 PM, Youness Alaoui wrote:
Hi Piotr,
Hi Youness,
Here's my librem13v2 info as reported by coreboot : CPU: Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz CPU: ID 406e3, Skylake D0, ucode: 000000c1 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 1904 (rev 08) is Skylake-U PCH: device id 9d48 (rev 21) is Skylake-U Premium IGD: device id 1916 (rev 07) is Skylake ULT GT2
So I can see that we have the exact same CPU, MCH, PCH and IGD, but there is one difference that I noticed, your line said : CPU: ID 406e3, Skylake D0, ucode: 00000000
Good catch. I'm not sure why I can't include microcode that I obtained using get_blobs.sh. I marked:
CONFIG_CPU_UCODE_BINARIES="cpu_microcode_blob.bin"
But my results is:
Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 47588 none fallback/ramstage 0xbb00 stage 84189 none vgaroms/seavgabios.bin 0x20440 raw 28672 none config 0x274c0 raw 457 none revision 0x27700 raw 580 none payload_revision 0x27980 raw 239 none (empty) 0x27ac0 null 1240 none fspm.bin 0x27fc0 fsp 389120 none payload_config 0x87000 raw 1682 none (empty) 0x87700 null 2200 none fsps.bin 0x87fc0 fsp 188416 none fallback/postcar 0xb6000 stage 31352 none fallback/dsdt.aml 0xbdac0 raw 12879 none fallback/payload 0xc0d80 simple elf 73920 none (empty) 0xd2e80 null 2877080 none cpu_microcode_blob.bin 0x391540 microcode 0 none (empty) 0x3915c0 null 1976792 none bootblock 0x573fc0 bootblock 49152 none
So something wrong with size. I added microcode manually and things look better right now. Thank you.
What is correct way to include binary microcode? In PC Engines we had to create our own method [1]. I wonder what would be correct way for tha t.
[1] https://github.com/pcengines/coreboot/pull/132/files
Best Regards, - -- Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com
Hi Piotr,
Great, I'm glad the ucode was indeed the issue, and that I was lucky enough to spot it. I think it doesn't get added correctly because the path might be wrong ? unless you put the ucode bin file in the root directory of coreboot, then it might not find it, or maybe it's another option to actually tell it to add the file to cbfs. See our ucode related configs in : https://code.puri.sm/kakaroto/coreboot-files/src/master/configs/config.libre...
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y CONFIG_CPU_MICROCODE_CBFS_GENERATE=y CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/cpu_microcode_blob.bin"
Also note these two options which get passed to the FSP so the microcode can get applied : CONFIG_CPU_MICROCODE_CBFS_LEN=0x18000 CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFE115A0
That location address makes cbfstool add the ucode binary in cbfs at the right offset so it's at that address, and the len has to match (or be superior) to the ucode file size.
I hope that helps, Youness.
On Sun, May 20, 2018 at 7:25 PM, Piotr Król piotr.krol@3mdeb.com wrote:
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256
On 05/18/2018 07:53 PM, Youness Alaoui wrote:
Hi Piotr,
Hi Youness,
Here's my librem13v2 info as reported by coreboot : CPU: Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz CPU: ID 406e3, Skylake D0, ucode: 000000c1 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 1904 (rev 08) is Skylake-U PCH: device id 9d48 (rev 21) is Skylake-U Premium IGD: device id 1916 (rev 07) is Skylake ULT GT2
So I can see that we have the exact same CPU, MCH, PCH and IGD, but there is one difference that I noticed, your line said : CPU: ID 406e3, Skylake D0, ucode: 00000000
Good catch. I'm not sure why I can't include microcode that I obtained using get_blobs.sh. I marked:
CONFIG_CPU_UCODE_BINARIES="cpu_microcode_blob.bin"
But my results is:
Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/romstage 0x80 stage 47588 none fallback/ramstage 0xbb00 stage 84189 none vgaroms/seavgabios.bin 0x20440 raw 28672 none config 0x274c0 raw 457 none revision 0x27700 raw 580 none payload_revision 0x27980 raw 239 none (empty) 0x27ac0 null 1240 none fspm.bin 0x27fc0 fsp 389120 none payload_config 0x87000 raw 1682 none (empty) 0x87700 null 2200 none fsps.bin 0x87fc0 fsp 188416 none fallback/postcar 0xb6000 stage 31352 none fallback/dsdt.aml 0xbdac0 raw 12879 none fallback/payload 0xc0d80 simple elf 73920 none (empty) 0xd2e80 null 2877080 none cpu_microcode_blob.bin 0x391540 microcode 0 none (empty) 0x3915c0 null 1976792 none bootblock 0x573fc0 bootblock 49152 none
So something wrong with size. I added microcode manually and things look better right now. Thank you.
What is correct way to include binary microcode? In PC Engines we had to create our own method [1]. I wonder what would be correct way for tha t.
[1] https://github.com/pcengines/coreboot/pull/132/files
Best Regards,
Piotr Król Embedded Systems Consultant https://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE-----
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Piotr Król -
Youness Alaoui